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[Untitled]

Authors :
Carl V. Thompson
Syed M. Alam
Donald E. Troxel
Source :
Analog Integrated Circuits and Signal Processing. 35:199-206
Publication Year :
2003
Publisher :
Springer Science and Business Media LLC, 2003.

Abstract

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.

Details

ISSN :
09251030
Volume :
35
Database :
OpenAIRE
Journal :
Analog Integrated Circuits and Signal Processing
Accession number :
edsair.doi...........13ee87a7190a5b7179210f45622c3eca