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In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

In this study, we used simulation technique to analyze the thermal characteristics of solo TGV (through-glass via) structure and solo TSV (through-silicon via) structure. The analysis showed, no matter in in-plane direction or in cross-plane direction, the thermal conductivity of a TGV structure is much lower than that of a TSV structure. Also, using simulation, we chose a typical 2.5D IC SiP (system in package) to compare the thermal performances between the SiP with TGV interposer and TSV interposer by using simulation. The specific via structures of 30μm in diameter and 60μm in pitch were adopted in the case studies. The results show the thermal performance of the 3D IC system with TSV is slightly better than that of the system with TGV, but both performances are nearly equal. The evaluations demonstrate the ultra-low thermal conductivity does not damage the thermal performance of a 3D IC SiP with TGV interposer; and proves the feasibility of the glass interposer for electronics applications.

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3DIC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding compound (SMC) was used to achieve the assembly of ultra-thin chip stacking module. The feasibility of this novel assembly was demonstrated and some process issues were also discussed in this investigation.

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of CMOS image sensor is temporarily bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. After thinning process, the backside is permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. By using a special trim from glass step, the temporarily bonded silicon carrier could be removed. Cu/Sn micro-bump is then fabricated at the front-side of the CMOS image sensor. No TSVs are needed in the proposed structure. A 300 mm silicon wafer with micro bumps bonded on 500 μm-thick glass wafer is demonstrated. Void free bonding is obtained by IR inspection both in temporary bonding and permanent bonding processes. The thickness of the silicon wafer is measured by IR system and the average thickness of the silicon wafer is 6.4 μm. After thinning, 1 μm TTV is obtained because the thermal plastic material flow during bonding process resulted in excellent planarization. From the cross sectional SEM image, Cu/Sn micro bump with thickness 4 μm/5 μm is formed at the front-side of the CMOS image sensor. The run-out issues from CTE mismatch is also discussed in this study.

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.

Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very difficult since thin wafers lose the supporting strength. Usually, the thin wafer is attached to a supporting wafer with adhesive to increase its rigidity and bending stiffness. Thus, adhesive is the key enabling material for thin-wafer handling, and how to select adhesive materials for temporary bonding and de-bonding is the focus in this study. Two sizes of wafers are considered; the 200mm wafers are used to find out the important and unimportant parameters in selecting the adhesive and then apply them to the 300mm wafers. It will be shown that wafer thinning and PECVD (plasma enhanced chemical vapor deposition) in vacuum chamber are the two critical steps for thin-wafer handling. The 300mm wafers are thinned down to 50μm and evaluated in different structures including: (a) blanket wafers, (b) wafers with 80μm solder bumps, and (c) wafers with 20μm micro-bumps and TSVs in 10μm diameter and 40∼50μm pitch. Based on this study, a set of useful process guidelines and recommendations is provided.

In this study, a three-dimensional (3D) integrated circuit (IC) chip stacking structure with a through-silicon via (TSV) is proposed. A high aspect ratio, void-free Cu electro-plating technology was achieved through super filling. The aspect ratio of the TSV was larger than eight. For chip stacking, Cu/Sn micro bumps with diameters less than 20 μm were used. Solder shape prediction using surface evolver showed good correlation with experiment results within a 2.5% error. Thin wafer handling technology with thermal plastic material was also adopted in this paper. The outgassing issue for silicon dioxide (SiO 2 ) was improved dramatically when an additional silicon nitride (Si 3 N 4 ) film deposition was made. Using the slide-off method with thermal plastic thin wafer handling material, an eight-inch wafer with a thickness of less than 50 μm was processed. After the die-saw process, ten chips could be stacked using the die bonder. Thermal cycling reliability test was also conducted with the temperature ranging from −55 to 125 oC. The reliability life for the proposed structure was 3,777 cycles from the Weibull plot. The average resistance for one interconnection was less than 50 mΩ. A 3D finite element model was also established in this study. The CTE mismatch between the polyimide and the silicon resulted in warpage. The simulation results showed that the maximum von Mises stress occurred at the corner of the TSV which could lead to a failure mode called “copper pumping.” For the von Mises stress in the micro bump, the maximum value occurred between the inter-metallic compound and the substrate copper pad. From the cross-sectional SEM image of the failed sample after thermal cycling test, the failure mode had good correlation with the simulation results. Equivalent plastic strain was around 0.11% in this simulation. As both silicon substrate and silicon chips were used in this study, a small equivalent plastic strain is expected.