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Ferroelectric (FE)-HfO2-based FETs (FEFETs) are one of the most promising candidates for emerging memories. However, the FE material suffers from a unique reliability phenomenon known as imprint: the coercive voltage shifts during data retention, which has been regarded as a major issue for memory operation, while the mechanism causing it is still under research. In this article, imprint and its recovery in FE-HfO2 are investigated in detail by comprehensive electrical measurements to reveal its underlying mechanism including the cause of asymmetric coercive voltage shifts. The recovery measurements clarify that domain switching is indispensable for the recovery from imprint. The subloop imprint effect shows that imprint and its recovery must be independent for each domain. In addition, switching time measurements and corresponding fitting results with the nucleation-limited-switching (NLS) model strongly indicate that imprint is caused by domain-seeds-pinning. Based on these results, we conclude that charge trapping and detrapping affecting activation barriers for domain switching, accompanied by domain switching, is responsible for imprint and its recovery.

The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects.

integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850°C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL’s grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E’ defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300°C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900°C oxide.

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ( $i$ ) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

We correlate the concentration and configuration of electrical defects in ferroelectric Si -doped HfO 2 (FE- HfO 2 ) with the electrical device performance during wake-up and fatigue regimes. To this end, we combine time-to-breakdown (TDDB), Kelvin probe force microscopy (KPFM), conductive atomic force microcopy (C-AFM) and Scalpel SPM, probing for the first time, the nanoscopic material variations as a function of device's field cycling behavior.

The electrical performance and reliability of MOSFETs and charge-trap flash memories are influenced by the traps in the gate dielectric. Trap properties depend on the atomic structure of the dielectric and are thus expected to be affected by mechanical stress, which modifies the bonds between atoms. Consequently, the mechanical stress, either engineered or created as a side effect of fabrication, needs to be considered in order to improve the device performance and reliability. This work demonstrates a systematic and controlled experimental study of the trapping process in individual gate oxide defects under externally applied mechanical stress. The significant and reversible impact of the mechanical stress on the trapping behavior is demonstrated and a theory to explain the observations is proposed.

While the bias temperature instability has provided many puzzles for more than half a century, the observation that bipolar (+V g /-V g ) AC stress can lead to larger degradation than DC or unipolar (V g /0) AC NBTI/PBTI combined, is particularly mysterious. Interestingly, similar observations have been made for oxide breakdown and hot carrier injection. Both have been linked to accelerated hydrogen release from the oxide under alternating positive and negative bias which then causes the creation of near-interface states. Based on these observations, we investigate the phenomenon from the perspective of the recently proposed gate-sided hydrogen release model for BTI. We suggest a mechanism which can explain the accelerated degradation observed during bipolar AC stress and investigate and validate possibilities for mitigating the effect by reducing the oxide volume from which H is released.

Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.

GaN-channel based transistors are ideally suited for RF/5G applications and also provide the promise of monolithic integration on a conventional Si-platform. Due to the wide scope of high electron mobility GaN transistor architectures, their reliability assessment is essential to ensure their successful deployment in low-power applications such as mobile computing devices, as well as high-power applications such as autonomous vehicles and base stations. We identify the most important DCreliability metrics necessary for fair benchmarking of future GaNon-Si RF transistors. A detailed analysis of the shortlisted DCreliability parameters for three device types, namely MOSFETs, MOSHEMTs/MISHEMTs and HEMTs is presented. MOSHEMT/MISHEMT is identified as the most robust device architecture, due to the presence of a barrier layer alleviating the impact of certain degradation mechanisms. Defect distributions in the gate-stack of MOS devices are extracted using defect band modelling technique. MOSHEMT devices are shown to undergo negative and positive Bias Temperature Instability (BTI) under specific ranges of positive gate-overdrive, thereby demonstrating the importance of correctly estimating the oxide field for MOSHEMT devices. Degradation map methodology is partially developed to distinguish the different gate-oxide degradation mechanisms and model the device lifetime pertaining to each of the mechanisms.

© 2019, Springer Science+Business Media, LLC, part of Springer Nature. Dangling bond defects (DBs) in silicon-passivated (1- or 3-nm thick Si cap) strained-(100)Si 1−x Ge x (x = 0.25–0.55) layers at interfaces with 1.8-nm thick HfO 2 gate dielectric are studied by means of Electron Spin Resonance (ESR) spectroscopy. The results suggest a dominant contribution of Si DBs (P b0 centers), a considerable fraction of which is located at the interface between the Si substrate crystal and the pseudomorphic Si 1−x Ge x film. The density of Si DBs in the Ge containing samples is significantly lower than at the reference (100)Si/ HfO 2 interface and decreases below the ESR detection limit (≈ 0.8 × 10 11 cm −2 ) with increasing thickness and Ge concentration in the Si 1−x Ge x layer. However, the beneficial effect of Ge becomes less pronounced when the thickness of the Si cap is reduced to 1 nm or in the case of direct deposition of HfO 2 on top of uncapped Si 1−x Ge x . From these observations we conclude that DBs are eliminated due to in-diffusion of Ge from the Si 1−x Ge x channel into interfacial Si layers, bringing the concentration of Ge to the range in which generation of Si DBs becomes energetically unfavourable, in agreement with previous observations on condensation-grown Si 1−x Ge x layers. ispartof: JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS vol:31 issue:1 ispartof: location:FRANCE, Strasbourg status: Published online

A common approach to incorporate workload dependent aging in circuits is to use an effective stress time or so-called signal probability (SP) to calculate degradation under realistic workload scenarios. However, this approach is not fully physics-based and incurs erroneous estimation of degradation. Moreover, cycle-accurate (CA) simulations are computationally expensive. In this paper, a relatively fast yet accurate, adaptive waveform splitting (AWS) algorithm is proposed to enable fast calculation of workload-dependent device aging. The proposed algorithm has been adopted to perform aging estimation of large circuits under specific workload scenarios.

For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

We present a kinetics-based analysis of the steep slope operation of ferroelectric (FE) FETs built on (i) a statistical multidomain nucleation-propagation mechanism of FE polarization switching and (ii) charge trapping in the high- K FE oxide. With a hardware-validated compact model we predict the change in hysteresis direction, the steep slope and the transient behaviors observed in our I-V measurements on Hf 0 5 Zr 0 5 O 2 -based planar n-FEFETs. We find that the proposed field-independent propagation is essential in explaining the measured reverse-sweep steep slope and transient current drift. Furthermore, the model suggests that a higher polarization and accordingly a larger I-V hysteresis are induced upon increased trapping. Finally, we show that for hafnia-based FE oxides, reliability engineering of defect band is needed for obtaining steep slope in scaled logic-FEFETs.

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology.

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

Response of a metal\ferroelectric Hf 0.5 Zr 0.5 O 2 \metal capacitor to an arbitrary excitation is investigated by polarization reversal curves and switching speed characterization. Results are explained in a steady-state Preisach as well as a modified transient NLS model framework. Applicability and limitations of each model are discussed. Switching speed measurements are found to be sensitive to parasitics. Separation of the intrinsic behavior from parasitics indicates the upper bound of the characteristic time constant of polarization switching speed is around 80ns in our sample.

To study charge trapping kinetics of oxide and interface defects, BTI and RTN measurements are typically performed. However, characterizing and investigating a statistically meaningful set of single defects is time consuming and inefficient at the single device level. To mitigate this, here we employ integrated arrays of nano-scale devices and characterize several thousands of single devices on a custom-made chip. We extract defect statistics from the threshold voltage shifts arising from single defects in individual transistors using the defect-centric approach. Finally, we also perform TCAD simulations to replicate the measurements and verify the array measurement scheme.

IEEE We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the gate work function. However, experimental data on capacitors show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metals with the dielectric, which yields different defect profiles depending on the process thermal budget, and not to the gate work function per se. This observation is confirmed by comparing BTI degradation in nMOS and pMOS Replacement Gate planar transistors with three selected work function metal stacks (representative of high-, standard, and low-Vth device flavors), and two different process thermal budgets. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that, on top of the unavoidable chemical interaction of different metals with the underlying SiO2/HfO2 dielectric stack, different gate work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs. ispartof: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY vol:19 issue:2 pages:268-274 ispartof: location:CA, Tahoe status: published

The mechanism of imprint in FE-HfO 2 is investigated in detail. It is clearly shown that the imprint can be recovered by additional pulses and domain switching is indispensable for the recovery. The results from sub-loop measurement suggest that the imprint of each domain can be considered to be independent. Switching time measurements reveal that the imprint is well described by the nucleation limited switching kinetic model. In addition, a clear correlation between imprint and gate leakage current is successfully demonstrated. Based on these results, a model for imprint is proposed.

Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate interface dipole engineering to suppress the carrier-defect interaction and achieve sufficient nMOS PBTI and pMOS NBTI reliability without the customary post-deposition anneals.

Degradation mechanisms, such as Bias Temperature Instabilities (BTI) and Hot Carrier Degradation (HCD), as well as the associated time-dependent variability, dictate the limit on the acceptable operating voltage conditions in modern deeply-scaled VLSI devices. Based on large statistical datasets, acquired using specifically designed on-chip arrays, we experimentally obtain DC degradation maps for both $\boldsymbol{n}$ - and $\boldsymbol{p}$ -type FETs. Defect-centric based analysis of the statistical parameters at every $\boldsymbol{V_{G}}, \boldsymbol{V_{D}}$ bias point provides physical insights in the underlying single- and multi-carrier degradation processes. As a result, we can separate the defect charging contributions of each degradation mechanism and describe to which extent these mechanisms co-interact. We finally present a simplified model (the “3-bucket” model) that is able to describe the degradation statistics up to $3\boldsymbol{\sigma}$ of a device population subject to an arbitrary combination of BTI and HCD stress.