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Short-channel Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) often utilize T-shape gates due to their large gate-line cross-sectional area and subsequent fMAX increase. In this paper, we report the linearity trade-offs associated with varying the T-gate geometries of AlGaN/GaN HEMTs on Si, specifically the gate extensions which serve as field plates and their impact on the large-signal performance. Small-signal characterization and modeling, in addition to TCAD, provide initial guidelines for the optimal dimensions for the gate field plates using the ratio of fT and the product of the gate resistance and the gate-to-drain capacitance. We utilize various characterization methods, including 6 GHz non-linear vector network analyzer characterization in addition to load-pull, to quantify the amplitude and phase distortion and their subsequent impact on the large-signal metrics of the devices under differing matching conditions and bias points. We deduce that the influence of the gate field plates on the amplitude and phase distortion is non-negligible, particularly under matched conditions.

This paper explores the potential game properties of the non-cooperative finite-horizon general-sum Linear Quadratic (LQ) game. We show that a general LQ game is potential if and only if it is an identical interest game. Based on this result, we restrict the class of LQ games to those with decoupled agent dynamics and information structure. For this restricted subset, we derive conditions under which the game is potential. Furthermore, for the identified subset, we prove the convergence of policy gradient to a Nash equilibrium., Comment: Submitted to CDC Conference

We extract an AlGaN surface state spectrum with a density ( ${D}_{\text{SS}}$ ) ranging between $1.4\times10$ 12 and $4.7\times10$ 12 eV−1cm−2. The low ${D}_{\text{SS}}$ is achieved with in situ SiN passivation. ${D}_{\text{SS}}$ is extracted from ungated AlGaN/AlN/GaN heterostructures with varied AlN thicknesses between 0 and 2 nm: increased AlN thicknesses in heterostructures monotonously increase two-dimensional electron gas (2DEG) densities ${N}_{\text{sh}}$ and AlGaN surface potential energies ${q} {\varphi } _{\text{s}}$ , and ${D}_{\text{SS}}$ is extracted with $\boldsymbol {\Delta } {N}_{\text{sh}}$ – $\boldsymbol {\Delta } {\varphi }_{\text{s}}$ correlations. The ${D}_{\text{SS}}$ extraction methodology in this work features calibrated polarization charge values, Hartree approximation-based 2DEG profile calculation, and incorporated C-doped GaN (C-GaN) substrate impact on 2DEG. We also extract the charge neutrality level at the AlGaN surface, which is ~0.95 eV below conduction band minimum.

We investigate the effect of varying the gate-to-drain spacing and the gate field-plate on the device linearity of GaN HEMTs on Si for 0.11μm, 0.15μm, and 0.19μm gate lengths. The gain compression, phase distortion, and harmonic distortion metrics are measured using a nonlinear characterisation setup calibrated at 6GHz up to the third harmonic. The acquired nonlinearity metrics are correlated with the extrinsic device parasitics extracted from S-parameter measurements. We observe that excessive gate field-plate length scaling down to 0.05μm lowers the total phase distortion at the expense of gain linearity and harmonic distortion in Class AB while minimising the gate-to-drain spacing alleviates the harmonic distortion only for devices of 0.19μm gate length. Further evaluation, under matched conditions, using a passive load-pull measurement setup points to a decline in the peak achievable PAE and PSAT at gate field-plates smaller than 0.12μm.

In this paper, Gallium Nitride (GaN) Metal-Insulator-Semiconductor (MIS)-HEMTs are compared with conventional Schottky Metal-Semiconductor HEMTs in terms of DC and ESD performance. Measurement results indicate TLP failures are highly related to 2DEG channel driving capability. The impacts of different gate interfaces in the GaN (MIS)-HEMTs on failure mechanisms are the key factor of final ESD robustness.

Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counterparts. An example can be a hybrid beamformer where GaN HEMTs can enable much smaller antenna array and therefore a smaller system form factor. For 5G wireless applications, standalone or co-integrated GaN HEMT based FEMs can lead to a more energy efficient and compact system as compared to standalone Si-CMOS technologies. However, for both amplifiers and switches, GaN-on-Si HEMTs present thermal management and substrate loss related issues. In this work, we study and model the impact of GaN HEMT integration on Si substrate on RF substrate losses and non-linearities. The growth of III-N buffer is the most significant factor in determining RF losses and harmonic distortion contribution from the substrate. High temperature annealing and ion implantation steps encountered during HEMT processing can also degrade the substrate performance. In addition, we demonstrate a direct co-relation between substrate losses and harmonic distortion analogous to silicon-on-insulator technologies (Figure 1). However, the bias dependence of RF losses and harmonics show a strong time dependence (memory effects) which is more complex to model [11]. We discuss the approaches to understand and model these effects. References: [1] H. W. Then et al, IEEE IEDM Tech. Dig., 2021, pp. 230-234. [2] B. Parvais et al, IEEE IEDM Tech. Dig., 2020, pp. 155-158. [3] W. E. Hoke et al, J. Vac. Sci. Technol. B 30, 02B101 (2012). [4] Drillet F et al, IJMWT 13, 517–522, 2021. [5] L. Cao et al, CSMANTECH conference Tech. Dig., 2020. [6] Roda Neve et al, IEEE TED, Vol. 59, NO. 4, pp. 924-932, 2012. [7] S. Yadav et al., in IEEE IEDM Tech. Dig., 2020, pp. 159-162. [8] Rack et al, ECS Trans., 92 (4), pp. 79-94, 2019. [9] Zhu et al, IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 377–379, 2018. [10] Raskin et al, IEEE SiRFIC, 2015. [11] P. Cardinael et al, IEEE ESSDERC 2021, pp. 303-306. Figure 1

High-temperature processing steps are frequently used in manufacture of AlGaN/(AlN/)GaN high electron mobility transistors (HEMTs). The thermal budgets drive Al diffusion into the GaN channel, increase alloy disorder scattering (ADS) of the two-dimensional-electron-gas (2DEG), and degrade the 2DEG mobility. By correlating the ADS to device thermal budget, we propose an analytical model to calculate the ADS limited mobility as a function of Al diffusion lengths (LD,Al) in AlGaN/(AlN/)GaN HEMTs. The simulation indicates that the ADS is a significant mobility degradation mechanism whose scattering rate increases with the 2DEG density and the LD,Al. The findings explain the generally observed trends in the literature that the 2DEG mobility and sheet resistances of GaN heterostructures degrade with increased thermal budgets, especially after >900 °C processing.

We introduce a set of new characterization techniques for the direct defect analysis of the sidewall surfaces of Nano-ridge, Nanowire, and FinFET based devices, being used in current (and future) logic and RF technologies. We demonstrate the application of these techniques on GaAs mesa, Nano-ridge, and InGaAs nano-wire based PIN diodes where surface defect densities are difficult to extract currently. We show that a close match in extracted density, with both measured data and calibrated TCAD simulations of above device types, is achieved validating the applicability of the techniques.

We report on the development of mm-wave GaN-on-Si AlGaN HEMTs integrated with a 3 level Cu damascene BEOL flow on 200mm Si wafers. Optimizations of the gate metal stack, contact resistance and gate length scaling to 110nm result in devices with a peak g m of 430 mS/mm and an f MAX of 135 GHz. While wafer warp was found to increase slightly through the processing of 3 levels of 1µm thick Cu metal, no significant deterioration was observed between devices measured at Metal 1 and Metal 3.

GaN-channel based transistors are ideally suited for RF/5G applications and also provide the promise of monolithic integration on a conventional Si-platform. Due to the wide scope of high electron mobility GaN transistor architectures, their reliability assessment is essential to ensure their successful deployment in low-power applications such as mobile computing devices, as well as high-power applications such as autonomous vehicles and base stations. We identify the most important DCreliability metrics necessary for fair benchmarking of future GaNon-Si RF transistors. A detailed analysis of the shortlisted DCreliability parameters for three device types, namely MOSFETs, MOSHEMTs/MISHEMTs and HEMTs is presented. MOSHEMT/MISHEMT is identified as the most robust device architecture, due to the presence of a barrier layer alleviating the impact of certain degradation mechanisms. Defect distributions in the gate-stack of MOS devices are extracted using defect band modelling technique. MOSHEMT devices are shown to undergo negative and positive Bias Temperature Instability (BTI) under specific ranges of positive gate-overdrive, thereby demonstrating the importance of correctly estimating the oxide field for MOSHEMT devices. Degradation map methodology is partially developed to distinguish the different gate-oxide degradation mechanisms and model the device lifetime pertaining to each of the mechanisms.

The impact of the short gate length on the drain current and low frequency (LF) noise in GaN/AlGaN metal-oxide-semiconductor high-electron-mobility field-effect-transistors has been studied. In some short devices, a parasitic subthreshold current is observed. In this article, the origin of parasitic subthreshold currents were explored using LF noise and trapping transient measurements. The LF noise power spectral density (PSD) of the devices without parasitic drain current decreased monotonically with the decrease of the drain current, while the PSD of the device with the parasitic drain current strongly increased for lower drain current. The 1/f 1.5 noise corresponding with the parasitic leakage can be explained by the level broadening of generation-recombination centers in the GaN channel. This is confirmed by the trapping transient measurements, revealing a temperature-independent time constant, associated with the leakage path in short channel transistors, exhibiting the subthreshold humps.

We report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance tradeoffs, limitations and solutions. The main highlights of process optimization include low RF transmission loss (0.15 dB/mm at 20 GHz), state-of-the-art contact resistance (R C ) of 0.14 Ω mm for a non-Au, low thermal budget ( BD ) of >300 V (pre and post device processing). We show that MISHEMTs, which feature the highest field effect mobility (μ FE ), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation.

The basic analog parameters of three splits of In x Ga1– x As nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO2/1-nm Al2O3 gate. The low equivalent oxide thickness improves the electrostatic coupling, enhancing ${I}_{{\text {DS}}}$ , and, consequently, also gm and ${A}_{V}$ , especially for higher $\text {V}_{{\text {GS}}}$ . The InGaAs tunnel field-effect transistors (TFETs) show compatible performance with Si TFETs, and have better performance than Si MOSFETs, making them useful for low-power and low-voltage analog applications. The highest efficiency is found using the combination of a 2-nm HfO2 with In0.53Ga0.47As, due to the 56-mV/dec subthreshold swing obtained. For all splits, the ${A}_{V}$ peak can be related to the ${V}_{{\text {GS}}}$ necessary for band-to-band tunneling to become the dominant transport mechanism.

We have validated that the electrical performances of the In0.53Ga0.47As MOSFETs such as sub-threshold slope (SS) and electron mobility were dependent on interfacial reactions in the metal/highk/InGaAs gate stacks which could be controlled remotely by choice of the metal electrodes. We demonstrated In0.53Ga0.47As MOSFETs with high mobility (peak mobility ~1300 cm2/Vs) and superior SS performance (SS 76.4 mV/dec) at the scaled CET region owing to the remote reduction of the native III-V oxide by the TiN electrodes.

In this work, deep levels present in n-type In0.53Ga0.47As hetero-epitaxial layers grown lattice-matched on n-type InP substrates by molecular beam epitaxy have been studied by deep-level transient spectroscopy (DLTS). Metal–oxide–semiconductor capacitors are employed, based on an Al2O3 gate oxide. It is shown that a single, near mid-gap electron trap dominates the DLT-spectra, whatever the surface pre-or post-gate oxide deposition treatment. At the same time, it is shown that the deep level parameters vary significantly from capacitor to capacitor and from wafer to wafer. Only after Forming Gas Annealing, a stable value for the activation energy of 0.39 ± 0.01 eV is obtained. These results are tentatively interpreted in terms of antisite defects in the epitaxial layer, which form a family of related complexes with close deep-level parameters.

We report the universal boosting impact of a true negative capacitance (NC) effect on digital and analog performances of Tunnel FETs (TFETs), mirrored for the first time in near hysteresis-free experiments and exploiting the S-shaped polarization characteristics. Well behaved InGaAs TFETs with a minimum swing of 55 mV/dec at room temperature are combined with high-quality single crystalline PZT capacitors, placed in series with the gate. When fully satisfying the exact NC matching conditions by a single crystalline ferroelectric that can perform a mono-domain state, a hysteresis-free (sub-10mV over 4 decades of current) NC-TFET with a sub-thermionic swing and an SS min of 40 mV/dec is demonstrated. In other devices, improvement in the subthreshold swing, down to 30 mV/dec, and analog current efficiency factor, up to 180 V−1, are achieved in NC-TFETs with a hysteresis as small as 30 mV. Importantly, the I 60 FoM of the TFET is improved up to 2 orders of magnitude. The supply voltage is thereby reduced by 50%, down to 300 mV, providing the same drive current. Our results show that NC can open a new direction as a universal performance booster in the FET design by significantly improving the low I 60 and low overdrive of TFETs.

We study the positive bias temperature instability (PBTI) of InGaAs tunnel-FETs (TFETs) with two different indium fractions (53% and 70%) and compare with reference MOSFETs, using the same gate stack. While identical threshold voltage instability is found irrespective of the device type, the subthreshold swing (SS) of the TFETs is found to be more robust against PBTI as compared with MOSFETs. With the aid of comprehensive TCAD simulations, we show that the SS of a TFET is intrinsically less sensitive to interface/oxide border traps, thanks to the narrow energy range swept by the channel Fermi level during the OFF-to-ON transition of the device operation. Moreover, only traps located within $\sim 20$ nm from the tunnel junction can affect the SS.

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection.

A simple analytical low-field electron mobility model to be employed for technology computer-aided design of thin-body MOSFETs based on III-V compound semiconductors is presented. The scattering sources accounted for in the model are Coulomb centers, lattice vibrations (i.e., phonons), and surface roughness. The dependence of the thin-body effective thickness on the transverse electric field is calculated through 1-D Schrodinger–Poisson numerical simulations and is introduced in the model by means of an appropriate analytical function. Then, the free-electron density distribution is determined by considering both quantization effects and oxide–semiconductor interface traps. The model is calibrated on the experimental data collected on In0.53Ga0.47As-on-InP thin-body MOSFETs featuring body thicknesses as low as 5 nm. In particular, the model accurately reproduces $C_{G}$ – $V_{\mathrm{ GS}}$ characteristics, effective mobility against inversion layer charge plots, and $I_{\mathrm{ DS}}$ – $V_{\mathrm{ GS}}$ curves at low $V_{\mathrm{ DS}}$ .

This correspondence highlights that the Gibbs free energy description of a ferroelectric capacitor in series with a paraelectric capacitor, depends on the initial charge on the plates of the ferroelectric capacitor. An incomplete Gibbs free energy description, as in the original manuscript, leads to an incorrect simulation result. Therefore, a fully comprehensive analytical description and a corrected conclusion concerning the particular point of an increase in apparent coercive voltage in the steep-slope ferroelectric tunnel-FET, are presented.

The growing interest for 5G radios pushes technology development towards low-cost and high-performance solutions for operating at microwave and mm-wave. Downscaling CMOS technology has allowed the integration of high-speed transceivers on silicon chips, but high-power amplifiers rely on III-V technologies to deliver the power and efficiency levels required by modern radios. In this work, we motivate the interest of non-Si technologies to meet 5G requirements, and we explore two routes to enable the fabrication of compound semiconductor devices on a large-scale manufacturable Si platform [1,2]. We provide insight on the potential of these new technologies for the design of advanced front-end modules, including modelling and reliability challenges. In the first route (Figure 1(a)), we report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance trade-offs, limitations and solutions. State-of-the-art contact resistance of 0.14 Ω.mm is demonstrated for a non-Au, low thermal budget (oC) contact scheme, as well as a high vertical breakdown voltage (VBD) of >300 V. We show that MISHEMTs, which feature the highest field effect mobility (μFE), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation. The GaN-on-Si substrate optimization for low RF losses and nonlinear distortion is further discussed. The second route (Figure 1(b)) includes the formation of HBT on Si wafer by selective epitaxy. We demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BVCBO, of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate. Figure 1

Pocketed vertical nanowire InGaAs/GaAsSb tunnel FETs (TFET) with sub-threshold swing (SS) reaching 47 mV/dec are demonstrated. The achieved sub-threshold performance is the steepest reported so far for a top-down TFET in the III-V material system. Smooth vertical wires with diameters as narrow as 30 nm are achieved using a CH 4 based dry etch process. Drive current at 0.35 V supply voltage approaches 0.7 μA/μm for a fixed I off of 1 nA/μm.

We report high performance, dry etched In 0.53 Ga 0.47 As vertical nanowire and vertical nanosheet devices, fabricated using a VLSI compatible process flow. Scaling the effective-oxide-thickness in combination with (NH4)2S channel treatment and forming gas anneal improves the device performance, in terms of Q (Gm/SS), by over 55%. At V DS = 0.5V, the devices exhibit a minimum SS = 63mV/dec, I on = 397μA/μm at Ioff = 100nA/μm, peak Gm = 1.6mS/μm and maximum Q = 21. These values are the best reported in literature for vertical IIIV devices. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the process flow does not introduce additional interface defects.

While the issues of Fermi level pinning by interface states at the dielectric/semiconductor interface has first attracted the concern of device engineers working on high-mobility channel devices, more and more attention is going nowadays to the so-called border traps (BTs) at some distance from the interface in the gate dielectric. According to their definition [1] they are able to communicate with the inversion layer in a MOS devices with time constants on the order of 1 ms and higher. As such, they will contribute to the frequency dispersion and hysteresis in capacitance-voltage and transconductance characteristics [2] and generally dominate the low-frequency noise spectrum [3]. Historically speaking, the 1/f noise in MOSFETs has always been interpreted in terms of trapping/detrapping towards BT (Fig. 1), whereby in many cases, pure elastic tunneling was assumed, yielding a simple relationship between the trap depth z and the noise frequency f, which is based on the tunneling parameter at. The latter mainly depends on the tunneling barier Φit at the interface and the tunneling effective mass mox [3]. Based on that, several methods to derive a BT density profile from a noise spectrum have been developed; an example is given in Fig. 2 for the spectrum obtained on a Si-passivated Ge pMOSFET. It is the intension of this work to illustrate the 1/f noise method for oxide trap profiling in high-mobility channel devices with a high-k gate stack. As shown in Fig. 3 for InGaAs/InP/Al2O3 nMOSFETs, quite uniform trap density profiles have been obtained, irrespective of the architecture, i.e., buried channel with InP cap or surface channel (InP etched) or the use of surface passivation with S [4]. On the other hand, the absolute value of the trap density strongly depends on pre- and post-high-k deposition treatments. While there is quite some literature on the LF noise of Ge pMOSFETs with silicon passivation, little results have been reported on alternative gate stacks or n-channel Ge MOSFETs. As shown in Fig. 4, the noise spectrum for a Ge nMOSFET with GeOx/Al2O3/HfO2 gate stack is close to 1/f, yielding a uniform profile, according to the constant fxSI function. It corresponds with a high NBT in the range of 6×1019 cm-3 eV-1, indicating a rather poor gate stack quality [5]. Finally, the impact of inelastic tunneling in the modeling of BT profiles from 1/f noise spectra will be discussed and a possible internal depth versus frequency calibration will be outlined [6]. References [1] D.M. Fleetwood, IEEE Trans. Nucl. Sci., 39, pp. 269-271 (1992). [2] D. Lin et al., in IEDM Tech. Dig., The IEEE (New York), pp. 645-648 (2012). [3] E. Simoen, H.-C. Lin, A. Alian, G. Brammertz, C. Merckling, J. Mitard and C. Claeys, IEEE Trans. Device and Mater. Reliability, 13, pp. 444-455 (2013). [4] M. Scarpino, S. Gupta, D. Lin, A. Alian, F. Crupi, and E. Simoen, IEEE Electron Device Lett., 35, pp. 720-722 (2014). [5] W. Fang, E. Simoen, H. Arimura, J. Mitard, S. Sioncke, H. Mertens, A. Mocuta, N. Collaert, J. Luo, C. Zhao, A. Thean, and C. Claeys, submitted for publication in IEEE Trans. Electron Devices. [6] E. Simoen, J.W. Lee and C. Claeys, IEEE Trans. Electron Devices, 61, pp. 634-637 (2014). Figure 1

In this work, the impact of the Zn diffusion processes in the source and the amount of Indium for In x Ga 1−x As nTFET was analyzed, focusing on the basic analog parameters. Three different splits were analyzed: In 0.53 Ga 0.47 As with Spin-on-Glass (SoG) Zn diffusion in the source, In 0.7 Ga 0.3 As using SoG and In 0.53 Ga 0.47 As with Gas Phase Zn diffusion in the source. The Ion increase of the Gas Phase device can be related to its higher source/channel junction abruptness that also reduces the tunneling length. The Gas Phase device has presented better subthreshold swing, which increases the transistor efficiency in the weak conduction regime. The Gas Phase device presents the lowest intrinsic voltage gain (A V )for high gate voltage (V GS ) values due to its significant output conductance (g D ) degradation However, the reduction of the temperature affects more g D than gm, resulting in an improvement of A V by more than 20 dB at 10 K for the Gas Phase device compared to both SoG splits.

In this work, the influence of the temperature and the different equivalent oxide thickness (EOT) of In 0.53 Ga 0.47 As nTFETs fabricated with gas phase Zn diffusion is analyzed. The different devices have in their gates stacks 3 nm of HfO 2 (with an EOT of 1 nm) or 2 nm of HfO 2 (with an EOT of 0.8 nm). The use of an EOT of 0.8 nm increases the band-to-band tunneling generation and also improves the subthreshold region characteristics, presenting a sub 60 mV/dec minimum subthreshold swing (56 mV/dec) at room temperature, resulting in better efficiency in weak conduction. Considering the temperature influence, the on-state current is less affected than the off-state current due to the band-to-band tunneling mechanism. In the subthreshold region the temperature decrease, which strongly reduces the off-state current, allows the band-to-band tunneling current to be more dominant, resulting in a better subthreshold swing and, consequently, a better transistor efficiency in the weak conduction regime. The opposite behavior occurs when heating the devices, reducing the influence of the band-to-band tunneling in the subthreshold region, degrading both the subthreshold swing and transistor efficiency in the weak conduction regime. In the strong conduction regime, the transistor follows the transconductance tendency, increasing for higher temperatures.

The low-frequency noise is studied in planar InGaAs channel nMOSFETs, with Al2O3 gate dielectric in combination with different pre- and post-gate treatments, namely, pre-gate TMA exposure or post-gate Forming Gas Annealing (FGA). It is shown that the oxide trap density is reasonably uniform in the gate stack between 1 and 2 nm from the interface, whereby a FGA yields a lower noise power spectral density compared with the TMA or untreated devices.

The relationship between the Threading Dislocation Density (TDD), the generation (τg) and recombination lifetime (τr) in relaxed n-type In.53Ga.47As is investigated for a series of p+n junction diodes, containing an TDD ranging from 105 to 1010 cm-2. The TDs are generated intentionally by lattice-misfit growth on Semi-Insulating (SI) InP and GaAs substrates. The lifetimes have been extracted from diode Current-Voltage (I-V) and Photoluminescence (PL) analysis showing that TDDs affect their values above a density of about 1×107 cm-2 (τg,E~0) and about 1×108 cm-2 (τr and τPL), which can be well-explained by the charged dislocation cylinder model. In addition, a detailed comparison between the results from Deep Level Transient Spectroscopy (DLTS) and from the diode characterization is performed, showing that the responsible G/R center shifts toward mid-gap in In.53Ga.47As and transfers from a native point defect (PD1) to a TD (E2/H1). Finally, the classical concept of generation lifetime and recombination lifetime in terms of dislocations is discussed based on the results.

The electrical activity of a defect in a semiconductor material is usually expressed in terms of the Shockley-Read-Hall (SRH) theory which provides an expression for the generation or recombination lifetime. Along the same lines, one can calculate the leakage current generated by a single defect in the depletion region of a junction, as shown in Fig. 1 [1]. It is clear that for III-V based ternary alloys, like the InxGa1-xAs system, the generation current depends proportionally on the intrinsic carrier concentration ni (see equation in Fig. 1). However, equally important is also the variation of the defect energy level ET as a function of the In content x: for ET pinned to the intrinsic Fermi level Ei(x), the leakage current will follow ni. On the other hand, when ET is pinned to either the valence or conduction band, the leakage current will decrease exponentially with the difference |ET-Ei| [2]. It is thus important to derive the variation of ET with alloy composition x for a certain type of defect and to establish what could be consideredas a kind of Vegard’s law for specific deep levels. In addition, when integrating III-V compounds on a silicon CMOS platform, extended defects will be inevitably introduced [3]; for a sufficiently high density, they will govern the reverse current [3,4]. It is thus of vital importance to study the electrical parameters of extended defects in III-V-on-silicon materials and their evolution with composition x. The aim of the this work is to review what is known about the electrical activity of extended defects in InxGa1-xAs-based hetero-epitaxial layers. Results will be described about a combined p-n diode current-voltage (I-V) and lifetime analysis on a set of nearly strain-free layers where x=0.53 with varying densities of extended defects [5]. Based on this, it is demonstrated that for an extended defect density exceeding ~2×107 cm-2 the SRH lifetime becomes dominated by a near mid-gap trap level, associated with them. A detailed Deep-Level Transient Spectroscopy (DLTS) analysis provides further information about the electrical activity of these extended defects and confirms the presence of a dominant electron trap. The corresponding activation energy is represented in Fig. 2 versus x and compared with available literature data. In addition, it is shown that this deep level indeed belongs to an extended defect, based on the electron capture behavior, varying approximately logarithmically with the capture time [4]. Moreover, it can be shown that the electron traps belong to a one-dimensional band-of-states, associated with a ‘perfect’ extended defect. According to Fig. 2, this level appears to follow approximately Ei(x), so that it will dominate the leakage current of a p-n junction over a wide composition range, at least up to 0.53, when present in a sufficient density. Moreover, the defects will become more efficient leakage centers for increasing x. Finally, the implications of the band-like nature of the energy states of extended defects on the carrier generation/recombination will be discussed. [1] J. Vanhellemont and E. Simoen, J. Electrochem. Soc, 154, H572 (2007). [2] E. Simoen, J. Lauwaert and H. Vrielinck, Semiconductors and Semimetals, Eds. L. Romano, V. Privitera and C. Jagadish, 91, pp. 205-250, Elsevier 2015. [3] E. Simoen, “Impact of defects on the performance of high-mobility semiconductor devices”, In: High Mobility Materials for CMOS Applications, Ed. N. Collaert, Elsevier, Ch. 5, July 2018. [4] C. Claeys et al., ECS J. Solid State Sci. and Technol., 5, P3149 (2016). [5] P.-C. Hsu et al., J. Appl. Phys., 124, 165707 (2018). Figure 1