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International audience; The study of parameter drift due to interface defect generation in “Off” mode or near Vth is very complex, because it is often concomitant with hot hole trapping which induces turnaround effects. Improving device aging models requires to consider hot-carrier degradation (HCD) in “On/Off states”, interaction of these different modes as well as any dynamic effects. The DC characterization of HCD modes might be insufficient, it is necessary to verify the quasi-static assumption made when we seek to model the degradation under realistic dynamic stress by a secession of static states. We present a detailed analysis of the interactions of HCD under “On” state and “Off” state”. Pulsed stressing are used to analyze the frequency dependence of HCD and “Off-state”. Such approach is required for accurate AC RF ageing modeling.

International audience; Extended Drain MOS (EDMOS) transistors were studied about hot-carrier (HC) degradation and its involvement in hard breakdown (BD) events as these smart power devices represent a big challenge to optimize under Off/On mode switching in RF circuits. N-channel devices with gate-length LG=0.5µm and two gate-oxide thicknesses were tested Tox= 2.3nm (GO1) and 8.5nm (GO2). The sensitivity to BD between Off-mode and HC is pointed out in GO1 through the hot-hole injections (HHI) that are involved as a function of gate-voltage VGS = VTH and VGmax where the VTH case induces HC damage that can be used with series resistance increase (RSD ) to detect BD events in the drift region. Hole trapping and interface traps are generated leading to the dominant effect of HHI, with very close generation rates between Off- and On- mode stressing. This can be used to prevent circuit aging giving warning level for confidence in AC lifetime for power amplifiers class E and class A.

International audience; Improving device aging models requires to consider hot-carrier degradation (HCD) between On/Off modes and interaction of these different damage rate mechanisms as well as the dynamic effects. As DC characterization of HCD modes might be insufficient, it is rather necessary to check the quasi-static validity when we seek to model the degradation under realistic dynamic stress by a succession of static states. We present a detailed analysis of the interactions of HCD under On and Off state in N-FETs devices using a compact modelling based on an empirical model. Pulsed stressing by measure-stress-measure method is further used to analyze the switching time dependence of HCD and Off modes for an accurate AC RF ageing modeling. This reliability methodology is useful to close the gap between the simple models used for DC HCD characterization and the degradation involved in power amplifiers under AC RF signals.

In this work, we have demonstrated that many elements are needed on top of conventional foundry reliability knowledge to enable robust automotive products in compliance with all restrictive norms. For intrinsic reliability, both reliability models (a design compatible WLR description), and dynamic aging compensation schemes are required. For extrinsic failures, screening procedures require well documented usage and are shown in use for volume production to bring the failure rate level down below 1 ppm automotive target. Altogether, the global approach developed in STMicroelectronics enable robust automotive products based on controlled and validated procedures.

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length LG = 0.5 μm, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain by an improved extraction of series resistance (ΔRSD) till a 2nd order mobility modeling as a function of stressing VGS from VGS = 0 to VGmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias V-B sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output device (EOT = 3.6 nm) to core blocks (EOT = 135 nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (I-on, V-T) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case. (C) 2016 Elsevier Ltd. All rights reserved.

This paper shows the advantages of using body bias. Experiments are performed in 14 nm and 28 nm UTBB FDSOI transistors and ring oscillators (ROs). The impact of body bias on performance and reliability is highlighted. The body biasing offers significant advantages for adapting the tradeoff between reliability and performance in logic circuits without changing the design margins. With FDSOI technology, we have an additional degree of freedom of process variability compensation by using body bias voltage (Adaptive Body Bias, ABB) next to supply voltage compensation used before. We show that ABB compensation technique presents better results for a complete power optimization.

International audience; This work demonstrates that up to 74% energy efficiency can be gained by combining Body-Bias Process, Temperature and Aging compensation schemes altogether. Thiscombination of compensation schemes offers the best energy efficiency gain as compared to recent results while guaranteeing high-level of robustness (

International audience; This paper proposes new physical explanations to explain altogether the impact of compressive strain, germanium content (in channel) and nitrogen content (in gate stack). Both compressive strain and Ge content impact on NBTI degradation is found to related to the modifications in the band structure in the channel. Excellent agreement between theory and experimental results shed new light on the NBTI degradation mechanism and the physics lying behind. Similarly, HCI degradation process dependences is well explained by the energy-driven model.

International audience; This paper shows new insights on the stochastic nature of aging-related timing impact in digital circuits. Varying critical paths through aging trigger the need for aging compensation control loop based on an unsupervised machine learning algorithm. Adaptive Resonance Theory (ART) algorithm is favored for its ability to handle the stability-plasticity dilemma.

International audience; New insights on the stochastic nature of aging-related timing impact in digital circuits trigger the need for aging compensation control loop. Such control loops enable additional 22% power savings but require dedicated safety measures (either margin or monitoring) to enable fault-free operations even in cases of out-of-specifications usage.

IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, APR 02-06, 2017; International audience; The ability to determine product failure rate at the design conception stage would serve as a feedback to the design teams to create robust designs. IP hardening leading to a long lasting reliable product portfolio is the need of the hour for the upcoming IOT and Smart Driving Markets. Conventional aged static timing analysis does not take into account the aging due to the digital circuit workload at operational lifetime and a degradation modulation of 2-3X is observed. But, workload dependent digital circuit reliability analysis has been made possible with models that predict the aged standard cell behavior for its corresponding operational stress. This paper thus leverages the workload dependent reliability analysis for early product failure rate calculations.

IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, APR 02-06, 2017; International audience; A novel control loop enables Dynamic Adaptive Voltage Scaling in a demonstrator with digital cores tightly coupled with monitors and Dynamic Controller. Control loop robustness is validated by Markov chains and experimental results. Monitors allow circuits to execute instructions from workloads in fault-free way with power savings up to 50%.

International audience; Endurance is investigated on one transistor floating body RAM cells processed on a silicon-on-insulator substrate with ultrathin buried oxide, and programmed using the bipolar junction transistor current inherent in MOSFETs. During the hole generation step, defects are generated close to the drain. These defects not only reduce the retention time but also result in a lower hole generation rate as a function of the number of cycles, which leads to a write 1 failure. We have shown that standard junction devices with a lightly doped drain (LDD) region are more enduring than extensionless devices with the LDD left undoped. This is owing to the poor spacer oxide on top of the extensionless region where holes are generated.

In this paper, we analyze the impact of Layout Dependent Effect (LDE) observed on MOSFETs. It is shown that changing the Layout have an impact on MOSFET device parameters and reliability. Here, we studied the Well Proximity Effect (WPE), Length of diffusion (LOD) and Oxide Spacing Effect (OSE) impacts on device MOSFET parameters and reliability. We also analyzed SiGe impacts on LDE, since it is commonly used to boost device performance.

IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, APR 17-21, 2016; International audience; This work demonstrates the fundamental aspects of Mission Profile Recording as an alternative to intrusive, aging monitoring systems to cope with oxide breakdown and electromigration degradation mechanisms. A functional prototype is designed, implemented and fully tested on several wafers to achieve a full proof-of-concept. This study offers new perspectives towards product hardening and qualification with respect to an adaptive approach to real user-based workloads.

International audience; This paper presents a theoretical framework about interface states creation rate from Si–H bonds at the Si/SiO2 interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two other cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability – CMOS device reliability in this case – at design stage thereby enabling judicious margins to be taken beforehand.

International audience; A large range of commercial deep submicron VLSI devices are used for avionic designs. Due to the scaling down, an ever higher level of integration and the use of new materials in foundries, the main failure mechanisms are changing while new ones appear. Lifetimes related to these failure mechanisms are suspected of being shorter and shorter so failure rate prediction becomes a great challenge for deep submicron (DSM) semiconductor reliability. We propose in this paper, a new approach based on technologies analysis in order to determine potential reliability risks regarding the specific use of DSM components for avionic applications.

International audience; A practical and accurate Design-in-Reliability methodology has been developed for designs on 90–65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes.

International audience; In this paper, we confirm that the energy is the driving force of hot-carrier effects. In high-energy long-channel case, the energy-driven paradigm allows to retrieve lucky electron model-like equations although the explanations are different. When the energy is lowered, high-energy electrons generated by electron–electron scattering become the dominant contribution to the degradation. Finally, for even lower energy, multiple vibrational excitation mechanism starts taking the lead.

International audience; For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Then Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.

International audience; Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.

International audience; Permanent damage induced by Channel Hot-Carrier (CHC) injections have been distinguished from the charge-discharge of near-interface traps in ultra-thin gate-oxide (1.6nm) MOSFETs. It is shown that usual DC accelerating techniques mostly devoted to CHC damage at large voltage conditions cannot be used alone for low supply voltage (VDD= 1V) MOSFETs. This arises from the charging of slow traps which induces a worst-case of damage which is relaxing in different ways depending on the discharging bias and cold phases. This is particularly more severe under hole injections in P-channel than under electron injections in N-Channel MOSFETs in relation to the smaller mobility of holes and to the gate-oxide nitridation which induces deep traps from the oxide valence band. The true effects of the distinct damage and relaxations are further analyzed using AC stresses which are required for the worst-case determination in advanced logic circuits. This is further evidenced by the determination of the effective quasi-static time factors dependent on the alternated damaging, discharging, and relaxing periods involved in ultra-thin gate-oxide MOSFETs operating at low voltage.

An experimental investigation on ultra-thin oxides under combined substrate hot-electron injection (SHEI) and tunnelling electrical stress (CVS) is reported. We study the electrical properties of 2.5–1.5 nm-thick SiO2 oxides in N-channel metal–oxide–semiconductor (NMOS) field effect transistors. CVS stress at VG = +3.5 V does not affect the transistor operating parameters but does increase, up to a factor of 10, the gate current. We have verified that the critical parameter of CVS stress is the gate voltage bias, consequently we suggest a model based on energetic electrons creating damage, which, correctly describes the reliability of ultra-thin SiO2 at CVS condition. In comparison SHEI is observed to be not only dependent on gate bias but also on the electric field in the oxide. A comparison of each parameter either injected charge or current, gate and substrate voltage or oxide field is experimentally done. Based on these and previous results, the defect creation probability for CVS and SHEI stress is fitted over gate voltage to resolve two defect generation mechanisms.

International audience; The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunneling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by VG and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunneling.

International audience; We have studied the possibility to use hot carrier stresses to reveal the latent damage due to Wafer Charging during plasma process steps in 0.18 μm and 0.6 μm CMOS technologies. We have investigated various hot carrier conditions in N- and PMOSFETs and compared the results to classical parametric studies and short electron injections under high electric field in Fowler–Nordheim regime, using a sensitivity factor defined as the relative shift towards a reference protected device. The most accurate monitor remains the threshold voltage and the most sensitive configuration is found to be short hot electron injections in PMOSFET’s. The ability of very short hot electron injections to reveal charging damage is even more evidenced in thinner oxides and the better sensitivity of PMOSFET is explained in terms of conditions encountered by the device during the charging process step.

International audience; This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

As the operating temperature increases, the tradeoff between performance and reliability becomes tricky as the classical hot-carrier (HC) picture has to be modified into the energy-driven formalism, taking into account the scattering mechanisms and thermal effects in ultrashort channel, which lead to current-driven damage in nanometer-scaled MOSFETs. This chapter focuses on the new requirements for advanced modeling of HC phenomena as a function of the scaled digital CMOS nodes. In the first part we recall the classical HC behavior in both N- and P-channel MOSFETs described by the lucky electron model (LEM) in thick (T ox ≥ 7 nm) to medium-range gate-oxide thickness T ox (3.2 nm ≤ T ox ≤ 5 nm), where charge detrapping is involved. Then we present the specificity of decananometer MOSFETs (T ox < 3.2 nm) using a unified energy-driven formalism between high carrier energy to high carrier density, as now cold-carrier (CC) damage results in a multiple-particle (MP) degradation process thermally activated under multivibration excitation of the passivated dangling bonds at the interface. Next, we finally develop a complete modeling for NMOS and PMOS devices that is transferred from DC accelerating damage to AC aging involved in logic cells using an Age(t s) function, for any pulse configurations, which are readily checked between experiments on digital cells at high temperature and the modeling. HC issues and temperature intricacy with bias temperature instability (BTI) are presented through some examples. Finally, we improve the CC modeling by defining a mixed-mode (MM) damage mechanism that lies between single-particle (SP) with high carrier energy processes and MP processes dominated by carrier density, including the progressive change from electron–electron scattering (EES) to multiple-interaction scheme until MP damage. This offers a complete comparison between 28-nm low-power (SiON) silicon bulk CMOS nodes and high-K metal gate (HfSiON) submitted to MP degradation process, with the interplay of thermal effects. It opens new perspectives for an accurate HC to CC reliability determination in actual and future nanoscale CMOS nodes.

A comprehensive study of HC reliability and process change variation for submicron fully depleted Silicon On Insulator (FDSOI) MOSFET's is presented. The different process variation within the FDSOI technology and their impact on HC degradation are examined (i.e. channel length L, Source/Drain resistance RSD, oxide thickness T ox , lightly-doped drain LDD). In order to prove its consistence, our energy driven model recently presented will be applied to the different process changes.

Based on experimental measurements at bitcell level combined with SPICE and Monte-Carlo simulations, an analytical method is presented to accurately predict fresh/aged Vmin distributions. The impact of BTI variability modeling and real workloads considerations is also deeply analyzed in this paper.

With technology scaling, highly integrated devices have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injections (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper an experimental analysis of HCI degradation for fully depleted Silicon On Insulator (FDSOI) MOSFETs. The carrier energy and bulk bias dependencies are modeled according to our recent findings through a simple HC model based on physical theories applied to the specificity of FDSOI technology with body bias operation.

With device scaling, electric fields across the gate oxide have increased and supply voltages have been reduced not as much as the gate-oxide thickness, intensifying the probability of dielectric breakdown events for transistors. In this context, the more the oxide thickness is reduced, the more the oxide breakdown degradation is progressive. However, the first breakdown event does not always cause a functional failure in digital circuits. As a consequence, relaxation of the predicted lifetime could be accounted at circuit level with respect to the area scaling. First, this paper deals with characterization of soft breakdown events at device level. Post-breakdown degraded parameters and their dispersion are identified and quantified. Then a transistor-level model of breakdown is presented; it handles distributions of Time to Breakdown, breakdown spots localization and parameters degradation (ΔV t , evolution of I d /I s , ΔI g , ΔI dlin ...). This model is implemented in API, it takes into account both BTI and oxide breakdown degradation contributions and is calibrated for a range of breakdown severity used at circuit level. A custom digital circuit has been implemented to measure the impact of multiple oxide breakdowns on static current and oscillation frequency. The theoretical models of multiple oxide breakdown events reproduce properly the experimental behavior. Finally the case of hard breakdown events in a data path is investigated and the impact on percentage errors is discussed.

International audience; The hot-carrier degradation induced by first- and second-impact ionization events is compared in advanced N-MOSFETs used for digital applications with a 3.2-nm gate-oxide thickness. Results show that the substrate enhanced electron injection (SEEI) mechanism is still increased in 0.15-mm channel length devices with p-pockets and shallow drain junctions with a measured much higher injection efficiency than that in older technologies. The enhancement of the gate current originates from tunneling contributions and from the secondary–primary-hot electron currents at low energy. The induced damage is explained solely by the interface trap generation and mobility reduction in 3.2-nm thick gate-oxide devices. The difference between first and second hot-carrier damage is related to the extension of the degraded region toward the source. This is in contrasts with thicker gate-oxide N-devices where the SEEI effect is weak and where the electron trapping extends from the gate-drain overlap region toward the source in addition to the generated interface traps.

International audience; The effects of the substrate voltage are studied in advanced N-MOSFETs with a 3.2m gate-oxide thickness used for logic applications. Results show that the electronic gate current originates at low voltage from tunneling contributions and from the first-induced second impact ionization mechanisms. The injection efficiency is found to be channel-length dependent through a large increase in the gate-current with the increase in the lateral field (vertical field) and the electron-electron scattering for low-energy hot-carriers. Lifetime prediction techniques are compared showing a strong device lifetime reduction with the back bias at VSB = VDD independently of the extrapolating model which can be modeled by the measurement of the gate-current and the emission probability.

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level is also evaluated.