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Designing in reliability in advanced CMOS technologies

Authors :
David Roy
Vincent Huard
F. Perrier
Emmanuel Vincent
C. Guerin
M. Denais
Chittoor Parthasarathy
G. Ribes
Alain Bravaix
STMicroelectronics [Crolles] (ST-CROLLES)
Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP)
Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)
Yncréa Méditerrané
Source :
Microelectronics Reliability, Microelectronics Reliability, 2006, Microelectronics Reliability, 46 (9-11), pp.1464-1471. ⟨10.1016/j.microrel.2006.07.012⟩
Publication Year :
2006
Publisher :
Elsevier BV, 2006.

Abstract

International audience; Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.

Details

ISSN :
00262714
Volume :
46
Database :
OpenAIRE
Journal :
Microelectronics Reliability
Accession number :
edsair.doi.dedup.....0a377abf4179d0114a51162555186bae