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In last 10 years, application of metallization in semiconductor has been expanded greatly. In this article, metallization technology and schemes in memory devices was reviewed in terms of its needs and requirements. Also new processes and concepts were proposed

The feasibility of the charge-transfer based polymer resistive memory as a future data storage device was tested using a thermally robust polyimide and PCBM composite film, available by low-cost solution processing. The proto-type device with a simple 4F2 cross-point cell structure demonstrated basic non-volatile memory functions (> 1000 write/erase cycles and 1-week data retention in an ambient without encapsulation). Not only bi-polar but also uni-polar operation scheme with multi-level programming worked for the device. The cells on both the top and the bottom layers of a stacked device with additional heat budget of > 300 °C for 1 hour exhibited no degradation on the performance.

Feasibility of high density probe-based memory with polycrystalline ferroelectric media has been demonstrated for next memory applications beyond sub-10 nm generation. Noble chemical-mechanical-polishing (CMP) method was employed to fabricate a very even surface on polycrystalline MOCVD Pb(Zr, Ti)O3 (PZT) media. On the CMP processed PZT media, domain dot array was able to be written and read even at grain boundary region by PFM technique. Moreover, 15 nm-sized domain dot was successfully demonstrated on 50 nm-thick PZT media. Also for the first time, we successfully demonstrated that the polycrystalline ultra thin 7 nm-thick PZT media has good ferroelectric properties.

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced x-ray emission spectrometry (LEXES) and other conventional techniques such as Four Point Probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and out-diffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well.

The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation of peripheral NMOS properties, which is the first approach to DRAM. The PMOS performance enhancement was found to be more than 40%. The authors suggest the SiGe SD structure as the key solution for the improvement of peripheral PMOS transistor properties in sub-50nm DRAM technology

We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation.

We demonstrate a highly manufacturable substrate-induced strained Si device, which is compatible with the conventional Si bulk process. It utilizes ultra-thick-strained Si (UTSS) layer thicker than 3000 /spl Aring/ and relaxed SiGe layer with low Ge content less than 10%. The UTSS n-MOSFET gives 6 /spl sim/ 12% increase in I/sub on/ according to the gate length without the cost of increase in I/sub off/. In addition, more than 5% increase in I/sub on/ for p-MOSFET can be obtained by hybrid stress of UTSS and SiGe source/drain process. We also emphasize the importance of the ratio of channel resistance (R/sub CH/) to source-drain resistance (R/sub SD/) for performance enhancement.

We reduced the gate tunneling current by seven times and suppressed NBTI using plasma nitridation-induced re-oxidation (PIROX). In plasma nitrided gate oxynitride, the nitrogen concentration at the MOS interface is determined after plasma nitridation process, which affects the electrical and physical properties of gate oxynitride. To facilitate the control of nitrogen concentration at the MOS interface, an additional re-oxidation process is needed, but decreasing the nitrogen concentration. In this paper, the plasma nitridation process is proposed that realizes simultaneously the nitridation and re-oxidation without an additional process and the decrease of nitrogen concentration. The control of nitrogen concentration and the amount of re-oxidation under high pressure process improves the gate tunneling current, mobility, and NBTI.

CVD-TaN thin films derived from a new noble precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4 K via chains. The via resistances were measured as a function of TaN thickness (10/spl sim/45 /spl Aring/), compared to PVD TaN. Diffusion barrier properties (bias temperature stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar and H/sub 2/ post-plasma after CVD-TaN was introduced to improve the properties of the barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma.

For the first time, we successfully developed highly reliable 50nm-thick polycrystalline PZT capacitor using noble Ir/SrRuO/sub 3/ top electrode and MOCVD PZT technology. In the 50nm-thick PZT capacitor, 33/spl mu/C/cm/sup 2/ of remanent polarization and 0.7V of saturation voltage have been demonstrated. Moreover, after 100hrs of bake-time at 150/spl deg/C, opposite-state polarization margin was over 23/spl mu/C/cm/sup 2/, which is world-wide best result so far achieved. Using this capacitor technology, highly reliable low voltage operating embedded FRAM device was successfully developed.

We describe a novel technique of fabricating WN nanocrystal memory device. Pulsed nucleation layer (PNL) method is firstly introduced for the formation of uniformly distributed high density (/spl sim/ 1.6 /spl times/ 1012 /cm/sup 2/) nanocrystals with the size of 3 /spl sim/ 5 nm. The WN nanocrystal memory exhibits very large threshold voltage shifts over 3.5 V and good retention and endurance characteristics. Further improvement of memory performances using stacked tunnel barrier and double layer storage node structures was also presented.

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

In this work, HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM with recess channel arrary transistor (RCAT) and W/poly-Si gate for the development of sub-60nm DRAM technology. No degradation of cell transistor characteristics was observed with HfSiON gate dielectric. In peripheral transistors, excellent sub-threshold swings and driving current of 515 /spl mu/A//spl mu/m and 216 /spl mu/A//spl mu/m for nMOS and pMOS, respectively, at V/sub dd/=1.8V and I/sub off/=20/spl mu/A//spl mu/m were obtained. Compared to surface channel pMOSFET, lower V/sub th/ was achieved in buried channel pMOSFET due to fermi-level pinning. Negligible increase of gate leakage current during post annealing up to 950/spl deg/C for 30min is shown the excellent thermal stability of HfSiON dielectric.

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 /spl mu/m/sup 2/, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

We have examined STTM as the alternative to DRAM in terms of scalability, operation power, and sensing signal. The characteristics of STTM are shown to strongly depend on those of vertical transistor. To obtain maximum performance, fully depleted vertical transistor is essential. Moreover, it is shown that scaling below 50 nm could exhibit long enough retention time for nonvolatile random access memory application.

The simple stacking structure such as [Sub/Zr/AlO/sub x//NiFe (or CoFeB)/capping layer] was prepared to investigate the changes of magnetic properties of free layer with annealing temperature. Ta, Ru, or Zr was used as the capping layer. Samples were annealed in a vacuum (below 1/spl times/10/sup -6/ Torr) for 1 hour under a magnetic field of 10 KOe. The magnetic properties were measured using vibrating sample magnetometer in sample with 1/spl times/1 cm/sup 2/ area. The changes of the coupling field between the pinned layers through Ru as a function of annealing temperature for various pinned layer materials were also studied.

We analyzed dopant concentration and profiles in source drain extension (SDE) by using in‐line low energy electron induced x‐ray emission spectrometry (LEXES), four point probe (FPP), and secondary ion mass spectroscopy (SIMS). By monitoring the dopant dose with LEXES, dopant loss in implantation and annealing process was successfully quantified. To measure the actual SDE sheet resistance in CMOS device structure without probe penetration in FPP, we fabricated a simple SDE sheet‐resistance test structure (SSTS) by modifying a conventional CMOS process. It was found that the sheet resistances determined with SSTS are larger than those measured with FPP. There are three mechanisms of dopants loss in CMOS process: 1) wet‐etching removal during photo resist cleaning, 2) out‐diffusion, and 3) deactivation by post‐thermal process. We quantified the loss of the dopant in SDE during the CMOS process, and found that the wet‐etching removal and out‐diffusion are the most significant causes for dopant loss in n‐SDE ...

Due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVD Al. For the process, CVD Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVD TiN and PVD TiN as a wetting layer, which was followed by PVD Al and reflow, then the Al surface was polished with colloidal silica based slurry.In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.

Plasma doping and laser annealing are successfully integrated into the conventional p-metal–oxide–silicon field effect transistor (PMOSFET) process to form ultra shallow junction (USJ). Comparing with the conventional combination of ion implantations and rapid thermal annealing (RTA), junction depth (XJ) and sheet resistance (RS) are reduced. Also, significant improvement of the short channel effects without the degradation of on-current is observed.

International audience; A new manganese (II) phosphite with the formula Mn(HPO3) has been synthesised under mild hydrothermal conditions and autogenous pressure. Large pink coloured single crystals were obtained, allowing the resolution of the structure by x-ray diffraction. Mn(HPO3) crystallises in the P21/c monoclinic space group with a=8.036(3) Å, b=8.240(3) Å, c=10.410(3) Å, β=124.73(3)° and Z=8. The structure consists of a three-dimensional, compact framework of edge sharing MnO6 octahedra linked to phosphite groups via oxygens. The presence of the phosphite anion has been confirmed by IR spectroscopy. Mn(HPO3) presents a high thermal stability limit of 580 °C, before rapid transformation to Mn2P2O7 occurs. Photoluminescence and diffuse reflectance spectroscopy studies show the presence of high spin Mn(II) in significantly distorted octahedral coordination with Dq and Racah parameters of Dq=820, B=910 and C=3135 cm−1. The ESR spectra, performed at different temperatures, are isotropic with a g-value of 2.00(1). Magnetic measurements indicate global antiferromagnetic interactions with a ferromagnetic transition at 15 K, attributed to a canting of the antiferromagneticaly aligned spins.

We applied non-melt laser anneal to the CMOS as an alternative method to activate the source/drain junction dopant. By simple changing of the spike anneal to the laser anneal, it was found that the short channel effect (SCE) is suppressed remarkably. The drive current of the device with the laser anneal is improved for the long channel transistor but degraded for the short channel transistor, compared to the spike anneal. We showed that the drive current is directly related to the overlap capacitance at short channel. And using a forward bias method, we found out that the current degradation is caused by the contact resistance.

The plasma nitrided gate oxide process has been developed and applied for mobile DRAM with low operating voltage. As a result, we confirm that plasma nitrided gate oxide can block the boron penetration in DRAM, which has a higher thermal budget than other devices. The nitrogen bonding status and profile are investigated to check the change in transistor and gate oxide characteristics.

PAALD (plasma assisted atomic layer deposition)-TaN thin films derived from a precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were developed and compared to the thermal ALD-TaN. The deposition rate of the PAALD-TaN process was around /spl sim/0.9 /spl Aring//cycle at 250 /spl deg/C. The resistivity of TaN film by the PAALD was /spl sim/ 366 /spl mu/ohm-cm, while the resistivity by the thermal ALD was not measurable. The PAALD-TaN and thermal ALD-TaN film appeared to have cubic and amorphous phase, respectively. In Cu metallization, as TaN thickness increased, via resistance with thermal ALD-TaN increased dramatically, but via resistance with PAALD-TaN was almost constant and much lower than that with thermal ALD-TaN. Using PAALD-TaN, the diffusion barrier characteristics was also improved in comparison to thermal ALD-TaN.

We suggested a new qualification method for DRAM retention property by evaluation of a cell transistor leakage current using the subthreshold characteristic parameters, V/sub th//S and dV/sub th//dV/sub BS/. Correlation between the Leakage current Evaluation Parameter (LEP) which is obtained from the method and the retention time of the DRAM products was carried out. The result shows that the measurement limitation imposed by the extremely small cell transistor leakage current can be overcome by the new method, and provides quick feedbacks on the retention characteristics at the early stage of process integration and qualification cycles. During the correlation procedure, we also investigated on the statistical distribution of the retention time of the DRAM cells.

A new test structure for a stacked capacitor DRAM cell transistors with a diagonal active-area was developed to analyze the leakage current characteristics of the cell transistors. The leakage current components of the low power DRAMs with different retention fail distributions was investigated in detail using the test structure, and the important aspect of the sub-threshold leakage component was discussed for below 0.11 /spl mu/m DRAM cell transistors.

The in-line plasma process monitoring was successfully performed with non-contact direct measurement (NCDM) tool and its results were well matched with those from devices. Using this monitoring method, we developed a plasma nitrided gate oxide process for mobile DRAMs with low operating voltage. We confirm that plasma nitrided gate oxide can block the boron penetration in DRAMs, which has higher thermal budget than other devices, and that the NCDM tool can be used for checking the degree of plasma nitridation. We assure that the NCDM tool is a time-effective tool for plasma nitridation process development.

New technologies for sub 0.1 /spl mu/m DRAM devices are reviewed and discussed in views of shallow trench isolation and capacitor process. In order to enhance the gap filling and reduce the accumulated mechanical stress in STI, Polysilazane-SOG pillar is introduced at the trench bottom. Additionally, poly-Si filling process is also developed to minimize channel edge effect. HfO/sub 2/ deposited by atomic layer deposition is employed to lower the Toxeq. down to about 25/spl Aring/. Toxeq. can be reduced further by introduction of TiN metal electrode. TiN electrode capacitor of Toxeq. 15/spl Aring/ shows the stable leakage current. Ru electrode help Toxeq. scale down to 10/spl Aring/. It is concluded that sub 0.1 /spl mu/m devices can be manufacturable through the introduction of new technologies and materials.

The nanocrystal floating gate flash memory has a potential advantage in high-density floating gate memory for its superior scalability over its conventional structure. However, the retention and small sensing window have remained as the main issues for practical applications. In this work, we propose a nitride/oxide/nitride (NON) tunnel barrier, which is more sensitive to the gate bias than the uniform oxide barrier, and present real nonvolatile memory with a 1 V window after 10 years at 85/spl deg/C with programming at 8 V, 10 /spl mu/s and erasing at -8 V, loops.

A novel CVD-cobalt process which enables a uniform salicidation even in novel MOS device structures with complex shape is developed for the first time. With CVD-cobalt salicidation, identical values of low sheet resistance can be realized on actives and gates regardless of the surrounding geometry, due to its excellent conformality. In addition, a low contact resistance can be obtained in small metal/active contacts even with high post thermal budget when CVD-Co is applied as an ohmic layer due to its conformality and inertness with the dopants. CVD-cobalt is a needed and suitable solution for the salicidation and silicidation of not only the continuously scaling conventional CMOS, but also the emerging next generation of devices with complex shapes and structures such as vertical and 3D FET.

For the first time, a nitride/oxide/nitride stacked tunnel structure is adopted as highly field-sensitive tunnel barrier to improve both program/erase speed and data retention of nanocrystal memory. Product-adaptive nonvolatility (>10 years at 85/spl deg/C) and cycling endurance (>10/sup 6/) were obtained with the program time of 10 /spl mu/s at V/sub G/=8 V and the erase time of 100 /spl mu/s at V/sub G/=-8 V with 0.84 V threshold window. The program speed was 100 times faster and the voltage was about 10 V smaller than those of a conventional NAND type flash memory cell. These results strongly suggest that nanocrystal floating gate memory becomes a promising solution to overcome the scaling limitation of the conventional floating gate memory cell.

We have successfully developed a MIM capacitor process technology with a HfO/sub 2/ single layer deposited by ALD (atomic layer deposition), where a Hf(NEtMe)4 and CVD-TiN cylinder-type storage-node were used as a Hf liquid source and bottom electrode for 90 nm-scale DRAMs. Our experimental results indicated that NH/sub 3/-plasma treatment on HfO/sub 2/ film promoted crystallization below 400/spl deg/C as well as the formation of a HfO/sub x/N/sub y/ layer on the surface of the HfO/sub 2/ film. With this treatment, it was possible to solve the degradation problem of the leakage current depending on deposition method of the top electrode, and a stable leakage current without degradation was obtained up to 550/spl deg/C. As a result, a TiN/HfO/sub 2//TiN (TIT) capacitor with 1.4 /spl mu/m-height storage node was successfully demonstrated with stable leakage current of 1fA/cell at +1.2 V and high cell capacitance of 40 fF after metal-2 integration.

For the first time, a highly manufacturable fin-channel array transistor (FCAT) on a bulk Si substrate has been successfully integrated in a 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL (/spl sim/13mV/V), and a high cell transistor drive current with remarkably low subthreshold leakage current (/spl sim/0.2fA/cell).

We have developed a novel cell structure of PRAM with metal interlayer. This novel structure has been proposed to solve the over-programming fail. We have examined the cause of over-programming by simulation of the phase transition of chalcogenide and successfully demonstrated reliable cell operation of this novel structure in writing current level, crystallization speed, and endurance. It can be explained by a model in which the metal interlayer is a local heat sink and the top GST layer is a thermal insulator.

For the first time, we integrated a HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric with a CVD-TaN metal gate deposited by TAIMATA (tertiaryamylimidotris dimethylamidotantalum) in n/pMOSFETs. It was found that TaN films with low impurity contents were required for optimized capacitance. Together with a slight improvement of the transconductance and a substantial gain in inversion EOT with HfAlO/TaN, improved current drivability was observed in comparison to nitrided-SiO/sub 2//poly-Si and HfAlON/poly-Si with similar EOTs. In addition, CVD-TaN resulted in improved J/sub g/ characteristics, showing F-N tunneling behavior with an effective barrier height of 1.1 eV in nMOS in the inversion region. These results suggest that a CVD-TaN metal gate is necessary for the implementation and scaling of high-k gate dielectrics.

The new barrier metal structure using selective wetting layer was proposed. This process using physical vapor deposition (PVD) Ti as the controlling layer for conformal chemical vapor deposition (CVD) Al layer shows an excellent filling capability for deep small contact and good electrical properties as well as the remarkable surface morphology, which can be applied for the new metallization process such as metal contacts and via holes filling.

The key factors to improve the switching characteristics are systematically analyzed to develop high density MRAM with a reliable operating margin. We demonstrated that roughness control of MTJ films, choice of free layer materials with small Ms, and optimized cell shape can effectively suppress the switching distribution. As a novel free layer scheme, a lamellar structure is proposed and found to improve the switching characteristics by suppressing the grain growth in the ferromagnetic layer.

In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

We have developed a cylindrical TiN/HfO/sub 2//TiN (TIT) capacitor for 70 nm DRAMs application. TIT capacitors with HfO/sub 2/ films deposited by ALD(Atomic Layer Deposition) using Hf(NEtMe)/sub 4/ precursor and O/sub 2/ plasma as a reactant is shown to be applicable to DRAM device below 70 nm design rule for the first time. It shows the thermal budget endurance against back-end process of DRAM device as well as the very low enough Toxeq of about 13 /spl Aring/ to provide the sufficient cell capacitance.