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The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search; moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool.

This paper presents a methodology for verifying non-linear arithmetic circuits by applying diffident concepts. In our proposed methodology, a combination of gate-level netlist, Functionally Reduced And-inverter Graph (FRAIG) and Taylor Expansion Diagram (TED) is used to verify that the implementation satisfies the specification. Backward algebraic rewriting technique is used for function extraction of the word-level abstraction. Gate-level netlist is adopted to form FRAIG graph which is verified via TED representation. This is intended to handle the complex verification process of multiplier and alternatives of the traditional AIG for arithmetic circuits. Experiments are conducted on both post and pre synthesized non-linear arithmetic circuit of various multipliers such as Booth and CSA. The results win by several order of magnitude in area consumption, were the used area is almost 50% less than other compared approaches with a slight increase in CPU run time.

The paper proposes a tool for the numerical simulation of the behavior of coupled oscillators based on Kuramoto model. The approach is based on constructing electrical circuit model for which Kirchhoff equations coincide with Kuramoto equations of the oscillator ensemble. A procedure to generate Spice netlist for the circuit has been developed. The procedure is based on the initial description of the Kuramoto model in the form of Matlab data structures.

The digital verification with Universal Verification Methodology (UVM) provides vast opportunities for automation. The momentous themes in the context of digital verification are constraint random stimulus generation, functional coverage, and self-checking test benches that make digital verification very robust. However, analog verification is still a manual process. Therefore, the demand is to transform analog verification techniques into an automated process in the context of digital-centric Mixed-Signal verification for more coverage. A new verification approach that simulates Mixed-Signal Design Under Test (DUT), which contains Register Transfer Logic (RTL), SPICE netlist, and Verilog-AMS models or Real Number Model (RNM) blocks has been demonstrated in the paper that describes the Mixed-Signal simulation environment and simulation techniques to achieve more simplistic yet very powerful strategies to address Mixed-Signal verification challenges.

This paper presents a dual output resistance tunable current controlled current conveyor (DO-RTCCCII). In the existing current conveyor the change in bias current is required to alter the design parameter Rx which is the intrinsic resistance of input X terminal. This variation changes the internal dc bias conditions such as saturation margins as well as total power consumption of the block. A resistance trimming block is added at X terminal which is controlled by some programmable bits. The usage of programmable bits helps to achieve the desired response without changing bias current, dc operating point and total power consumption. The port relationships of the DO-RTCCCII block are checked and the circuit and design parameters of current follower, voltage follower are analyzed. The operation of filter circuit is also included to illustrate usefulness of the proposal. The circuit has been designed and simulated using 28 nm CMOS bulk technology model parameters on Cadence Virtuoso/AMS environment (eldo simulator) using 0.75 V supply voltage and results have been verified with post layout netlist.

This paper aims at integrating three powerful techniques namely Deep Learning, Approximate Computing, and Low Power Design into a strategy to optimize logic at the synthesis level. We utilize advances in deep learning to guide an approximate logic synthesis engine to minimize the dynamic power consumption of a given digital CMOS circuit, subject to a predetermined error rate at the primary outputs. Our framework, Deep-PowerX, focuses on replacing or removing gates on a technology-mapped network and uses a Deep Neural Network (DNN) to predict error rates at primary outputs of the circuit when a specific part of the netlist is approximated. The primary goal of Deep-PowerX is to reduce the dynamic power whereas area reduction serves as a secondary objective. Using the said DNN, Deep-PowerX is able to reduce the exponential time complexity of standard approximate logic synthesis to linear time. Experiments are done on numerous open source benchmark circuits. Results show significant reduction in power and area by up to 1.47 times and 1.43 times compared to exact solutions and by up to 22% and 27% compared to state-of-the-art approximate logic synthesis tools while having orders of magnitudes lower run-time.

Computing power brings new technologies into human life. NVIDIA devoted to accelerating parallel computing through CPU-GPU cooperating architecture since we invented CUDA in 2007. In the last decade, one of the most important technologies, deep learning, became feasible and realistic because GPU accelerates the optimizing process of neural network over 60x, which means that the model training time shortens from weeks to hours. DL not only performed superior to human in some computer vision tasks like ImageNet but also made significant progress of many fields like medical, autonomous, manufacturing, finance, electronic design automation (EDA) etc.In this paper, we introduced two deep learning innovations in EDA field including (1) Graph Convolutional Network in Testability Analysis and (2) DREAMPlace. In (1), graph convolutional network can predict observation point candidates in a netlist more efficiently compared to commercial tools. In (2), DREAMPlace significantly accelerates the VLSI placement process by using deep learning framework of GPU for optimizing process.

A methodology for On-Die Power Supply Induced Jitter (PSIJ) for High Speed IO is put forth. The approach accurately estimates the jitter induced due to currents of various blocks through the power distribution network (PDN). The analysis relies on simulations of Detailed Standard Parasitic Format (DSPF) netlist of circuit blocks along with post layout PDN network. A model order reduced distributed RC network of PDN is computed to reduce the simulation times due to huge PDN network with millions of nodes. This allows designers to perform accurate PSIJ estimation along with identifying the buffers causing higher jitter due to ripple seen on their PG pins, thus optimizing circuit blocks. The analysis can drive decisions regarding die capacitance partitioning and requirements for regulation on various circuit blocks.

To protect the SoC supply chain from such vulnerabilities, academic and industry researchers have proposed many design for security and hardware Trojan detection techniques. However, these techniques either rely on RTL verification methods which may not be applicable to netlist/layout level designs or leverage testing/measurement results to indirectly identify possible hardware vulnerabilities. There lacks a CAD tool based deterministic process which can convert layouts/netlists into RTL code for design verifications. In this talk, I will introduce our recent effort in building such a CAD toolchain through which a layout in GDS-II format can be de-syntheiszed and converted to the high level description, e.g., RTL code, for security analysis. The CAD toolchain includes a series of circuit reverse engineering tools which can also be applied individually for specific tasks such as design deobfuscation, hardware Trojan detection, etc. This toolchain fits in an even larger concept of CAD for Security, a recent trend for SoC/IC protection and trust verification.

The involvement of external vendors during the different phases of the integrated circuits (IC) allows the adversaries to insert the hardware Trojan (HT). Existing HT detection techniques fail to detect Trojans accurately, time-consuming, does not handle class imbalance problem efficiently, use tree-based feature importance, and possess large false positive and negative rates. Therefore, to overcome these problems, this paper proposes a new class weighted Extreme Gradient Boosting (CW-XGB) based HT detection technique, which detects Trojans from gate-level netlist using the best set of SCOAP feature values. A weighting scheme is proposed in the CW-XGB model to tackle class imbalance problem by assigning higher weights to minority Trojan-inserted class, thus removing the need to apply the oversampling/synthetic data algorithm. Moreover, the proposed model automatically addresses the overfitting issue by incorporating the regularization in the loss function. Besides, we also employ early stopping to avoid the over-training of the proposed model. Further, a new feature selection method is proposed, which selects the best set of SCOAP features based on permutation feature importance values, and it also avoids the continuous retraining of the model. Finally, a new HT detection algorithm is proposed that accurately detects HT from gate-level netlist using the best set of features and proposed CW-XGB model. Experimental results on Trust-Hub benchmarks shows that the proposed HT detection technique provides on an average 99%, 98.86%, and 99% accuracy, precision, and recall, respectively. Further, it provides on an average 98.76% and 98.73% F-measure and ROC-AUC score, respectively.

Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert hardware Trojans into their products, developing an effective hardware Trojan detection method is strongly required. In this paper, we evaluate hardware Trojan detection methods using neural networks and random forests at gate-level intellectual property (IP) cores that contain more than 10,000 nets. First, we extract 11 features for each net in a given netlist, and learn them with neural networks and random forests. Then, we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on the learned classifiers. The experimental results demonstrate that the average true positive rate becomes 84.6% and the average true negative rate becomes 95.1%, which is sufficiently high accuracy compared to existing evaluations.

In this paper, we propose a new methodology for equivalence checking in the AMS domain. On top of comparing two existing approaches, we define a new methodology using continuous reachable sets. The approaches are illustrated upon two existing abstract modeling techniques. Moreover, the generated models are compared against a conformant model that captures the measured system behavior from the real circuit. These modeling methodologies yield hybrid automatons (HAs), which along with the netlist, are compared using different equivalence checking methods demonstrating verification techniques on different abstraction levels. Finally, we discuss the methodologies with respect to an efficient and safe circuit design.

The contemporary IC supply chain depends heavily on third-party intellectual property (3PIP) that is integrated to in-house designs. As the correctness of such 3PIPs should be verified before integration, one important challenge for 3PIP vendors is proving the functionality of their designs while protecting the privacy of circuit implementations. In this work, we present Pythia that employs zero-knowledge proofs to enable vendors convince integrators about the functionality of a circuit without disclosing its netlist. Pythia automatically encodes netlists into zero knowledge-friendly format, evaluates them on different inputs, and proves correctness of outputs. We evaluate Pythia using the ISCAS’85 benchmark suite.

This paper introduces GRANNITE, a GPU-accelerated novel graph neural network (GNN) model for fast, accurate, and transferable vector-based average power estimation. During training, GRANNITE learns how to propagate average toggle rates through combinational logic: a netlist is represented as a graph, register states and unit inputs from RTL simulation are used as features, and combinational gate toggle rates are used as labels. A trained GNN model can then infer average toggle rates on a new workload of interest or new netlists from RTL simulation results in a few seconds. Compared to traditional power analysis using gate-level simulations, GRANNITE achieves >18.7X speedup with an error of only

The ability to reverse engineer a hardware netlist in order to detect malicious logic has become an important problem in recent years. Much work has been done on algorithmically identifying structure and state in circuits; the first step of which is to separate control signals from data signals. The most current tools rely on topological comparisons of logic in order to identify signals which are uniquely structured in the netlist, as these signals are likely control signals. However, topological comparisons become less effective when a netlist has been resynthesized and optimized. We present a new tool, RELIC-FUN, based on netlist slicing and functional comparison of logic. Experimental results show that depending on netlist size, optimization, and control logic density, the proposed algorithm can be more accurate, and faster, than existing topological algorithms in many cases.

In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology uses Graph-based Analysis (GBA) STA principles, is fast, is able to compute setup or hold slacks on sequential elements, and operates without cycle cutting. Industrial Timing Libraries, Verilog input and multiple PVT corners are supported. To perform STA on the cyclic circuit portion, a Graph-based Event Model, a live and 1-bounded Signal Transition Graph (STG), i.e. a simplified PeTri-Net (PTnet), the Event Timing Graph (ETG), is automatically generated from the netlist and the associated timing arcs. The ETG is a cyclic, timing arcs graph, the period analysis of which can identify the cyclic portion's period and Critical Cycle(s). The acyclic portion's STA may be subsequently performed, based on the cyclic portion's Arrival Times (AT). We illustrate an algorithm for automated ETG construction, based solely on circuit components, and their technology library (.lib) timing arcs unateness. We prove that the generated ETG will be live and 1-bounded. Our STA approach is demonstrated on three practical, mixed cyclic, acyclic circuits, a ring-oscillator, a Vernier delay line, and a GALS controller.

Reverse engineering has been increasingly used by malicious actors to steal valuable Intellectual Property, leading to a loss of revenue and potential compromise of security from pollution of the supply chain with counterfeits. IC camouflaging is a promising approach to counter reverse engineering attacks. In this work, we leverage the availability of multi-threshold FinFET transistors to facilitate camouflaging of logic cells. We propose cell designs, for 2-, 3- and 4-input gates, which realize various logic functions by utilizing different combinations of transistors with different threshold voltages. The structurally identical cells increase the effort needed by an attacker to reverse engineer the logic as the cell's functionality is not apparent from its layout. We explore de-obfuscation of a camouflaged netlist using SAT solver based approach and show that our designs can increase the deobfuscation effort by over 10x compared to limited camouflaging.

The throughput and the latency for practically larger capacitive loads are the two key factors that needs to be considered in the HPC (High Performance Computing), AI (Artificial Intelligence), high frequency trading applications. In this paper we are addressing the latency which needs to be low for any such applications. For this implementation we have re-looked into the functionality of each constituents of the transceiver and implemented the circuits to reduce the overall latency of the system without affecting the Serializer/Deserializer (SerDes) throughput. The proposed architecture replaces some of the conventional blocks of transceivers to reduce the latency. In this paper we describe the implementation in detail with circuit simulated upto extracted netlist level. This design of a transceiver with 20gb/s is sent for fabrication in TSMC 28nm HPC + technology node. This paper is limited to transmitter portion of the work, where we see a major reduction in the associated latency compared to conventional transmitters.

A gigantic amount of test pattern covering all faults is required to attain a high test quality in modern VLSI testing. With this, the Test Data Volume (TDV) rises, which leads to an increase in Test Application Time (TAT) as well as the power requirement. This paper proposes a Fault-based Approximate Testing (FAT) technique that generates test patterns only for distinguished faults. The basic idea is identifying a set of faults (tolerable faults) that can be ignored and left untested. The remaining faults (intolerable faults) are tested by generating test patterns for those faults. We examine the impact of overlooking some of the faults by injecting stuck-at faults in the appropriate place of the netlist. Deviation in the output is analyzed in respect of an application-specific error threshold. The experimental result shows that irrespective of the erroneous result produced, these circuits can be used in all kinds of error-tolerant applications like image/video processing, speech processing, and digital communications. Along with the above benefit number of fault-sites is reduces by 40–50%, which leads to a reduction in the number of test patterns.

We propose FlowTrojan, the first systematic framework for insertion and detection of Hardware Trojans (HTs) on Flow-based Microfluidic Biochips (FMFBs). The FMFB is an emerging platform with critical usages in the medical field due to the handling of sensitive information. We discuss the attack model where the malicious foundry aims to compromise the on-chip control circuitry. FlowTrojan is designed to automatically extract the netlist for the control circuitry from the layout and explore the internal independence between regions on FMFBs for partitioning. We demonstrate that HT triggers can feature a low activation probability while placed on the non-critical timing path to stay clandestine during functional and parametric testing. To avoid such attacks, FlowTrojan provides a parallel regime of control-value (CV) based HT detection as the countermeasure. Experimental results corroborate the effectiveness and scalability of the proposed attack and detection schemes.

In this paper, it is shown how partitioning, placement, and routing of an 8-bit shift register circuit using cadence tools done. The functionality of the shift register circuit is verified by writing a Verilog code and simulated using the Cadence NCLaunch tool. The RTL code is synthesized to convert the gate-level netlist using the Genus tool from Cadence. Reporting the power, area & timing of the gate-level netlist. The generated gate-level netlist is used for placement and routing in the physical design process. The placement and routing of the shift register circuit are carried out in the Cadence Innovus tool using the 180nm library file. Reporting power, area, and timing at each stage of Pre-CTS, Post-CTS, and post-routing of the circuit and GDS II file is generated. In Post-CTS the overall Power is abridged to 12.69mW, Area is 119.7504um^2 and timing is 9787ps.

In this paper we present the first generation of a secure platform developed by following a security-by-design approach. The security of the platform is built on top of two pillars: a secured hardware design flow and a secure microkernel. The hardware design is protected against the insertion of hardware Trojans during the production phase through netlist obfuscation provided by logic locking. The software stack is based on a trustworthy and verified microkernel. Moreover, the system is expected to work in an environment which does not allow physical access to the device. Therefore, on-the-field attacks are only possible via software. We present a solution whose security has been achieved by relying on simple and open hardware and software solutions, namely a RISC-V processor core, open-source peripherals and an seL4--based operating system.

Circuit simulators have the capability to create virtual environment to test circuit design. Simulators save time and hardware cost. However, when components in circuit design increase, most simulators take longer time to test large circuit design, in many cases days or even weeks. Therefore, to handle large dataset and accurate performance, simulators need to be improved. In this paper, we propose machine learning-based parallel implementations of circuit analyser on graphics card with Compute Unified Device Architecture (CUDA). After parsing netlist file, the first approach is to analyse compute intensive mathematical functions and then convert it into parallel executable version. Further, we propose a Design-Level Parallelism with hybrid parallel implementation of components and processing methods. Dynamic decision-making is required to select functions and parameters to map on Graphics Processing Unit (GPU). To reduce load overhead, machine learning clustering approach has been adopted. Combination of procedure clustering and mapping takes few cycles but overall performance enhances efficiency as compared to serial processing.

The recycling of used integrated circuits (ICs) has raised serious problems in ensuring the integrity of today’s globalized semiconductor supply chain. This poses a serious threat to critical infrastructure due to potentially shorter lifetime, lower reliability, and poorer performance from these counterfeit new chips. Recently, we have proposed a highly effective approach for detecting such chips by exploiting the power-up state of on-chip SRAMs. Due to the symmetry of the memory array layout, an equal number of cells power-up to the 0 and 1 logic states in a new unused SRAM; this ratio gets skewed in time due to uneven NBTI aging from normal usage in the field. Although this solution is very effective in detecting recycled ICs, its applicability is somewhat limited as a large number older designs do not have large on-chip memories. In this paper, we propose an alternate approach based on the initial power-up state of scan flip-flops, which are present in virtually every digital circuit. Since the flip-flops, unlike SRAM cells, are generally not perfectly symmetrical in layout, an equal number of scan cells will not power-up to 0 or 1 logic states in most designs. Consequently, a stable time zero reference of 50% logic 0s and 1s cannot be used for determining the subsequent usage of a chip. To overcome this key limitation, we propose a novel solution in this paper that reliably identifies used ICs from testing the part alone, without the need for any additional reference data or even the netlist of the circuit. Through scan testing of the IC, we first identify a significant number of asymmetrically stressed flip-flops in the design, divided into two groups. One group of flip-flops is selected such that it mostly experiences the 1 logic state during functional operation, while the other group mostly experiences the 0 state. The resulting differential stress during operation causes growing disparity over time in the number of 0s (and 1s) observed in these two groups at power-up. When new and unaged, these two groups behave similarly, with similar percentage of 1s (or 0s). However, over time the differential stress makes these counts diverge. We show that this changing count can be a measure of operational aging. Our simulation results show that it is possible to reliably detect used ICs after as little as three months of operation.

Manufacturing testing screens out defective chips. However, untrusted test environment raises several security/trust concerns. An attacker can tamper the test data to send defective/malicious chips to the market or reduce yield causing financial losses. In this paper, we investigate the adversarial tampering attack of the test data. We shed light on an untrusted test facility that targets reducing yield and deceiving the designer to spend more money on testing for diagnosis purposes. We assume the presence of design-for-security architectures to protect the Intellectual Property (IP) and hide the test data. We analyze the similarity between corrupted and simulated test data under faults. We show that even if the attacker fails to reverse engineer the original IP netlist or decrypt the test patterns and their responses, she/he can still deceive the designer by flipping few bits of the encrypted test patterns, which results in responses that comply with the simulated responses.

The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the difficulty of the problem is related to the fact that machinegenerated designs have been unable to match the quality of the human designer. The human designer typically recognizes blocks from a netlist and draws upon her/his experience to translate these blocks into a circuit that is laid out in silicon. The ability to annotate blocks in a schematic or netlist-level description of a circuit is key to this entire process, but it is a process fraught with complexity due to the large number of variants of each circuit type. For example, the number of topologies of operational transconductance amplifiers (OTAs) easily numbers in the hundreds. A designer manages this complexity by dividing this large set of variants into classes (e.g., OTAs may be telescopic, folded cascode, etc.). Even so, the number of minor variations within each class is large. Early approaches to analog design automation attempted to use rule-based methods to capture these variations, but this database of rules required tender care: each new variant might require a new rule. As machine learning (ML) based alternatives have become more viable, alternative forms of solving this problem have begun to be explored. Our effort is part of the ALIGN (Analog Layout, Intelligently Generated from Netlists) project [2, 3], which is developing opensource software for analog/mixed-signal circuit layout [1]. Our specific goal is to translate a netlist into a physical layout, with 24-hour turnaround and no human in the loop. The ALIGN flow inputs a netlist whose topology and transistor sizes have already been chosen, a set of performance specifications, and a process design kit (PDK) that defines the process technology. The output of ALIGN is a layout in GDSII format.

As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the research of electronic design automation (EDA) to make the technology node scaling happen. Graph is of great significance in the technology evolution since it is one of the most natural ways of abstraction to many fundamental objects in EDA problems like netlist and layout, and hence many EDA problems are essentially graph problems. Traditional approaches for solving these problems are mostly based on analytical solutions or heuristic algorithms, which require substantial efforts in designing and tuning. With the emergence of the learning techniques, dealing with graph problems with machine learning or deep learning has become a potential way to further improve the quality of solutions. In this paper, we discuss a set of key techniques for conducting machine learning on graphs. Particularly, a few challenges in applying graph learning to EDA applications are highlighted. Furthermore, two case studies are presented to demonstrate the potential of graph learning on EDA applications.

Hardware intellectual property (IP) theft is a major issue in today’s globalized supply chain. To address it, numerous logic locking and obfuscation techniques have been proposed. While locking initially focused on digital integrated circuits (ICs), there have been recent attempts to extend it to analog ICs, which are easier to reverse engineer and to copy than digital ICs. In this paper, we use algorithms based on evolutionary strategies to investigate the security of analog obfuscation/locking techniques. We present a genetic algorithm (GA) approach which is capable of completely breaking a locked analog circuit by finding either its obfuscation key or its obfuscated parameters. We implement both the GA attack as well as a more naive satisfiability modulo theory (SMT)-based attack on common analog benchmark circuits obfuscated by combinational locking and parameter biasing. We find that GA attack can unlock all the circuits using only the locked netlist and an unlocked chip in minutes. On the other hand, while the SMT attack converges faster, it requires circuit specification to execute and it also returns multiple keys that need to be brute-forced by a post-processing step. We also discuss how the GA attack can generalize to other recent analog locking techniques not tested in the paper.

Clock-less Wave-Propagated Pipelining is a long-known approach to achieve high-throughput without the over-head of costly sampling registers. However, due to many design challenges, which have only increased with technology scaling, this approach has never been widely accepted and has generally been limited to small and very specific demonstrations. This paper addresses this barrier by presenting WavePro, a generic and scalable algorithm, capable of skew balancing any combinatorial logic netlist for the application of wave-pipelining. The algorithm was implemented in the WavePro Compiler automation utility, which interfaces with industry delays extraction and standard timing analysis tools to produce a sign-off quality result. The utility is demonstrated upon a dot-product accelerator in a 65 nm CMOS technology, using a vendor-provided standard cell library and commercial timing analysis tools. By reducing the worst-case output skew by over 70%, the test case example was able to achieve equivalent throughput of an 8-staged sequentially pipelined implementation with power savings of almost 3×.

Logic locking has received a lot of attention in the literature due to its very attractive hardware-security characteristics: it can protect against IP piracy and overproduction throughout the whole IC supply chain. However, a large class of logic-locking attacks, the oracle-based ones, take advantage of a functional copy of the chip, the oracle, to extract the key that protects the chip. So far, the techniques dealing with oracle-based attacks focus on the netlist that the attacker possesses, assuming that the oracle is always available. For this reason, they are usually overcome by new attacks. In this paper, we propose a hardware security scheme that targets the protection of the oracle circuit, by locking the circuit when the, necessary for setting the inputs and observing the outputs, scan in/out process begins. Hence, no correct input/output pairs can be acquired to perform the attacks. The proposed scheme is not based on controlling global signals like test_enable or scan_enable, whose values can be easily suppressed by the attacker. Security threats are identified, discussed and addressed. The developed scheme is combined with a traditional logic locking technique with high output corruptibility, to achieve increased levels of protection.

Logic obfuscation emerged as an efficient solution to strengthen the security of integrated circuits (ICs) from multiple threats including reverse engineering and intellectual property (IP) theft. Emergence of Boolean Satisfiability (SAT) attacks and its variants have shown to circumvent the security mechanisms such as obfuscation and a plethora of its variants. A plethora of advanced security defenses to thwart the SAT attacks are introduced. Despite the effectiveness, the imposed overheads in terms of area and power are unacceptably high. In contrast, our current work focuses on devising an iterative, dynamic and intelligent SAT-hard clause generator for a given SAT-prone problem, termed as SATConda. The SATConda is a SAT-hard clause generator that utilizes a bipartite propagation based neural network model. The utilized model comprises multiple layers of artificial neural networks to extract the dependencies of literals and variables, followed by long short term memory (LSTM) networks to validate the SAT hardness. The SATConda is trained with conjunctive normal form (CNF) of the IC netlist that are both SAT solvable and SAT-hard. Further, the SATConda is equipped with a SAT-clause generator to convert a CNF from satisfiable (SAT) to unsatisfiable (unSAT) with minor perturbation (which translates to minor overheads) so that the SAT-attack cannot decrypt the keys. To the best of our knowledge, no previous work has been reported on neural network based SAT-hard clause or CNF translator for circuit obfuscation. We evaluate our proposed SATConda's empirical performance against MiniSAT, Lingeling and Glucose SAT solvers on ISCAS'85 benchmark circuits.

Superconducting single flux quantum (SFQ) technology using Josephson junctions (JJs) is an excellent choice for the computing fabrics of the future. Current recycling is a necessary technique for the implementation of large SFQ circuits with energy-efficiency, where circuit partitions with similar bias current requirements are biased serially. Though this technique has been verified for small scale circuits, it has not been implemented for large circuits as there is no trivial way to partition the circuit into circuit blocks with separate ground planes. The major constraints for partitioning are (1) equal bias current and (2) equal area for all the partitions; (3) minimize the connections between adjacent ground planes with high-cost for non-adjacent planes. For the first time, all these constraints are formulated into a cost function and it is minimized with the gradient descent method. The algorithm takes a circuit netlist and the intended number of partitions as inputs and gives the output as groups of cells belonging to separate ground planes. It minimizes the connections among different ground planes and gives a solution on which the current recycling technique can be implemented. The parameters of cost function have been initialized randomly along with minimizing the dimensions to find the solution quickly. On average, 30% of connections are between non-adjacent ground planes for the given benchmark circuits.

This paper presents Applique, a computationally efficient open source environment for wireless power transfer coil design. The system allows designers to rapidly design and simulate coils. Applique extracts coil parameters and backannotates the extracted values into a SPICE netlist model of the wireless power transfer coil. Applique then automatically executes SPICE and combines extracted inductances, capacitances, and resistances to provide the user with narrow or wideband impedance analysis, as well as component values for a functionally meaningful simplified circuit model. Final designs may then be exported to common PCB CAD software.

The FPGA circuit design usually adopts full-custom design method, it indicates that it is difficult to design and optimize an FPGA manually. So, we present FPTLOPT (FPGA Transistor-Level Optimization Tool) which supports a more complex FPGA architecture called general routing matrix (GRM) architecture, and also has higher-accuracy and higher-speed than COFFE [1]. To fit a more complex FPGA architecture, we use the regular matching method to automatically extract the circuits type and build the circuits netlist; To get the higher-accuracy, we predict the layout area by area model we build, then we precisely predict the layout post simulation delay by load model we build; To get the higher-speed, we devise the variable range greedy algorithm, to expanding range automatically. We also provide equalization kernel multi-thread acceleration that can change the thread number according to the current CPU hardware environment. The experimental results illustrate that FPTLOPT supports the optimization of GRM architecture and build the key sub-circuit netlist. Also, the area prediction is by maximum of 43%, the delay get from delay prediction is 28% more precise than the ones in COFFE. Besides, quickly gets the optimal transistor sizing results for different optimization objectives. For the same circuit, the optimization speed is 19.96 times faster than COFFE.

Memristive crossbar architecture with high device density is the most preferred structure to realize memristor based in-memory computing system. Typically, synthesized gate-level netlist of NOR and NOT gates is mapped to the memristive crossbar architecture to realize a given logic function. We analyze the impact of radiation induced Single Event Transients (SETs) on such architectures. CMOS drivers are used to drive the wordline and bitline of the memistor array. These drivers are susceptible to incident particle strikes. The SETs generated can result in undesirable effects while executing a logic function. We also analyze SET induced crosstalk noise due to interconnect coupling effects in the array. Detailed SPICE level simulations on crossbar array has shown SETs resulting from single and multiple particle strikes can worsen the execution delay of NOR/NOT gate, trigger state drift in memristor(s), or flip memristor state (i.e., single event upset). For example, for single particle strike with LET 50, the memristor delay worsened by 5X.

Logic locking is a promising design-for-trust solution to the hardware IP piracy problem. Early logic locking methods for combinational circuits were susceptible to Boolean satisfiability (SAT) based attacks. Recently proposed SAT-based attack methods have shown success in unlocking locked sequential logic circuits without scan chain access. This paper introduces a new logic locking scheme that locks a sequential circuit on the occurrence of a chosen rare state transition. A novel approach to selecting suitable states for the ‘locking’ transition using the gate-level netlist of the design is proposed. Two unique methods to estimate the rarity of occurrence of the chosen states are discussed. Additionally, techniques to increase the error rate of the locked design are presented. The attack resiliency of the proposed technique against the Sequential SAT attack is demonstrated using several standard benchmark circuits.

It is well known that solving a sparse system of linear equations is the workhorse critical step in analog and RF circuit simulation. The LU factorization of sparse system matrix is a key operation in order to solve a system of linear equations. Extracting parallelism to factorize a sparse matrix requires knowledge of pattern of non-zeros in the matrix. Exploiting the fact that sparsity patterns of matrices involved in circuit simulations do not change across iterations, the schedule of computing steps of LU factorization can be statically determined and analyzed for parallelism. This approach has been well investigated by [1] and [2] in recent years. Our work improvises this well-researched approach and exposes more parallelism, thereby yielding improved results (by factor up to 2). The accelerated design is prototyped using custom high-level-synthesis tool specific to LU decomposition problem.The case of RF Circuits is treated slightly differently. Such circuits have a number of nonlinear components. Periodic steady state response can be determined efficiently using Harmonic Balance method even when amplitudes are not small. Acceleration of this method has been a subject of vigorous interest in recent years [4], [7]. The system matrix appearing in this method is a sparse set of tiles whose solution can benefit from the techniques mentioned above. The sparsity pattern is inherited from the circuit connections. This paper describes FPGA-and manycore-based acceleration of automated Harmonic Balance (HB) simulator which simulates a circuit with a netlist similar to SPICE. Our 100MHz custom digital design on the FPGA of ZedBoard (XC7Z020) yields a speed up of up to 4.39 over the on-chip dual Core ARM Cortex-A9, 666 MHz processor. And on Intel’s Xeon Phi Knights Landing (KNL) manycore chip, we obtain a speed up of up to 8.96 over a 4-core Intel i7 processor running at 3GHz clock frequency.

The paper presents a new iterative Boolean satisfiability (SAT) based approach to the routing of the switch blocks in an island-style reconfigurable system-on-a-chip. The detailed routing procedure results in obtaining the optimal combination of switches, multiplexors or tri-state buffers, inside a switch block. All the assigned interconnections should be completely routed without any conflicts. Within the SAT based approach each actually used switch block is presented as a Boolean equation system that is processed by the SAT-solver. In this paper the detailed routing task is solved for the switch blocks of two architectures. Their main difference is the quantity of tracks the current pin of switch block can be connected to. The computational experiments prove the efficiency of the considered method. The algorithm implemented in C programming language meets the requirements of the netlist full routability and minimization of routing runtime.

In this paper, we will cover several techniques that can enhance the resilience of timing of digital circuits. Using post-silicon tuning components, the clock arrival times at flip-flops can be modified after manufacturing to balance delays between flip-flops. The actual delay properties of flip-flops will be examined to exploit the natural flexibility of such components. Wave-pipelining paths spanning several flip-flop stages can be integrated into a synchronous design to improve the circuit performance and to reduce area. In addition, with this technique, it cannot be taken for granted anymore that all the combinational paths in a circuit work with respect to one clock period. Therefore, a netlist alone does not represent all the design information. This feature enables the potential to embed wave-pipelining paths into a circuit to increase the complexity of reverse engineering. In order to replicate a design, attackers therefore have to identify the locations of the wave-pipelining paths, in addition to the netlist extracted from reverse engineering. Therefore, the security of the circuit against counterfeiting can be improved.

Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware. We present a novel method for designing neural network topologies that directly map to a highly efficient FPGA implementation. By exploiting the equivalence of artificial neurons with quantized inputs/outputs and truth tables, we can train quantized neural networks that can be directly converted to a netlist of truth tables, and subsequently deployed as a highly pipelinable, massively parallel FPGA circuit. However, the neural network topology requires careful consideration since the hardware cost of truth tables grows exponentially with neuron fan-in. To obtain smaller networks where the whole netlist can be placed-and-routed onto a single FPGA, we derive a fan-in driven hardware cost model to guide topology design, and combine high sparsity with few-bit activation quantization to limit the neuron fan-in. We evaluate our approach on two tasks with very high intrinsic throughput requirements in high-energy physics and network intrusion detection. We show that the combination of sparsity and few-bit activation quantization results in high-speed circuits with small logic depth and low LUT cost, demonstrating competitive accuracy with less than 15 ns of inference latency and throughput in the hundreds of millions of inferences per second.

Recently, due to the increase of outsourcing in integrated circuit (IC) design and manufacturing, the threat of injecting a malicious circuit, called a hardware Trojan, by third party has been increasing. Machine learning has been known to produce a powerful model to detect hardware Trojans. But it is recently reported that such a machine learning based detection is weak against adversarial examples (AEs), which cause misclassification by adding perturbation in input data. Referring to the existing studies on adversarial examples, most of which are discussed in the field of image processing, this paper first proposes a framework generating adversarial examples for hardware-Trojan detection for gate-level netlists utilizing neural networks. The proposed framework replaces hardware Trojan circuits with logically equivalent circuits, and makes it difficult to detect them. Second, we define Trojan-net concealment degree (TCD) as a possibility of misclassification, and modification evaluating value (MEV) as a measure of the amount of modifications. Third, judging from MEV, we pick up adversarial modification patterns to apply to the circuits against hardware-Trojan detection. The experimental results using benchmarks demonstrate that the proposed framework successfully decreases true positive rate (TPR) by at most 30.15 points.

State-of-the-art attacks against cyclic logic obfuscation use satisfiability solvers that are equipped with a set of cycle avoidance clauses. These cycle avoidance clauses are generated in a pre-processing step and define various key combinations that could open or close cycles without making the circuit oscillating or stateful. In this paper, we show that this pre-processing step has to generate cycle avoidance conditions on all cycles in a netlist, otherwise, a missing cycle could trap the solver in an infinite loop or make it exit with an incorrect key. Then, we propose several techniques by which the number of cycles is exponentially increased as a function of the number of inserted feedbacks. We further illustrate that when the number of feedbacks is increased, the pre-processing step of the attack faces an exponential increase in complexity and runtime, preventing the correct composition of cycle avoidance clauses in a reasonable time. On the other hand, if the pre-processing is not concluded, the attack formulated by the satisfiability solver will either get stuck or exit with an incorrect key. Hence, when the cyclic obfuscation under the conditions proposed in this paper is implemented, it would impose an exponentially difficult problem for the satisfiability solver based attacks., Comment: arXiv admin note: substantial text overlap with arXiv:1804.09162

The outsourcing of the design and manufacturing of integrated circuits (ICs) in the current horizontal semiconductor integration flow has posed various security threats due to the presence of untrusted entities, such as overproduction of ICs, sale of out-of-specification/rejected ICs, and piracy of Intellectual Properties (IPs). Consequently, logic locking emerged as one of the prominent design for trust techniques. Unfortunately, these locking techniques are now inclined to achieve complete Boolean satisfiability (SAT) resiliency after the seminal work published in Subramanyan et al. (in: International Symposium on Hardware 907 Oriented Security and Trust, pp 137–143, 2015). In this paper, we propose a novel oracle-less attack that is based on the topological analysis of the locked netlist even though it is SAT-resilient. The attack relies on identifying and constructing unit functions with a hypothesis key to be searched in the entire netlist to find its replica. The proposed graph search algorithm efficiently finds the duplicate functions in the netlist, making it a self-referencing attack. This proposed attack is extremely efficient and can determine the secret key within a few minutes. We have also proposed a countermeasure to make the circuit resilient against this topology-guided attack to progress toward a secure logic locking technique.

Due to its complexity, the physical design process is divided into several primary steps. Having introduced in Chap. 4 the flow, constraints and methodologies of today’s physical design process, we now investigate the various steps required to generate its output: a layout. These steps, which transform a netlist into optimized mask data, are dealt with one by one in this chapter. A layout is generated from a netlist. We first describe how a netlist is created, that is, either by using hardware description languages (HDLs) in digital design (Sect. 5.1), or by deriving it from a schematic, as is common in analog design (Sect. 5.2). Then the physical design steps, comprising partitioning, floorplanning, placement, and routing, are presented in detail (Sect. 5.3). All of these steps are supported by highly sophisticated EDA tools in the case of digital designs, which is our focus here. We also discuss in this section the key aspects of symbolic compaction, standard-cell design and PCB design. When the physical design phase is completed, the resulting layout must be verified. This verification step confirms both functional correctness and design manufacturability. Methodologies and tools for comprehensive design verification, with a focus on physical verification, are covered in Sect. 5.4. Finally, we briefly touch on layout post-processing methodologies, such as resolution enhancement techniques (RET), that might impact physical design (Sect. 5.5).

A sub-circuit can use an existing symbol, either by modifying an existing one, or by downloading from the Internet; or by creating one from scratch. And it can be useful to have a symbol for, say, a variable resistor, which we create from an assembly of lines and shapes that can be sized, rotated, moved and copied. We then add and name pins in the netlist order. We use the Symbol Attribute dialogue to assign a ‘Type’, ‘Prefix’ and optionally ‘SpiceModel’ to associate the symbol with a model file and ‘Value’ and ‘Value2’ fields to supply default values and then the ‘SpiceLine’, ‘SpiceLine2’ and ‘ModelFile’ fields to specify a library and optionally prevent it being edited.

International audience; Electronics are increasingly susceptible to energetic particle interactions within the silicon. In order to improve the circuit reliability under radiation effects, several hardening techniques have been adopted in the design flow of VLSI systems. This paper proposes a pin assignment optimization in logic gates to reduce the Single-Event Transient (SET) cross-section and improve the in-orbit soft-error rate. Signal probability propagation is used to assign the lowest probability to the most sensitive input combination of the circuit by rewiring or pin swapping. The cell optimization can reach up to 48% reduction on the soft-error rate. For the analyzed arithmetic benchmark circuits, an optimized cell netlist can achieve from 8% to 28% reduction on the SET crosssection and in-orbit soft-error rate at no cost in the circuit design area. Additionally, as the pin swapping is a layout-friendly technique, the optimization does not impact on the cell placement and it can be adopted along with other hardening techniques in the logic and physical synthesis.

Logic Locking is a well-accepted protection technique to enable trust in the outsourced design and fabrication processes of integrated circuits (ICs) where the original design is modified by incorporating additional key gates in the netlist, resulting in a key-dependent functional circuit. The original functionality of the chip is recovered once it is programmed with the secret key, otherwise, it produces incorrect results for some input patterns. Over the past decade, different attacks have been proposed to break logic locking, simultaneously motivating researchers to develop more secure countermeasures. In this paper, we propose a novel stuck-at fault-based differential fault analysis (DFA) attack, which can be used to break logic locking that relies on a stored secret key. This proposed attack is based on self-referencing, where the secret key is determined by injecting faults in the key lines and comparing the response with its fault-free counterpart. A commercial ATPG tool can be used to generate test patterns that detect these faults, which will be used in DFA to determine the secret key. One test pattern is sufficient to determine one key bit, which results in at most $\vert\pmb{K}\vert$ test patterns to determine the entire secret key of size $\vert\pmb{K}\vert$ . The proposed attack is generic and can be extended to break any logic locked circuits.

Reverse engineering of integrated circuits, i.e., understanding the internals of Integrated Circuits (ICs), is required for many benign and malicious applications. Examples of the former are detection of patent infringements, hardware Trojans or Intellectual Property (IP)-theft, as well as interface recovery and defect analysis, while malicious applications include IP-theft and finding insertion points for hardware Trojans. However, regardless of the application, the reverse engineer initially starts with a large unstructured netlist, forming an incomprehensible sea of gates. This work presents DANA, a generic, technology-agnostic, and fully automated dataflow analysis methodology for flattened gate-level netlists. By analyzing the flow of data between individual Flip Flops (FFs), DANA recovers high-level registers. The key idea behind DANA is to combine independent metrics based on structural and control information with a powerful automated architecture. Notably, DANA works without any thresholds, scenario-dependent parameters, or other “magic” values that the user must choose. We evaluate DANA on nine modern hardware designs, ranging from cryptographic co-processors, over CPUs, to the OpenTitan, a stateof- the-art System-on-Chip (SoC), which is maintained by the lowRISC initiative with supporting industry partners like Google and Western Digital. Our results demonstrate almost perfect recovery of registers for all case studies, regardless whether they were synthesized as FPGA or ASIC netlists. Furthermore, we explore two applications for dataflow analysis: we show that the raw output of DANA often already allows to identify crucial components and high-level architecture features and also demonstrate its applicability for detecting simple hardware Trojans. Hence, DANA can be applied universally as the first step when investigating unknown netlists and provides major guidance for human analysts by structuring and condensing the otherwise incomprehensible sea of gates. Our implementation of DANA and all synthesized netlists are available as open source on GitHub., IACR Transactions on Cryptographic Hardware and Embedded Systems, Volume 2020, Issue 4