On Die PSIJ Methodology for High Speed IO

A methodology for On-Die Power Supply Induced Jitter (PSIJ) for High Speed IO is put forth. The approach accurately estimates the jitter induced due to currents of various blocks through the power distribution network (PDN). The analysis relies on simulations of Detailed Standard Parasitic Format (DSPF) netlist of circuit blocks along with post layout PDN network. A model order reduced distributed RC network of PDN is computed to reduce the simulation times due to huge PDN network with millions of nodes. This allows designers to perform accurate PSIJ estimation along with identifying the buffers causing higher jitter due to ripple seen on their PG pins, thus optimizing circuit blocks. The analysis can drive decisions regarding die capacitance partitioning and requirements for regulation on various circuit blocks.