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In this work, hydrogen (H) plasma treatment is implemented to dope indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), and indium oxide (In

We evaluate the use of the thick buried oxide (BOX) of Fully Depleted Silicon-on-Insulator (FD-SOI) transistors for Total Ionizing Dose (TID) measurements in a radiotherapy application. The devices were fabricated with a custom process in Université Catholique de Louvain (UCL) which allows to make accumulation mode PMOS transistors and inversion mode NMOS transistors. We characterized the temperature behavior of these devices and the response under X-ray radiation produced by an Elekta radiotherapy linear accelerator, and compared the obtained dose sensitivity to other published works. Taking advantage of these devices, an ultra low power MOS ionizing dose sensor, or MOS dosimeter, with inherent temperature compensation is presented. This dosimeter achieved a sensitivity of 154 mV/Gy with a temperature error factor of 13 mGy/°C and a current consumption below 1 nA.

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K in short-channel devices are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

In this paper, for the first time, we apply the ultra-low-power (ULP) diode concept with Schottky Barrier (SB) transistors and analyze the performance in comparison to standard CMOS, using calibrated TCAD mixed-mode simulations. The negative impedance characteristics obtained in reverse mode with SB devices are shown to offer superior current performance compared to CMOS, especially as a function of temperature.

We developed a low-cost process for assembling versatile sensors without expensive, thick metal finish on rigid and flexible PCB using anisotropic conductive films (ACF) flip-chip (FC) process. This allows a lower temperature budget than conventional FC assembly. The ACF FC process requires no expensive set up, is quick to implement and suits perfectly for sensor prototyping and low-scale manufacturing. The process was directly applied to assemble the bare die of a CMOS strain gauge sensor on flexible PCB without compromising its integrity.

The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufacturing. Several solutions are available on market with efficient robustness and compliant with the ESD window especially in 28 nm FD-SOI technology. In the framework of harsh environment applications and to explore the performance under total ionizing dose (TID) radiation, it is important to investigate ESD protection devices such as gated and STI diodes in hybrid bulk or BIMOS solution in thin silicon film. This study is based on transmission line pulse (TLP) characterization before and after Co60 TID radiation in the range of [25 krad–200 krad]. This dose range is chosen for a first robustness exploration and in link with product applications. Following this analysis, we expect to gain better understanding of robustness and push the final performance of the device. The preliminary results will be useful to give a trend and to improve the device robustness against ESD and TID events and lead to more competitive solutions.

This article aims at providing a better behavior understanding and performance evaluation of a large-size passive on-chip tapped transformer when used as a transducer in low-frequency integrated microsystems [30–300 kHz]. Thus, a CMOS-based 1:1 transformer, consisting of 70 turns of 1.6- $\mu \text{m}$ -wide top-level metal spaced by 0.6 $\mu \text{m}$ and with a total length of 1.7 mm, has been investigated and tested. The spatial separation between the two transformer windings was set to 70 $\mu \text{m}$ . An electrical equivalent lumped model has been extracted through an exhaustive specific measurement procedure. The model is useful to simulate and evaluate the voltage transformation ratio (TR) between the two transformer windings. The effects of parasitics and imperfect coupling between transformer windings and through the silicon substrate are outlined from the circuit point of view. We report a magnetic coupling coefficient that does not exceed $k=0.15$ , with a voltage TR of about 0.39 around the resonance frequency of ~5.3 MHz, when the secondary is unloaded. It has been proven that the interwindings capacitance introduced by close conductors of each winding, evaluated to 13 pF, assures the most important role in the power transfer. This article has shown that by optimizing properly the transformer realization and limiting some parasitics elements, the inductive and capacitive links could both play a key role in MEMS transducers through tapped transformers operation around 100-kHz frequencies.

This paper presents an evaluation of mismatching impact on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. This study is carried out by means of electrical measurements and two-dimensional numerical simulations, comparing GC to uniformly doped transistors. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.

© 2018, Brazilian Microelectronics Society. All rights reserved.This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The in-fluence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measure-ments. The transconductance, output conductance, Early volt-age and intrinsic voltage gain have been used as figures of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been ob-tained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain. 13 2 1 7

Duobinary modulation is a robust and attractive coding format for high-speed serial data transmission because it allows an excellent tradeoff between speed, noise and power. However, conventional architectures reported in the literature performing the necessary precodification in a duobinary transceiver suffer from a severe vulnerability to glitches that limits their performances at high data rates. This study presents a new precoder scheme that overcomes this limitation with a very small design, area and power consumption, and a time-domain analysis that confirms the advantages of the proposed solution. The proposed precoder has been implemented in a full duobinary transceiver fabricated in a 0.13-μm partially depleted-silicon on insulator CMOS technology that works at 10 Gb/s. The fabricated precoder consumes 13.8 mW and the decoder consumes 23.2 mW from a single supply of 1.2 V. Experimental results are provided for a simulated channel of 50-m plastic optical fiber.

Terahertz rectifying antennas (rectennas) couple micron-size antennas and high-speed diodes to convert the incident electro-magnetic radiation to useable DC power. At such frequencies, the device acting as the diode requires both a nonlinear electrical behavior and a very low parasitic capacitance. Due to their low-capacitance planar structure and high carrier mobility values, several graphene devices based on various rectification mechanisms have been previously proposed as the rectifying device in the terahertz range. In this paper, we report an asymmetric behavior in micrometer-scale rectangular CVD-grown graphene field-effect transistors (GFETs), both at 77 K and room temperature (295 K). The asymmetry with a measured I ON /I OFF ratio as high as 1.85 is shown to originate from the slight change in graphene conductivity induced by drain-gate voltage variations. This is confirmed by simulations using a simple drift-diffusion transport model. The conclusions can be directly applied to optimize diode-connected GFETs. This nonlinear effect may also be of interest for graphene interconnect considerations as well as circuit designs using GFETs.

In this paper, for the first time, we apply the ultra-low-power (ULP) diode concept with Schottky Barrier (SB) transistors and analyze their performance in comparison to standard CMOS, using calibrated TCAD mixed-mode simulations. The negative impedance characteristics obtained in reverse mode with SB devices are shown to offer more stable current characteristics compared to CMOS, especially as a function of temperature. The origin of this behavior manifests itself in the fact that carriers tunneling through the barrier by field emission and carriers overcoming the barrier by thermionic emission both contribute to the total device current. This enables superior current performance over temperature. This enables ultra-low-power memory application over a larger temperature range, or with a denser cell area.

In this paper, negative transconductance (NTC) behavior in molybdenum disulfides (MoS2) field effect transistors (FETs) is investigated. Combining experimental observation and numerical analysis, we demonstrate that positive shift in the device transfer curves results from the electron trapping/de-trapping processes, where the defect densities at the MoS2/SiO2 interface are reduced when the temperature T decreases from 300 to 200 K. Moreover, the main types of defects that affect the device electrical performance are the interface defect and bulk sulfur vacancy VS in which VS induces the p-type doping effect. While decreasing T below 100 K, NTC occurs when their active layer thickness t (=41 and 35 nm) is larger than the Debye length λ (28 nm). Considering the n-type doping effect induced by the interface defects and the p-type doping caused by the bulk S vacancies, these two opposite doping regions are carefully implemented in simulation at T = 70 K. A vertical barrier induced by the inhomogeneous electron distribution enlarges with the increased gate bias VGS and, thereafter, leads to the unconventional increase in the contact and total resistances with t > λ. While t ≦ λ, the barrier and NTC behavior disappear. The current IDS and transconductance g obtained from the simulation confirm the low-temperature NTC mechanism related to the defects as discussed above. The material defects and physical origin of NTC discussed in the multilayer MoS2 transistors provide the theoretical foundation for designing and realizing novel structures of functional devices via defect engineering in the two-dimensional FET.

In this paper, we present a detailed analysis of leakage current in a silicon-on-insulator (SOI) lateral P+P−N+ (p-i-n) diode suspended on a microheating platform, combining device experimental characterization and numerical simulation. The diode leakage currents have been extensively studied using the back-gate bias as a means to alter the space-charge (SC) condition at the P− region (I-region)/buried oxide interface from accumulation to full depletion, and finally to inversion. Both dark leakage current analysis and low-frequency noise characterization performed on the suspended SOI lateral p-i-n diode indicate device degradation induced by microelectromechanical systems postprocessing (i.e., deep reactive-ion etching or aluminum deposition). A low-temperature (~250 °C) in situ (i.e., using embedded microheater) annealing of SOI lateral p-i-n diode after postprocessing allows reduction of the diode leakage current and optimization of the device performance by neutralizing the interface traps and improving carriers’ lifetime and surface recombination velocity. Numerical simulations have been performed with Atlas/SILVACO for deeper analysis of the leakage current behavior in the lateral p-i-n diode and identification of the generation mechanism dominating the diode leakage behavior. Simulation reveals that the dominant generation rate in the diode depends on the SC conditions, the interface trap density, and the carriers’ lifetime in the I-region. The experimental and simulated behaviors of “as processed” and annealed diode leakage current are shown to be in good qualitative agreement.

Power Si/SiC LDMOSFET are being developed for the benefits of high temperature space and terrestrial harsh-environment applications. For the first time, high voltage devices are fabricated on a direct bonded Si/SiC substrate and characterised at room temperature. Peak field-effect channel mobility of the fabricated MOSFET reached ≈300 cm2/V.s and the avalanche breakdown was not observed up to 200 V, despite of a high leakage current in the device off-mode.

Thin-film lateral SOI p-i-n diodes can be used as photodetectors especially in the wavelength range of blue and ultra-violet (UV) radiation. Unlike vertical devices, lateral diodes can have depletion regions very close to the device surface, where the absorption of low-wavelengths radiation takes place. Due to this proximity to the surface, an MOS back-gate can control the charge density inside this region, allowing quantum efficiency improvement. This paper reports experimental results of SOI p-i-n photodetectors with different intrinsic lengths in the 300-500-K range, simultaneously considering back-gate bias and temperature influences. Indeed, the back-gate bias becomes very effective in terms of quantum efficiency control with up to 52.4% for $\text {L$_{\mathrm {I}}$}=1\mu \text{m}$ at $T=500$ K in inversion mode, while in accumulation, the resulting efficiency was 48.2% at $T=500$ K for the device with $\text {L$_{\mathrm {I}}$}= 10\,\,\mu \text{m}$ at UV. These variations are related to the behavior of dark current and the recombination rate of the devices.

This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1 ${\mu }\text{m}$ fully depleted SOI complementary metal-oxide semiconductor technology was employed to manufacture the devices. We observe that the octagonal layout style for MOSFETs is capable of maintaining its better electrical performance (for 573 K: a reduction of the leakage drain current of 65%, an increase of 159% in the saturation drain current, and an increase of 175% in the unit voltage gain frequency) in comparison to the standard rectangular counterpart. This happens because the longitudinal corner effect and parallel connection of MOSFETs with different channel lengths effect continue to function at high temperatures. Therefore, the octagonal layout style can be considered as an alternative hardness-by-design approach to boost the electrical performance of n-type SOI MOSFETs in high-temperature environments, without causing any extra burden for any current planar SOI MOSFET manufacturing process.

This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.

This work investigates the low-frequency noise performance of a long-channel UTBB FD SOI nMOS transistor operated in triode region as typically used for MOSFET-C filter applications. Measurements of the low-frequency noise have been performed over a large temperature range (25–125°C) at different constant currents above threshold, as a function of the back-gate bias. It is highlighted that in such case, 1/f noise power is dominant, however sufficiently low, in the frequency range of interest for the filters, i.e. below 1 MHz. Noise power strongly reduces with temperature and slightly with positive back-gate bias, which is adequate for the filter tuning.

The growing interest in detecting specific volatile organic compounds (formaldehyde, toluene, xylene, etc.), toxic or even carcinogenic, involves new techniques to ensure both selectivity and sensitivity of gas sensors. Furthermore, the indoor pollution monitoring requires small, low power and wireless module. Looking at novel metal oxide (MOX) gas sensors, the working temperature is critical for selectivity. Its good regulation ensures an optimized tradeoff between the response time, the recovery time and the sensitivity [1] . Finally, the baseline resistance is humidity dependent and requires compensation.

This work studies, for the first time to the authors’ best knowledge, the self-heating (SH) effect in ultra-thin body ultra-thin BOX (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, is employed to assess SH parameters and related degradation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating on analog FoMs is slightly weaker at cryogenic temperatures with respect to room-temperature case. The extracted thermal resistance and channel temperature rise at 300 K and 77 K are of the same order of magnitude. The observed increase in SH characteristic frequency with temperature reduction emphasizes the advantage of the RF technique for the fair analysis of SH-related features in advanced technologies at cryogenic temperatures.

This paper presents an analysis of the harmonic distortion extracted from simulated results of symmetric and asymmetric self-cascode devices (S-SC and A-SC, respectively) composed by ultra-thin body and BOX fully depleted silicon-on-insulator planar MOSFETs 28 nm technological node. The results show that the A-SC effectively increases the operating drain current range for lower distortion. Comparisons with the literature show that the A-SC structures are a promising option for enhancing the circuit design flexibility for advanced MOSFETs.

This paper proposes a general methodology for designing noise-canceling low noise amplifiers (LNA). The procedure provides designers a more accurate information of the topology trade-offs in the technology and which restrictions must be imposed to design variables to attain target specifications. Thus, it is especially desirable when opposite specification, such as cut-off frequency, linearity, noise figure or power consumption are required. A CG-CS LNA in a 45 nm SOI CMOS technology is presented, although authors give guidelines to extrapolate the method to other topologies and technologies.

Este trabajo propone una metodología para la optimización de amplificadores de bajo ruido (LNA). El sistema propuesto proporciona una mejor información al diseñador acerca de los compromisos entre las especificaciones deseadas y las variables que puede modificar. Se ha realizado un diseño en tecnología CMOS de 45 nm para la comprobación del método

We present a new methodology to discriminate random telegraph noise (RTN) and flicker (1/f) noise components from set-up noise. We illustrate it for a strong RTN case (ΔI D /I D ~~ 30%) measured on a 26nm gate length nMOS transistor. The approach is based on high-accuracy time-domain measurements. An iterative Schmitt trigger-like algorithm was developed to properly identify and model the RTN and 1/f noise. Statistical analysis allows to assess the accuracy of the extraction. The power spectral densities (PSD) of the different noise models accurately match the frequency measurements.

This work investigates the on-resistance and harmonic distortion (HD) of Ultra-Thin Body and Buried Oxide (UTBB) fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFETs for a typical process (TT) working in the triode regime, of interest for MOSFET-C filter applications. Circuit simulations of the DC characteristics of n- and p-type MOSFETs in a large temperature range (−2S°C-150°C) allow to identify the interest of the back-gate bias to compensate the shift of the on-resistance and 3rd - order HD with the temperature.

Near-threshold circuits operating at ultra-low voltage (ULV) have matured with integration in commercial products, such as ultra-low-power (ULP) MCUs for the IoT [1]. In this market, MCU design faces the key performance tradeoff between speed, active power, deep-sleep retention power and wakeup time, with the challenge of preserving it over PVT corners. We present a ULP MCU SoC in 28nm FDSOI codenamed SleepRunner, exploiting back-biasing (BB) capability of FDSOI to push the performance tradeoff beyond the state-of-the-art.

With continuous device scaling, avalanche breakdown in the two-dimensional (2D) transistors severely degrades device output characteristics and overall reliability. It is highly desirable to understand the origin of such electrical breakdown for exploring the high-performance 2D transistors. Here, we report an anomalous increase in drain currents of the black phosphorus (BP)-based transistors operating in saturation regime. Through the comprehensive investigation of various channel thicknesses, channel lengths and operating temperatures, it is attributed such novel behavior to the kink effect originating from impact ionization and related potential shift inside the channel, which is further confirmed by device numerical simulations. Furthermore, Nitrogen plasma treatment is carried out to eliminate the current anomalous increase and suppress the kink effect with improved saturation current. This work not only sheds light on the understanding of carrier transport within the BP transistor, but also could open up new potential for achieving high-performance and reliable electronic devices based on the 2D materials.

Wireless power transfer (WPT) has emerged as a solution for supplying smart sensors for long-term battery-less deployment. Because the amount of power harvested by the smart sensor is limited due to WPT path loss, the optimization objective is twofold: achieving ultra-low-power operation for the sensing task and improving the harvesting efficiency even at low incident power. In this paper, we focus on the use case of a Bluetooth LE-connected motion detection system supplied by 2.45-GHz RF power. The full system (RF energy harvester, power management, sensor transducer and interface, control, data processing and wireless transmission) is implemented using low-power off-the-shelf components. In the sensing sub-system, ultra-low-power operation is achieved by the duty-cycling of the sensor interface and by an event-driven scheme for communication. In the harvesting sub-system, the design of the matching network and rectifier, combined with maximum power point tracking (MPPT), is optimized for increasing the power harvesting efficiency (PHE) at low incident power. Measurements show a total reduction in the power consumption for the sensing sub-system by a factor 20. When using custom WPT waveform with high peak-to-average power ratio, the RF energy harvester is functional with an incident RF power starting from −20 dBm. The smart sensor is able to perform its motion-detection task with an incident power as low as −17.3 dBm.

In this work, we present a silicon-based p-i-n thermal diode, with post-CMOS MEMS processing (deep reactive ion etching and Al deposition) and annealing (at 250 °C). The MEMS processing degraded device stability as well as thermal sensing linearity and sensitivity, while the local annealing recovered the device performance (forward and reverse characteristics) by reducing the trap density and improving the carrier lifetime. After annealing, the on-membrane diode can achieve stabilized thermal linearity with a high sensitivity of ~ 2.25 mV/°C at 0.02– $0.03~\mu \text{A}$ low constant current, in the temperature range from room temperature to 200 °C, under a back-gate bias of 90 V to achieve a fully-depleted condition in the intrinsic (I) region and decrease the trap-assisted recombination at the front surface which dominates and degrades the device forward output current. To be compatible with commercial 1.0- $\mu \text{m}$ SOI CMOS technology, a front gate with a 25-nm-thick oxide dielectric is proposed and simulated in Atlas/SILVACO to optimize the device performance and achieve the same thermal characteristics under a front-gate bias of 1.0 V, showing its potential in low-power consumption electronics. The temperature sensor investigated in this work shows its industrial capability in gas sensing and integrated circuit applications.

In ultra-thin chalcopyrite solar cells and photovoltaic modules, efficient light management is required to increase the photocurrent and to gain in conversion efficiency. In this work we employ optical modelling to investigate different optical approaches and quantify their potential improvements in the short-circuit current density of Cu(In, Ga)Se2 (CIGS) devices. For structures with an ultra-thin (500 nm) CIGS absorber, we study the improvements related to the introduction of (i) highly reflective metal back reflectors, (ii) internal nano-textures applied to the substrate and (iii) external micro-textures by using a light management foil. In the analysis we use CIGS devices in a PV module configuration, thus, solar cell structure including encapsulation and front glass. A thin Al2O3 layer was considered in the structure at the rear side of CIGS for passivation and diffusion barrier for metal reflectors. We show that not any individual aforementioned approach is sufficient to compensate for the short circuit drop related to ultra-thin absorber, but a combination of a highly reflective back contact and textures (internal or external) is needed to obtain and also exceed the short-circuit current density of a thick (1800 nm) CIGS absorber.

This paper summarizes the outcome of the EC FP7 project MSP - Multi Sensor Platform for Smart Building Management (Grant Agreement No. 611887). The MSP consortium comprising 17 partners from 6 European countries developed a full manufacturing chain for 3D system integration, which has never been realized before. It enables 3D-integration of highly sophisticated components and sensor devices on a CMOS electronic platform chip. The final multi-sensor system comprises a variety of gas sensors as well as optical sensors for ultraviolet, visible and infrared light. The MSP demonstrator system implemented in a wearable wristband device integrates a total of 57 sensors - this is a worldwide unique sensor system.

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

Simultaneous wireless information and power transfer (SWIPT) is a flexible and cheap way to supply Internet-of-Things (IoT) smart sensors avoiding battery replacement. In this paper, we analyze, model, and design a 2.45-GHz RF energy harvesting (RFEH) system based on a discrete-component matching network (MN), a custom 65-nm CMOS cross-coupled rectifier, and an off-the-shelf storage-charging power management unit (PMU), which regulates the rectifier output voltage with maximum power point tracking (MPPT). We propose a reverse global analysis to model the RFEH. It allows an accurate prediction of the power harvesting efficiency (PHE) to directly size the MN and select the RFEH MPPT regulation ratio, at different incident RF power levels. We perform parasitic-aware RFEH design to take advantage of printed circuit board (PCB)/package capacitive parasitics at the rectifier input for optimizing the $\pi $ -MN with the help of the proposed RFEH modeling results. We show that this parasitic capacitance introduces a maximum bound on the real impedance at the rectifier input to ensure good impedance matching in practice. MPPT is used to help reach this target real impedance at given incident RF power, as the rectifier equivalent input impedance is a function of both its input and output voltages. Measurement results show a sensitivity as low as −17.1 dBm with a peak PHE of 48.3% at −3-dBm incident RF power. Global modeling, simulation, and measurement results demonstrate that the PHE is limited by PCB/package parasitic capacitance and that PCB/packaging technology improvement to reduce parasitic capacitance by 150 fF could boost the PHE up to 45% for a low incident RF power level of −10 dBm.

Here, the bilayer InGaZnO/In2O3 thin-film transistors (TFTs) are deposited by radio-frequency magnetron sputtering at room temperature. A high field-effect mobility (μFE) of 64.4 cm2 V−1 s−1 and a small subthreshold swing (SS) of 204 mV per decade are achieved in the bilayer-stack TFTs fabricated upon SiO2/Si substrate, with large improvement compared to the single layer InGaZnO and In2O3 TFTs. Implementing HfO2 and Si3N4 as high-k gate dielectrics, μFE and SS are correspondingly enhanced to be 67.5 and 79.1 cm2 V−1 s−1 , and 85 and 92 mV per decade in the bilayer TFTs. Defect self-compensation effect is also revealed, i.e., (In)+ + (O)− → In − O, while, respectively, considering the indium- and oxygen-related defects in InGaZnO and In2O3 and exploring the numerical simulations in SILVACO/Atlas (for electrical performance) and Quantum Espresso (for physical analysis). The In-O formation can result in a significant reduction in defect density (validated by the X-ray photoelectron spectra and low-frequency noise characterizations) and therefore improvement of μFE and SS in the bilayer-stack TFT. The important role of defect self-compensation mechanism while combining different individual channel layers in the oxide semiconducting TFTs is underlined and highly potential application in next-generation, fast-speed flexible displays is shown.

We present an ultra-thin lateral SOI PIN photodiode with transferred monolayer graphene as the transparent gate, to provide enhanced ultraviolet (UV) performance and mechanical flexibility beyond standard Si-based devices. The device dark current shows intact characteristics after the post-CMOS thinning and graphene transfer processing steps. The device responsivity presents high potential in UV and visible wavelength detections (i.e. within the 200-900 nm range) under monochromatic light illumination. A maximum responsivity of 0.18 A W-1 has been experimentally achieved at 390 nm wavelength and validated by simulation, for a diode with intrinsic length L i of 20 μm. Additionally, the ∼5 μm-thick device chip with direct board assembly paves the way towards the development of hybrid flexible electronics.

This work presents a detailed RF characterization of 28 FDSOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current gain cutoff frequency (f T ) and maximum oscillation frequency (f max ), as well as parasitic elements of the small-signal equivalent circuit are extracted from the measured S-parameters. The observed behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28 FDSOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

This letter investigates the large spread of values of capacitance measured in Si/TiO2 MIS structures for different properties of the TiO2 layer and proposes an approach to understand the behavior of the system. Experimental results show large variations of the maximum capacitance with TiO2 thickness for the as-deposited structures and further highlight the change of trend after annealing. Simulations qualitatively depict the theoretical trends explaining the C–V characteristics to the first order, by the different behaviors of the oxide layer in the structure and the distribution of the majority carriers showing depletion effects.

Sequential DC magnetron sputtering and rapid thermal processing appear very promising to fabricate CZTS-based thin-film photovoltaic (PV) solar cells with regards to existent environmental and industrial issues. However, their state-of-the-art efficiency remains limited to about 10% to date. In this work, we aim at optimizing the optical and electrical properties of the CZTS absorber by an extensive screening of their correlation with the material composition. This is widely varied by different deposition (i.e. thickness of precursors) and process (i.e. RTP) conditions. We assess the impact of absorber composition on the energy bandgap, absorption coefficient, p-type carrier concentration and mobility. The most important results lie in the extensive analysis of the inverse power-law trend for carrier concentration versus mobility and logarithmic trend versus bandgap. Our conclusions point the optimal composition ratios towards Cu-poor and less than actual target Zn-rich range. As a result, a potential roadmap is drawn up based on presented experimental results and SCAPS simulations in order to reach more than 10% cell efficiency with the target technology.

Cell aggregation plays a key role in biofilm formation and pathogenesis of Staphylococcus species. Although the molecular basis of aggregation in Staphylococci has already been extensively investigated, the influence of environmental factors, such as ionic strength, remains poorly understood. In this paper, we report a new type of cellular aggregation of Staphylococci that depends solely on ionic strength. Seven strains out of 14, all belonging to staphylococcal species, formed large cell clusters within minutes in buffers of ionic strength ranging from 1.5 to 50 mM, whereas isolates belonging to other Gram-positive species did not display this phenotype. Atomic force microscopy (AFM) with chemically functionalized tips provided direct evidence that ionic strength modulates cell surface adhesive properties through changes in cell surface charge. The optimal ionic strength for aggregation was found to be strain dependent, but in all cases, bacterial aggregates formed at an ionic strength of 1.5-50 mM were rapidly dispersed in a solution of higher ionic strength, indicating a reversibility of the cell aggregation process. These findings suggest that some staphylococcal isolates can respond to ionic strength as an external stimulus to trigger rapid cell aggregation in a way that has not yet been reported.

Here we demonstrate the influence of firing temperatures on the electronic properties of Atmospheric Pressure Plasma Liquid Deposition (APPLD) silicon dioxide films due to reformed material composition and its overall impact on surface passivation quality. Experimentally extracted electronic parameters using electrical capacitance-voltage-conductance (C-V-G) measurements on a Metal-Oxide-Semiconductor (MOS) structure reveal that films fired at 810 °C show a slightly higher concentration of negative fixed charges (− Qf) and interface trap charges (Dit) compared to films fired at 940 °C. Such a dependency on the firing temperature can be attributed to variation in the net concentrations of silanol and carbon groups within the films, subsequently influencing the type of passivation mechanism involved. We show that for films fired at 810 and 940 °C, the predominant passivation mechanisms are related to field effect induced by excess silanol groups and chemical passivation due to the absence of electrically active carbon related defects, respectively. Additionally, dielectric constant (K) extraction from C-V measurements at 1 kHz returns an almost 2-fold higher K-value for films fired at 810 °C (K ~ 21) compared to films fired at 940 °C (K ~ 12), due to excess silanol concentration in the former films.

A three-stage Greinacher rectifier is designed using ultra-low-leakage CMOS diodes and characterized at 13.56 MHz for a 1 Vpp sinusoidal input and a 10 μA load current in 250 nm CMOS bulk technology. The measured dc output voltage is 1.9 V with 72% power conversion efficiency providing a 19 μW output power. This ultra-low-power and high-efficiency ac/dc power converter with 0.13 mm 2 chip area can be used with RF energy harvesters to power implantable or wearable biomedical devices in body sensor networks. The automated design optimization methodology using a gradient method and foundry models is presented and discussed. The measured performances are presented for various frequencies, load currents, and input voltages. The robustness against process and temperature variations is studied through temperature measurements and corner simulations.

This paper reports on the performance of a silicon-on-insulator photodiode suspended on a dielectric membrane. The micro-hotplate platform consists of a micro-heater and a thin-film lateral P+/P−/N+ (PIN) photodiode. Without optimizing the multilayer stack on top of the PIN diode, experimental responsivities of the suspended photodiodes at room temperature (RT) are 0.02–0.06/W within the visible and near the IR light range, under a reverse bias of −2 V. Up to $2.5\times $ , responsivity improvement has been achieved with regard to the diodes on the substrate thanks to reflection from the gold finish layer of the device package acting as a bottom mirror. Optimizing the layer stack above the diode, the responsivity of the on-membrane device can be theoretically improved up to 0.09–0.11 A/W within 450–520-nm wavelength range. Measured from RT up to 200 °C, the photodiodes on membrane continuously show an improved optical response under high-power LED illumination. Assisted by the micro-heater as heat source, the suspended photodiode can work stably up to 200 °C with in situ temperature sensing and control, which makes it highly suitable and attractive for high-temperature application. Full 2-D ATLAS device simulations have been comprehensively performed to investigate the optical and electrical characteristics. Very good agreement has been achieved between the numerical simulations and the experimental data.