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In this paper, multiplexer based logic gates design is presented using ballistic deflection transistor. The three-parameter gaussian peak analytical model is integrated into behavioral modeling in the Verilog-AMS module to achieve the characteristics of ballistic deflection transistor. Also, the device is modeled and simulated on the Cadence AMS simulator and further the single ballistic deflection transistor is used to design the inverter/buffer circuit. The two ballistic deflection transistor is used to design the logic gates, which are based on the 2:1 multiplexer structure. The simulated results confirm the correct working of all logic gates.

Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become a major concern due to leakage currents; hence, researchers are continuously trying to evolve ways to mitigate this. Out of many such ways the use of carbon nanotube technology is a promising way to design low-power circuits, as carbon has a property of providing variable threshold voltage (VTH) in N-type transistors. Here simulation results confirm that CNTFET has better performance than MOS and FinFET technologies in low-power world. In this paper existing and proposed adiabatic logic is implemented by CNTFET technology at 32 nm in HSPICE by using Predictive Technology Model (PTM). Comparison of simulation results shows that proposed CNTFET-based ON–OFF-DCDB-PFAL adiabatic logic saves average power 94.33% in Buffer/NOT, 93.13% in NAND/AND, 93.14% in NOR/OR, 91.76% in XOR/XNOR when compared with 2N2N2P circuit at 10 MHz frequency.

We propose a very compact structure for all-optical XOR, XNOR, NAND and OR logic gates based on photonic crystal 3-dB coupler in binary-phase-shift-keyed (BPSK) signals. The square lattice of dielectric rods in SiO2 background has been considered for photonic crystal structure. The photonic band gap (PBG) and light propagation simulations of proposed logic structure have been accomplished by plane wave expansion and finite difference time domain methods. The proposed structure can achieve logical function when the refractive index of all rods and substrate is fabricated with relaxed error tolerance within −0.005 to 0.005 from designed parameters. The proposed logic functions may potentially be used as key components in all-optical information networks for processing the BPSK signals.

Graphene plasmonic logic gates (GPLGs) with high compaction and simple structure are presented and investigated in this paper. Due to the strong confinement of edge mode graphene surface plasmon polaritons (EGSPPs), it can process optical signal on nanoscale ribbons with both straight and flexible shapes. Three eigen modes of graphene surface plasmon polaritons (GSPPs) are studied from the aspect of their propagation properties, indicating that the symmetric edge-mode (SEM) is an optimal choice for designing the GPLGs. Finally, some basic logic gates, i.e., the XOR and XNOR gates, are demonstrated by employing the SEM. More kind of GPLGs and functional devices are expected to be realized by cascading these basic logic gates.

In the emerging field of $v\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}l\phantom{\rule{0}{0ex}}l\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}y\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}o\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}s$, logic gates are typically based on the valley-pseudospin degree of freedom in materials with particular electronic structures. For certain two-dimensional (2D) materials, the valley-dependent spin polarization is 100% and can be switched by an electric field. The authors design valley-spin logic gates based on certain 2D materials, and demonstrate seven complete logic gates: NOT, XNOR, XOR, AND, NAND, OR, and NOR. Importantly, the proposed valley-spin gates satisfy the concatenation requirement, which is key for practical use: The output of one can be used as the input for the next, and all inputs and outputs are plain voltages.

This paper proposes a brand new non-volatile XNOR logic-gate that works as both a logic-gate and a nonvolatile memory. It can unify a micro-processor and a memory and it is expected that it saves energy consumption associated with data transfer and enhances band-width of data transfer between the devices.

In this paper, Two Dimensional (2D) Photonic Crystal (PhC) based 3-input all optical NOR, NAND and XNOR gates is proposed and designed. The proposed device is formed by the combination of line defects and square cavity. The performance of the device is analyzed using 2D Finite Difference Time Domain (FDTD) method. The band gap analysis is done by Plane Wave Expansion (PWE) method. The device has the lattice constant and refractive index of 616 nm and 3.46, respectively. The dimension of the proposed structure is about 12.5 µm*12 µm which is highly compact and suitable for photonic integrated circuits (PIC).

In this paper, we aim to design an all-optical device, which can perform XOR and XNOR functions in a single structure. The proposed structure will be realized by cascading two nonlinear resonant ri...

QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 ?m2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

The trend of pushing inference from cloud to edge due to concerns of latency, bandwidth, and privacy has created demand for energy-efficient neural network hardware. This paper presents a mixed-signal binary convolutional neural network (CNN) processor for always-on inference applications that achieves 3.8 $\mu \text{J}$ /classification at 86% accuracy on the CIFAR-10 image classification data set. The goal of this paper is to establish the minimum-energy point for the representative CIFAR-10 inference task, using the available design tradeoffs. The BinaryNet algorithm for training neural networks with weights and activations constrained to +1 and −1 drastically simplifies multiplications to XNOR and allows integrating all memory on-chip. A weight-stationary, data-parallel architecture with input reuse amortizes memory access across many computations, leaving wide vector summation as the remaining energy bottleneck. This design features an energy-efficient switched-capacitor (SC) neuron that addresses this challenge, employing a 1024-bit thermometer-coded capacitive digital-to-analog converter (CDAC) section for summing pointwise products of CNN filter weights and activations and a 9-bit binary-weighted section for adding the filter bias. The design occupies 6 mm2 in 28-nm CMOS, contains 328 kB of on-chip SRAM, operates at 237 frames/s (FPS), and consumes 0.9 mW from 0.6 V/0.8 V supplies. The corresponding energy per classification (3.8 $\mu \text{J}$ ) amounts to a 40 $\times $ improvement over the previous low-energy benchmark on CIFAR-10, achieved in part by sacrificing some programmability. The SC neuron array is 12.9 $\times $ more energy efficient than a synthesized digital implementation, which amounts to a 4 $\times $ advantage in system-level energy per classification.

In this paper, we report the design, simulation, and some applications of a tunable graphene-based cylindrical resonator by analytical and numerical two-dimensional finite-difference time-domain methods. The base structure operates as a bandpass filter in the mid-infrared region. The tunability of the filter is achieved by changing the radius and/or the chemical potential of the graphene cylinder. Based on the proposed cylindrical resonator, a two-channel wavelength selector and some novel linear plasmonic logic gates are designed and proposed. The even- and the odd-order resonance modes are separated in the two-channel wavelength selector and are transmitted to the output graphene waveguides. Moreover, the plasmonic logic gates including XOR, XNOR, NAND, and NOT having the significant features such as linearity, compact size, and low loss are proposed. The analytical approach and the numerical simulations prove the excellent performance of the logic gates in comparison to the reported ones in the literature. The simulation results demonstrate that the maximum ON/OFF ratios for these plasmonic logic gates are 29.09, 28.78, 28.78, and 29.09 dB, respectively. The proposed functional ultra-compact nano-scale graphene-based structures offer potential basic blocks for mid-infrared optical computing and signal processing.

Using the knowledge that any gate can be built through different arrangements of micro-ring resonators, this paper proposes the all-optical design of XOR and XNOR logic gates. The gates structure thus consists of micro-ring resonators (MRR) paired with a constant source of light (COS). MRRs in these designs are utilized as modulators by tuning their resonant wavelengths. In this way, under no external disturbances, the rings are uncoupled by default. The proposed devices are CMOS-compatible meaning that they can be fabricated using the existing technologies. Also, to reduce the fabrication complexity of the proposed devices, thermo-optic modulation is employed as primary light modulating technique. The logic gates are tested at 25 kpbs. Device parameters are provided as well for manufacturing purposes. The study concludes with suggestions on design improvements and potential application of the optical gates.

Surge in the power dissipation due to increased leakage current has become one of the major concern in conventional CMOS VLSI design because of reduced transistor size, lower threshold voltage and lower supply voltage. To alleviate this, we have designed hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on logic-in-memory (LIM) structure for various logic gates such as NAND/AND, NOR/OR and XNOR/XOR. This paper investigates the performance of hybrid gates and the results are compared with the conventional CMOS based gates in-terms of power, delay and device count. Hybrid gates designed in this paper are not only non-volatile in nature due to the use of MTJs but also they are found superior than the conventional CMOS circuits by dissipating less power and occupying smaller die area.

Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and energy efficiency along with throughput. For both varieties, we demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarized neural network implementation, we achieve up to twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable., Comment: arXiv admin note: substantial text overlap with arXiv:1904.00938. Accepted manuscript uploaded 02/03/20. DOA 01/03/20

In this paper, a new topology for dynamic logic-based full adder is proposed and analyzed. The XOR and XNOR gates are generally used as basic logic blocks in the full adder design. In this work, the modified architectures of XOR and XNOR logic gates are used in the implementation of full adder circuit. The suggested topology of XOR/XNOR gates exhibits a full logic swing. The proposed full adder circuit is simulated using the conventional 180 nm CMOS process technology. The simulation results using SPICE simulation tool demonstrate that there are substantial improvements in power dissipation and speed of the proposed circuit compared to the earlier reported designs.

This work presents 16×128 stochastic-binary processing elements for energy/area efficient processing of artificial neural networks. A processing element (PE) with all-digital components consists of an XNOR gate as a bipolar stochastic multiplier and an 8bit binary adder with 8x registers for accumulating partial-sums. The PE array comprises 16x dot-product units, each with 128 PEs cascaded in a single row. The latency and energy of the proposed dot-product unit is minimized by reducing the number of bit-streams required for minimizing the accuracy degradation induced by the approximate stochastic computing. A 128-input dot-product operation requires the bit-stream length (N) of 1-to-16, which is two orders of magnitude smaller than the baseline stochastic computation using MUX-based adders. The simulated dot-product error is 6.9-to-1.5% for N=1-to-16, while the error from the baseline stochastic method is 5.9-to-1.7% with N=128-to-2048. A mean MNIST classification accuracy is 96.11% (which is 1.19% lower than 8b binary) using a three-layer MLP at N=16. The measured energy from a 65nm test-chip is 10.04pJ per dot-product, and the energy efficiency is 25.5TOPS/W at N=16.

In this paper, we present a graphene-based plasmonic electro-optical multi-logic gate (MLG) operating at THz frequency. The designed MLG supports AND, XNOR, and NOR logic gates in a graphene-dielectric-metal structure, simultaneously. The propagation length of the surface plasmons (SPs), stimulated by a 27.35 THz incident TM wave, is about 62 times larger in ON state compared to OFF state. Simulation results by the finite difference time domain (FDTD) method show the minimum extinction ratio (ER) of 29.41, 97.38, and 29.40 dB for AND, XNOR, and NOR logic gates, respectively. Also, the minimum modulation depth (MD) is obtained 99.99% for XNOR and 99.88% for AND and NOR logic gates. The proposed MLG provides a high extinction ratio and ultra-compact logical block for using in digital processing circuits and THz applications.

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices.

True random number generators (TRNGs) are considered as an innovative basis to obtain unpredictable and irreproducible digital bit-streams in secure systems and communications. Because of its ultra-low power and extremely-small size features, the quantum-dot cellular automata (QCA) is most promising nanoelectronic technology for implementing digital systems with security capabilities. This paper presents a novel QCA implementation of TRNG, which is comprised of proposed cross-coupled circuit and cross-oriented structure, in order to generate truly random numbers. This implementation extracts the randomness from the oscillatory trajectory of QCA cross-coupled loop that is composed of XNOR gates only to guarantee the quality of randomness. Furthermore, it exploits the oscillatory metastability resulting from zero-energy QCA cells of cross-oriented structure that is connected across cross-coupled outputs to increase the quality of randomness. Its behavior is verified through QCA simulations and its architecture is passed statistical tests of random numbers. Consequently, the proposed QCA-based TRNG can be considered as a promising candidate for future security applications in Nano communications.

In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.

Spin switch (SS) is a promising spintronic device which exhibits compactness, low power, non-volatility, input–output isolation leveraging giant spin Hall effect, spin transfer torque, and dipolar coupling. In this paper, we propose a novel device-to-architecture co-design for an in-memory computing platform using coterminous SS (IMCS2), which could simultaneously work as non-volatile memory and reconfigurable in-memory logic (AND/NAND, OR/NOR, and XOR/XNOR) without add-on logic circuits to memory chip. The computed logic output could be simply read out like a normal magnetic random access memory bit cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in the conventional von Neumann computing system. The IMCS2-based in-memory bulk bitwise Boolean vector operation shows ${\sim }9\times $ energy saving and ${\sim }3\times $ speedup compared with that of DRAM-based in-memory computing platform. We further employ in-memory multiplication to evaluate the performance of the proposed in-memory computing platform for vector–vector multiplication with different vector sizes.

All optical logic gates can play very important roles in all optical digital systems. In this paper we designed an all optical XNOR gate. The switching part of the designed XNOR consists of two nonlinear resonant cavities. The nonlinear cavities were created by adding two nonlinear defects made of doped glass. Plane wave expansion and finite difference time domain methods were used for simulating the designed structure. The final structure has two input and one output ports. The output port is ON when the input ports have similar states. For the designed structure the delay time is about 2.5 ps.

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates.

In recent years, there is a trend towards the development of reconfigurable circuits where devices using them offer flexibility and performance. Different technologies are explored, such as threshold logic gates (TLGs), which are one of the most promising future technologies, and researchers are examining and improving different characteristics such as density, performance and power dissipation. This research presents a 4-bit arithmetic logic unit (ALU), which was designed using TLGs through reconfigurable logic blocks with a universal circuit configured with three stages based on a floating-gate metal oxide semiconductor transistor with more than one control gate, which was named neu-complementary metal oxide semiconductor (ν-CMOS). The main contribution is that this device is configured as a ν-CMOS inverter and has the ability to program the threshold voltage of its transfer curve by applying an external voltage to the additional control gates. The number of input bits and the magnitude of the weighted input capacitances related to control gates of the ν-CMOS inverters is obtained and analyzed by using the graphical method (floating-gate potential diagram). Finally, the proposed 4-bit ALU shows similar results as those measured from the ALUs implemented in the field programmable gate array evaluation kit and the Motorola chip MC14581B.

In this paper, a low-power high-speed hybrid full adder cell is proposed, which is implemented based on two-input multi-threshold $$({V}_{\mathrm{t}})$$ XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power–delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations.

In this letter, all-optical logic gates with attraction and repulsive interactions of coherent spatial optical solitons have been designed in a bulky nonlinear Kerr medium. The logic gates comprise logical AND and OR gates by the attraction of two obliquely propagating inphase spatial optical solitons and logical NOR and XNOR gates based on repulsive interaction among three out of phase spatial optical solitons. The numerical results show that soliton interactions perform a high contrast power level between ON/OFF states. The proposed model is applicable to design phase-modulated logical gates too. The simplicity and ease for fabrication of the proposed logic gates would be a potential key component for the future of all-optical logical photonic devices and computational photonic circuits.

We have presented all-optical XOR, XNOR, and NOT gates using metal-insulator-metal (MIM)-coupled ring resonator. The performance of the device is evaluated by finite difference in time-domain (FDTD) method. The proposed gate utilizes a unique phenomenon of Fano resonance to excite logic OFF/ON state. Fano resonance has quite asymmetric resonance profile and the transmission spectrum of Fano profile abruptly drops to a minimum value at the resonance condition. Due to this unique resonance phenomenon, a large value of contrast ratio is obtained. The proposed XNOR gate offers a contrast ratio (C.R.) of 20.66 dB while XOR and NOT gates offer C.R. 12.8 and 18.8 dB respectively. The variation of contrast ratio is also studied against different input wavelength and it is reported that the obtained value of contrast ratio is an optimum value for the proposed structure. The device is compact sized with small dimension 0.31 λ02, where λ0 = 1.55 μm. The proposed device opens up the avenues for designing on-chip optical gates in the field of high-speed optical communication networks.

Since last few decades optics has already proved its strong potentiality for conducting parallel logic, arithmetic and algebraic operations due to its super-fast speed in communication and computation. So many different logical and sequential operations using all optical frequency encoding technique have been proposed by several authors. Here, we have keened out all optical dibit representation technique, which has the advantages of high speed operation as well as reducing the bit error problem. Exploiting this phenomenon, we have proposed all optical frequency encoded dibit based XOR and XNOR logic gates using the optical switches like add/drop multiplexer (ADM) and reflected semiconductor optical amplifier (RSOA). Also the operations of these gates have been verified through proper simulation using MATLAB (R2008a).

This paper addresses the issue of deceptive jamming against synthetic aperture radar (SAR) by using 1-bit sampling and time-varying threshold (TVT). With 1-bit intercepted SAR signal, the multipliers involved in a convolution is replaced by xnor gates, which considerably simplify the jamming signal generation. Moreover, the TVT is used for 1-bit quantization before retransmission to retain the relative amplitude information of the jamming signal. As a result, the proposed deceptive jamming schemes are superior to their conventional counterpart in terms of realization. Effects of harmonics and oversampling are analyzed to evaluate the performance degradations caused by the 1-bit sampling and TVT. Simulation results are provided to confirm the validity of the proposed schemes.

In this article, we propose the realization of XNOR logic function by using all-optical XOR and NOT logic gates. Initially, both XOR and NOT gates are designed, simulated and optimized for high contrast outputs. T-shaped waveguides are created on the photonic crystal platform to realize these logic gates. An extra input is used to perform the inversion operation in the NOT gate. Inputs in both the gates are applied with out of phase so as to have a destructive interference between them and produce negligible intensity for logic ‘0'. The XOR and NOT gates are simulated using Finite Difference Time Domain method which results with a high contrast ratio of 55.23 dB and 54.83 dB, respectively at a response time of 0.136 ps and 0.1256 ps. Later, both the gates are cascaded by superimposing the output branch of the waveguide of XOR gate with the input branch of the waveguide of NOT gate so that it can be resulted with compact size for XNOR logic function. The resultant structure of XNOR logic came out with the contrast ratio of 12.27 dB at a response time of 0.1588 ps. Finally, it can be concluded that the proposed structures with fair output performance can suitably be applied in the design of photonic integrated circuits for high speed computing and telecommunication systems.

The COVID-19 pandemic is spreading around the world causing more than 177 million cases and over 3.8 million deaths according to the European Centre for Disease Prevention and Control. The virus has devastating effects on economies, health, and well-being of worldwide population. Due to the high increase in daily cases, the available number of COVID-19 test kits in under-developed countries is scarce. Hence, it is vital to implement an effective screening method of patients using chest radiography since the equipment already exists. With the presence of automatic detection systems, any abnormalities in chest radiography that characterizes COVID-19 can be identified. Several artificial-intelligence algorithms have been proposed to detect the virus. However, neural networks training is considered to be time-consuming. Since computations in training neural networks are spent on floating-point multiplications, high computational power is required. Multipliers consume the most space and power among all arithmetic operators in deep neural networks. This paper proposes a 15 Gbps high-speed bipolar-complementary-metal-oxide-semiconductor (BiCMOS) exclusive-nor (XNOR) gate to replace multipliers in binarized neural networks. The proposed gate can be implemented on BiCMOS-based field-programmable gate arrays (FPGAs). This will significantly improve the response time in identifying chest abnormalities in CT scans and X-rays.

We designed and evaluated a high-performing and biocompatible sensing platform to quantitatively detect glutathione (GSH) in the intracellular environment. To this end, we constructed a fluorescent switch using nitrogen-doped graphene quantum dots (N-GQDs) as fluorescent probes and MoS2 nanoflowers as the GSH recognition unit. Fluorescence emission of N-GQDs was first switched OFF when combined with MoS2 nanoflowers due to the fluorescence resonance energy transfer (FRET) mechanism. It was readily switched ON by reducing MoS2 to Mo3+ in the presence of GSH, enabling the recovery of fluorescent signal. We performed experiments to test the dependence of the sensing platform fluorescence intensity on the concentrations of GSH in the range of 0.4–4.4 mM. The detection limit was 2.47 μM. The monitoring of concentrations of GSH in human retinal pigment epithelium cells (ARPE-19) samples revealed excellent sensing performance with facilitated visualization of the probe, suggesting that the unique sensing strategy has the exceptional anti-interference property for assessing the intracellular GSH quantity in diagnostics and biomedical research. The OFF/ON switch for the detection of GSH was explored to create a XNOR molecular logic gate.

High-speed all-optical logic gates are the demand of an exponentially growing high-performance all-optical network. Here, we propose the six all-optical logic gates by exploiting cross-gain modulation (XGM) in semiconductor optical amplifier (SOA). The high chirping and low extinction ratio cause the low bitrate in XGM based optical logic gates. However, the XGM interaction experienced by a low power probe signal increases significantly in the presence of a high-power pump signal and a high injection current of SOA. The XGM interaction also increases for high gain and low saturation power SOA. By considering these parameters, we realize a high extinction ratio and high-quality factor all-optical logic gates at the bitrate of 340 Gb/s, increasing the possibility of establishing a high-performance all-optical network.

We have developed and analysed logic NOR, NAND and XNOR gates based on two dimensional (2D) photonic crystals at a wavelength of 1.55 μm. The interference and self-collimation effects are used to design logic gates, which control the output by adjusting the phase difference to achieve constructive or destructive interference. The splitter is a line defect of the photonic crystal with a row of periodically arranged air rods. The radius of the defect rods depends on the function of the logic element. The use of these logic gates can reduce the size of logic devices.

Linear-optical logic gates have the potential to be the bases of the next-generation information technology (IT) because of the low power consumption and rapid response. This study proposes a general theoretical model to obtain the optimal solutions for linear-optical logic gates. All common logic gates (AND, OR, NOT, NAND, NOR, XOR, and XNOR) are experimentally demonstrated with one single sample structure based on ultracompact plasmonic waveguides. The measured intensity contrast ratio between the output-logic “1” and “0” states reaches 28 dB for the OR gate and 9.4 dB for the AND gate, thereby approaching the theoretical maximum of infinity and 9.5 dB, respectively. The proposed logic gates provide uniform output intensities for identical output logics when the input logics are different. The measured intensity discrepancies are below 1% for the three output-logic “1” states of the OR gate and the three output-logic “0” states of the AND gate. This phenomenon is favored in practical applications and th...

Fabricating plasmonic nanowire waveguides and circuits by lithographic fabrication methods is highly desired for nanophotonic circuitry applications. Here we report an approach for fabricating metal nanowire networks by using electron beam lithography and metal film deposition techniques. The gold nanowire structures are fabricated on quartz substrates without using any adhesion layer but coated with a thin layer of Al2O3 film for immobilization. The thermal annealing during the Al2O3 deposition process decreases the surface plasmon loss. In a Y-shaped gold nanowire network, the surface plasmons can be routed to different branches by controlling the polarization of the excitation light, and the routing behavior is dependent on the length of the main nanowire. Simulated electric field distributions show that the zigzag distribution of the electric field in the nanowire network determines the surface plasmon routing. By using two laser beams to excite surface plasmons in a Y-shaped nanowire network, the output intensity can be modulated by the interference of surface plasmons, which can be used to design Boolean logic gates. We experimentally demonstrate that AND, OR, XOR and NOT gates can be realized in three-terminal nanowire networks, and NAND, NOR and XNOR gates can be realized in four-terminal nanowire networks. This work takes a step toward the fabrication of on-chip integrated plasmonic circuits.

A type of all-optical logic gates based on a graphene nanoribbon rectangular ring resonator for terahertz frequency is proposed and numerically investigated by finite-difference time-domain simulations. By utilizing the surface plasmon polaritons propagated along the graphene nanoribbon, the tunability in frequency of the filter effect can be achieved by tuning the bias voltage of graphene. The proposed structure can realize NOT, XOR, and XNOR gates, corresponding to the high contrast ratio of about 14.2, 19.5, and 14.1 dB, respectively. The proposed logic gates would be a potential component for designing all-optical logical photonic devices in an optical communication system.

Optical logic gates are important elements in optical computing and optical circuits. However, the footprints of the present optical logic gates are still on the micrometer scale. Further miniaturization of the logic gates to nanometer scale remains challenging. Here we propose, and demonstrate experimentally, subwavelength all-optical logic gates based on single-element optical slot nanoantennas. By employing a spin-encoded scheme, we achieve OR, AND, NOT, NAND and NOR logic gates via an L-shaped optical slot nanoantenna with a footprint of 300 nm by 300 nm, and a XNOR logic gate via a rectangle optical slot nanoantenna with a footprint of 220 nm by 60 nm. The SPP launching and logic operation via mode coupling instead of path interference are integrated together at a single-element nanoantenna, which considerably shrinks the dimensions of the device. The experimental results show the potential of the single optical slot nanoantenna in subwavelength all-optical logic computing and nanophotonic information processing.

With the development and application of Internet of things, new requirements for optical communication technology are put forward, and this text proposed new optical information processing device design logic-oriented-based for Internet of brain things application. Three micro rings were coupled with three different shapes of optical waveguide components, their wavelengths were varied with the change of the applied voltages (logical input) so as to control the propagation direction of the input optical signal and the final output forms of lighting or darkness representing different logic level values as the result of the logical operations. The working wavelength of the device was determined as $1.5146~\mu \text{m}$ through static simulations with MATLAB tools, and it was proved that the functions of flexible optical switch logic operations “and/not”, “or/nor”, and “xor/xnor” can be realized in the dynamic simulations, the results indicated that the device with low-power consumption, high-bandwidth, flexible structure, and multiple logical operation functions has been accomplished and can be used as components of VLSI designs in future. This paper also gives a useful reference to many Internet of brain things applied field.

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

Summary Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious. As a new type of computer architecture, computing-in-memory is an alternative approach to alleviate the von Neumann bottleneck. Here, we have demonstrated two kinds of computing-in-memory designs based on two-surface-channel MoS2 transistors: symmetrical 4T2R Static Random-Access Memory (SRAM) cell and skewed 3T3R SRAM cell, where the symmetrical SRAM cell can realize in-memory XNOR/XOR computations and the skewed SRAM cell can achieve in-memory NAND/NOR computations. Furthermore, since both the memory and computing units are based on two-surface-channel transistors with high area efficiency, the two proposed computing-in-memory SRAM cells consume fewer transistors, suggesting a potential application in highly area-efficient and multifunctional computing chips.

Optical logical operations demonstrate the key role of optical digital computing, which can perform general-purpose calculations and possess fast processing speed, low crosstalk, and high throughput. The logic states usually refer to linear momentums that are distinguished by intensity distributions, which blur the discrimination boundary and limit its sustainable applications. Here, we introduce orbital angular momentum (OAM) mode logical operations performed by optical diffractive neural networks (ODNNs). Using the OAM mode as a logic state not only can improve the parallel processing ability but also enhance the logic distinction and robustness of logical gates owing to the mode infinity and orthogonality. ODNN combining scalar diffraction theory and deep learning technology is designed to independently manipulate the mode and spatial position of multiple OAM modes, which allows for complex multilight modulation functions to respond to logic inputs. We show that few-layer ODNNs successfully implement the logical operations of AND, OR, NOT, NAND, and NOR in simulations. The logic units of XNOR and XOR are obtained by cascading the basic logical gates of AND, OR, and NOT, which can further constitute logical half-adder gates. Our demonstrations may provide a new avenue for optical logical operations and are expected to promote the practical application of optical digital computing.

We experimentally investigated a novel broadband optoelectronic chaos generation scheme. The proposed system is achieved by adopting the highly nonlinear operation of an electro-optical exclusive-NOR (XNOR) logic gate and two delayed feedback loops that refer to the Boolean chaos model. The XNOR gate is established by a commercial use inphase and quadrature-phase (IQ) modulator that works at a specific bias point. The resulting power spectrum of the broadband chaos signal extends from DC to 29.1 GHz (10 dB bandwidth), and the probability density distribution is Gaussian distribution like. Owing to the strong nonlinearity of XNOR operation, the conditions to enter the chaos region are more relaxed compared to traditional optoelectronic oscillator (OEO) chaos systems, and the time delay signature (TDS) of the feedback loop is also suppressed. Moreover, to further enhance the performance of the generated chaos signal, we injected the optoelectronic chaotic signal into a semiconductor laser. Experimental results indicate that after the cascade optical injection, the bandwidth of the output chaos signal is extended to 38.4 GHz and the TDS is completely concealed; meanwhile, a perfect Gaussian distribution can be obtained.