315 results on '"Rooyackers, R."'
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152. GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices.
153. A systematic study of trade-offs in engineering a locally strained pMOSFET.
154. 90nm RF CMOS technology for low-power 900MHz applications [amplifier example].
155. Triple junctions for reduced impact of offset spacer variation on CMOS device parameters.
156. Perspective of FinFETs for analog applications.
157. Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node.
158. Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield.
159. Thin L-shaped spacers for CMOS devices.
160. Investigation by Convergent Beam Electron Diffraction of the Stress around Shallow Trench Isolation Structures
161. Diode Analysis of High-Energy Boron Implantation-Induced P-Well Defects
162. SSRM and SCM Observation of Enhanced Lateral As- and BF2-diffusion Induced by Nitride Spacers.
163. Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity
164. A New Dummy-Free Shallow Trench Isolation Concept for Mixed-Signal Applications
165. SSRM and SCM Observation of Enhanced Lateral As- and BF2-diffusion Induced by Nitride Spacers
166. Transconductance hump in vertical gate-all-around tunnel-FETs.
167. Stress variation across arrays of lines and its influence on LOCOS oxidation
168. (Invited) Monolithic Integration of III-V Semiconductors by Selective Area Growth on Si(001) Substrate: Epitaxy Challenges & Applications
169. A High Performance 0.18 um Elevated Source/Drain Technology with Improved Manufacturability.
170. Investigation of Stress in STI using UV-Raman Spectroscopy.
171. Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy.
172. An Optimized Poly-Buffered LOCOS Process for a 0.35 μm CMOS Technology.
173. Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins.
174. A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devices With 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node.
175. Optimization of polysilicon encapsulated logos for 0.25 micron CMOS: Correlation between cavity dimensions, mechanical stress, and gate oxide integrity
176. Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node
177. Design methodology of FinFET devices that meet IC-Level HBM ESD targets
178. NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics
179. 90nm RF CMOS technology for low-power 900MHz applications
180. Electrical and thermal scaling trends for SOI Fin FET ESD design
181. 90nm RF CMOS technology for low-power 900MHz applications [amplifier example]
182. Minimization of the muGFET contact resistance by integration of nisi contacts on epitaxially raised source/drain regions
183. Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits
184. Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield
185. Silicide and Shallow Trench Isolation line width dependent stress induced junction leakage
186. 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions.
187. CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
188. Triple junctions for reduced impact of offset spacer variation on CMOS device parameters
189. Specific features of the capacitance and mobility behaviors in finfet structures
190. Thin L-shaped spacers for CMOS devices
191. Suitability of FinFET technology for low-power mixed-signal applications
192. Perspective of FinFETs for analog applications
193. Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions
194. Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL
195. MUGFET - alternative transistor architecture for 32 nm CMOS generation
196. A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
197. Novel architecture to boost the vertical tunneling in Tunnel Field Effect Transistors.
198. Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions.
199. Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL.
200. CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach.
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