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A technology that has been in use for years, surface mount devices (SMD), is increasing board density, increasing functional capability, and lowering assembly costs. The transition to SMD requires careful planning because each step in the design process differs from established methods. SMDs are available in small outline, ceramic leadless chip carriers, and plastic leadless carriers. The problem of thermal coefficient expansion is being researched. SMDs can be purchased in bulk, on tape, in cartridges, or on rails. The pick and place equipment in use today are bench type systems, mass placement systems, and X-Y tables. Testing boards is more complicated, and testing approaches will have to change. Photograghs of SMD assembly systems, capacitors, LEDs, chips, trimmers, chip carrier sockets, connectors, and assemblies, and a table of SMD manufacturers are included.

New switch-mode power supplies have increased power density and improved performance. They are sold at lower prices and adhere to current standards. The designs have as much as three watts per cubic inch and ninety percent efficiency. Advances have been made in control integrated circuits with higher frequencies and lower costs. Current-mode technology controls phase shift, has increased reliability, and a more stable loop. Discrete components used by manufacturers include control integrated circuits, MOS field effect transistors (MOSFET), and surface mount devices (SMD). Photographs of a SMD module, power supplies, power supply circuit boards, and a modular motherboard and a table of switch-mode power supplies are included.

The inefficiency of conventional MOSFET devices using large dice made them too expensive to compete with bipolar transistors. The DMOS structures were the first power MOSFETs. VMOS transistors with vertical current conduction allowed current to flow from the back of the die to the source metallization on the top surface. Breakthroughs in DMOS technology in the early 1980s found manufacturers coining trademarks to reflect their special cell geometry and processing techniques. More recently, second and third generation devices are combining increased packaging density and short channel processes resulting in devices with significantly lower on-resistances per unit of silicon area.

Improved characteristics in power MOSFETs include reduced on-resistance and lower overall capacitance. Improvements have been most evident in low-voltage devices. Conductivity of a given chip size may be increased fourfold, drastically reducing heat-sinking requirements. Designers may select replacements on the basis of on-resistance or current ratings enabling use of a device with a smaller die. Die-size information is shown in a table, and a chart show the on-resistance values for first, second, and third generation TMOS transistors. A graph show the rise in case temperature during typical application to the efficiency of the latest chip designs. Another diagram illustrates a control circuit tailored for a blower motor employing a p-channel MOSFET for the power switch. The MOSFET's expansion into the power transistor market is likely to increase as designers come to realize the efficiency and economy of low-voltage MOSFETs.

The encapsulated dc-dc power converters of today offer a wide range of power ratings (from less than 1W to 50W) and a wide price range (from less than $15 to more than $150). Money can be saved in choosing a product if power needs are not overspecified. New component and manufacturing technologies enable converter manufacturers to put more power into smaller packages. Hidden costs incurred in choosing a more powerful unit than needed include decreased power efficiencies and loss of space on a pc board or in a chassis. A table lists a sample of the wide range of converters in small packages that are available. Advances in the smaller, more powerful converters include thick-film hybrid technology, custom, integrated circuits (ICs) and miniaturized magnetic components. Smaller converter size is obtained through the use of lower power levels and unregulated converters. Avoidance of load-regulation circuitry results in more power output as well as smaller package size. Some researchers say that unregulated converters are also more reliable in having a lower component count. Some applications require a regulated output; battery-fed units are an example. A number of converters combine regulation with a wide range of input voltages. Photographs of converters are included.

The high-density prototyping system consists of Unilayer II boards, wire-wrapping boards, multilayer boards, card cages, and custom engineering services. Six standard board geometries are available. As many as five 2-piece, 108-pin connectors may be used by each board. The largest board holds 465 ICs integrated circuits; the largest card cage holds 26 boards. Design engineers can submit wiring data and receive fully wired wire-wrapped or Unilayer II boards in three weeks. CAD engineering services can transfer the design to multilayer boards for volume production after the prototype has been tested and debugged. Prices range from $91 to $330. A photograph of the packaging system is included.

A densely packaged power supply produces high operating temperatures, stress, and decreased reliability and maintainability. The Navy Power Supply Reliability: Design and Manufacturing Guideline (NAVMAT) recommends a power density of one to three watts per cubic inch. A graph of the NAVMAT curves of power density is included.

A trend in printed circuit boards indicates that fifty percent of all boards will use surface mount devices (SMD) by 1990. The technology can reduce board sizes by as much as seventy percent and costs by fifty percent. It has increased density compared to through-hole components with more functional capability in the same package or comparable capability is smaller packages. A chart of world SMD consumption is included.

A new CAD-CAM workstation for engineering design is low in cost mainly because of highly dense packaging. The CDX-9000 from Cadnetix Corp., Boulder, Colorado, packs two PC-board electronics together with a Winchester and 5.25-inch floppy disks, thirty-five Mbytes memory, a 68010 microprocessor, and a seventeen-inch bit-map CRT in a desktop cabinet. In basic configuration, the icon-and-mouse-driven system costs $36,500 in lots of four to nine. Other models are available at varying prices depending on configuration. A photograph of the system is shown.

The ion implantation, oxide isolation with scaling (IMOX-S) bipolar IC processing technique has been utilized to significantly improve the processing speeds and chip densities of VLSI circuits without the expected concommitant increase in power consumption. Power requirements were reduced by optimizing the interrelationships between successive steps of the IMOX-S processing techniques. Greater processing speeds and higher chip densities have been achieved by IMOX via use of oxide isolation and walled-emitter structures, and elimination of capacitances that tend to reduce switching speeds. Details of the IMOX-S process are illustrated with diagrams and photographs.

In the world of nonvolatile memories, capacities are doubling annually, costs and access times continue to fall, and the use of CMOS technology is increasing. The nonvolatile memory is unique because it retains contents even during power shutdown, a feature that offers distinct advantages over other types of memory. Tighter design rules, circuit innovations, and improved lithography are teaming together to reduce delays inside the chips. The industry is anxiously awaiting the 512k EPROM, with the thought that a 1-mbit EPROM is not far away. A graph is included that portrays bit density vs. year.

Dennis Derfiny, a section manager for Motorola Inc. Systems Division, warns that as speed increases to the point required for high-frequency communications, passive components become electrically active. Surface-mounted components will not only improve density and reliability, they will reduce propagation delays and spurious noise emissions at or past gigahertz frequencies. This is understood by most microwave engineers, but is still newsworthy for telecommunications people.

The PAL 32R16, developed by Monolithic Memories, is the equivalent of 1600 gates and operates at eighteen MHz. Based on the novel product-term sharing technique, the active state of PAL 32R16 may be programmed low or high. The TTL-compatible 32R16 is listed at $50 each in lots of 100. A photograph is shown.

VLSI (Very Large Scale Integration) technology has brought about lower costs, higher speed, and more efficiency to computers. A single VLSI chip can have as many as 100,000 embedded transistors, making it possible to have personal computers with huge amounts of memory and powerful 32-bit processors. A new VLSI device takes about a year to develop, and computers are now part of that development process. VLSI circuits have become so compact that traditional DIP packaging is inadequate. Photographs of various chips are included.

Raytheon Co. will introduce a family of high-speed programmable read-only-memory chips that use amorphous-silicon switches for improved density. The PROMs will use an antifuse approach in which an amorphous-silicon switch acts as an insulator until a programming voltage is applied. Stacking the amorphous-silicon switches above the Schottky diodes allows for density improvements.

Magnetic-bubble memory chips holding 1-Mbits could pose serious competition to batter-backed CMOS static RAMs when used in portable microcomputer applications. The device can be switched off when not in use, a technique that can give the bubble chip an overall power consumption less than that of the RAM. This fact, when coupled with the device's ruggedness and density per square inch, makes the bubble-memory an attractive alternative to CMOS static RAMs.

By packing 8K bytes of ROM onto a single chip, the first step in putting an operating system on a chip has been taken. The S83 from American Microsystems Inc. is just such a device, and was built using 3 micrometer technology and a clever adaptation of CP-M. The Z80-based device also features decoding logic as well as control logic for data buses and external RAM. All of this fits onto a chip less than 40,000 mils square and smaller than current microprocessors having 4-kbytes of ROM. The device can also serve as an auxiliary controller, connected as a slave to a host.

Impact (Implanted Advanced Composed Technology) is a new bipolar process in which all critical components of a very large- scale integrated circuit are placed at the same time with a single mask. Impact combines faster speed than C-MOS with the density of MOS. Fully composed masking allows components to be placed closer together which, along with its fully walled structure, reduces capacitance and boosts density. Impact is suitable for harsh environments. It will likely be targeted for high-speed display processors, superminicomputers and array processors as well as other high speed, high performance applications. Diagrams of the Impact process, graphs of relative performance and a sample applications circuit diagram are included.

Several milestone achievements were unveiled at a recent International Solid-State Circuits Conference. Most notable is a 32K-by-8-Bit static RAM that packs well over 1 million active devices onto an area slightly over 6 by 8 mm. The device from Toshiba Ltd uses 1.2 micromillimeter technology. Also attracting attention at the conference were 256K-bit dynamic RAMs which have been fine tuned to obtain extremely fast access times at low power levels. Fujitsu has developed the smallest GaAs RAM yet reported - only 47 by 32 micromillimeters. More than 26,000 FETs are contained on the device, the highest density level yet attained.

A new CMOS process, the self-aligned contact CMOS, or Sacmos, process produces chips with 1.5 to three times the miniaturization attained by the ordinary CMOS process, when both are using the same rules. The chip density achieved by Sacmos when using four-micrometer design rules is the same as that attained by ordinary CMOS utilizing 2.5-micrometer rules. A diagrammatic illustration of the Sacmos process which also permits easier layout, is given. The easy to implement Sacmos is compatible with existing MOS processes. Other theoretical details about Sacmos are given.

Intel Corp.'s new 27256 EPROM chip exemplifies the new class of 256K EPROMs that have resulted from the steady increase in EPROM densities in recent years. It represents the solution of key technical proglems which will soon lead to development of megabit and larger arrays. It offers great promise to microsystem designers, as two or three 256K chips can store a PASCAL compiler along with a sophisticated word-processing program. The 27256 was created from the 2764, a 64K EPROM, through a two-step scaling-down process. The first step involved the introduction of wafer-stepping lithography for levels such as the first polysilicon and contact openings, which produced a 128K chip. In the next step all the design rules were scaled down, and the stepper lithography was used to full advantage. The redesign that produced the 256K array suggests that, from a device design perspective, 512K and one megabit arrays will be feasible in two to three years, although this will require significantly improved control over dimensions. Circuit diagrams of the 27256's read circuitry and decoder are included, along with a diagram showing the scaling method used in the chip and a table of the chip's scaling data.

General Dynamics Corp. has developed two new methods of constructing high-density, hermetically sealed integrated circuit packages that are suited for avionic, missile, and aerospace applications. Versipak and Isopak both offer reduced size and weight, increased system reliability, and lower costs. Both packaging methods are based on matrix, or batch, processing, which involves the stepping and repeating of a package pattern across a panel of Kovar, a metal alloy with the same temperature coefficient as glass. This process produces packages that can be processed, assembled, tested, and burned in as a unit. In Versipak packages the lead posts and package outlines are all in precisely controlled positions, making it an ideal matrix for automation. Isopak incorporates all the features of Versipak, as well as a self-contained glass insulating layer that provides for complex device interconnections or the construction of a complete thin-film hybrid. A photograph of an Isopak package is included, along with diagrams illustrating both packaging techniques.