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Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS$_2$ films at 560 C in 50 min, within the 450-to-600 C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ~140 $\mathrm{{\mu}A/{\mu}m}$ at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS$_2$ grown below 600 C using solid-source precursors. The effective mobility from transfer length method test structures is $\mathrm{29 \pm 5\ cm^2V^{-1}s^{-1}}$ at $\mathrm{6.1 \times 10^{12}\ cm^{-2}}$ electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.

A key technology future direction is CMOS + X, where X can be memory, photonics, spintronics, power electronics, nanomechanics, sensors and actuators, RF/mm-wave, and even quantum computing. Nanosystems of 3D integrated “X” technology (N3XT) is a key concept at the chip level. We must also go beyond a single chip from a wafer and focus on integrating chips into systems using MOSAIC (MOnolithic Stacked Assembled IC). I will give an overview of the new materials and device technologies that may need to be developed to realize this vision. In particular, low-dimensional materials are suitable for logic transistors in this 3D MOSAIC of N3XT chips vision because of the low temperature for device fabrication as well as the thin device layers.

Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS 2 , is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor deposited monolayer MoS 2 using transmission line model (TLM) structures, before and after dielectric encapsulation. We report contact resistance values as low as 330 ohm-um, which is the lowest value reported to date. We further study the effect of Al 2 O 3 encapsulation on variability in contact resistance and other device metrics. Finally, we note some deviations in the TLM model for short-channel devices in the back-gated configuration and discuss possible modifications to improve the model accuracy.

High-density memory arrays require selector devices, which enable selection of a specific memory cell within a memory array by suppressing leakage current through unselected cells. Such selector devices must have highly nonlinear current-voltage characteristics and excellent endurance; thus selectors based on a tunneling mechanism present advantages over those based on the physical motion of atoms or ions. Here, we use two-dimensional (2D) materials to build an ultrathin (three-monolayer-thick) tunneling-based memory selector. Using a sandwich of h-BN, MoS2, and h-BN monolayers leads to an "H-shaped" energy barrier in the middle of the heterojunction, which nonlinearly modulates the tunneling current when the external voltage is varied. We experimentally demonstrate that tuning the MoS2 Fermi level can improve the device nonlinearity from 10 to 25. These results provide a fundamental understanding of the tunneling process through atomically thin 2D heterojunctions and lay the foundation for developing high endurance selectors with 2D heterojunctions, potentially enabling high-density non-volatile memory systems.

Vanadium dioxide (VO2) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ~1 nm wide carbon nanotube (CNT) heaters to trigger the IMT in VO2. Single metallic CNTs switch the adjacent VO2 at less than half the voltage and power required by control devices without a CNT, with switching power as low as ~85 ${\mu}W$ at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin Probe Microscopy (KPM) and Scanning Thermal Microscopy (SThM). Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO2 by the CNT play a key role in the IMT. These results demonstrate the ability to trigger IMT in VO2 using nanoscale heaters, and highlight the significance of thermal engineering to improve device behaviour.

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

A physics-based compact model for retention behaviors of conductive-bridge random access memory (CBRAM) is developed by modeling: 1) the material-dependent metal atom transport from the conductive filament into the electrolyte; and 2) the conduction percolation controlled by the atom concentration. Considering the material properties of the metal and electrolyte, this compact model can well reproduce the retention behaviors of the CBRAM in both low resistance state and high resistance state (HRS) for various material stacks under various operating temperatures. Two types of HRS resistance shift can be reproduced by accurately modeling the percolation paths. The compact model can enable the reliability projection of cells in a crossbar array.

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

We investigate the valley Hall effect (VHE) in monolayer WSe2 field-effect transistors using optical Kerr rotation measurements at 20 K. While studies of the VHE have so far focused on n-doped MoS2, we observe the VHE in WSe2 in both the n- and p-doping regimes. Hole doping enables access to the large spin-splitting of the valence band of this material. The Kerr rotation measurements probe the spatial distribution of the valley carrier imbalance induced by the VHE. Under current flow, we observe distinct spin-valley polarization along the edges of the transistor channel. From analysis of the magnitude of the Kerr rotation, we infer a spin-valley density of 44 spins/μm, integrated over the edge region in the p-doped regime. Assuming a spin diffusion length less than 0.1 μm, this corresponds to a spin-valley polarization of the holes exceeding 1%.

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programing iterations on average.

© 2018 IEEE. Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide

Hardware for deep neural network (DNN) inference often suffers from insufficient on-chip memory, thus requiring accesses to separate memory-only chips. Such off-chip memory accesses incur considerable costs in terms of energy and execution time. Fitting entire DNNs in on-chip memory is challenging due, in particular, to the physical size of the technology. Here, we report a DNN inference system—termed Illusion—that consists of networked computing chips, each of which contains a certain minimal amount of local on-chip memory and mechanisms for quick wakeup and shutdown. An eight-chip Illusion system hardware achieves energy and execution times within 3.5% and 2.5%, respectively, of an ideal single chip with no off-chip memory. Illusion is flexible and configurable, achieving near-ideal energy and execution times for a wide variety of DNN types and sizes. Our approach is tailored for on-chip non-volatile memory with resilience to permanent write failures, but is applicable to several memory technologies. Detailed simulations also show that our hardware results could be scaled to 64-chip Illusion systems. A networked system of eight computing chips, each with its own on-chip memory, can be used to efficiently implement a range of neural network models and sizes.

To realize superior electrostatic control, a gate oxide bilayer for carbon nanotubes (CNT) is employed consisting of a 0.35 nm interfacial dielectric (k=7.8) and 2.5 nm high-k ALD dielectric (k=24). Using experimentally measured dielectric constants on sp2 carbon and minimum oxide thickness on CNT, a COX on CNT of 2.94×10-10 F/m is calculated for top-gate geometry. Gate leakage sub-1 pA/CNT is measured at 0.7V, better than the sub-5 nm node technology target. Top-gated carbon nanotube field effect transistors in this paper have 65 mV/dec subthreshold slope and DIBL as low as 20 mV/V at 15 nm gate length. Negligible hysteresis and no degradation in drive current from the top-gate process is observed. TCAD modeling predicts this approach will enable 68 mV/dec for top-gate CNFET with 10 nm L G , 1 nm CNT diameter and 250 CNT/μm, revealing a path to energy and performance gains from a CNT transistor technology.

One-dimensional contact (so-called edge contact) to monolayer 2D materials has been proposed for ultimate transistor scaling but reported on-state currents are much lower than those from top contact devices. Experiments in this work reveal that the fabrication processes for metal MoS2 contact strongly affect the electrical characteristics such as Schottky barrier height. Using in-situ 2D etching and metal deposition, we obtained Fermi-level pinning-free Ni-MoS2 edge contact transistor devices. Moreover, it reaches the highest on-state current among those TMDs edge contact devices reported in literatures and comparable to top-contact ones. First-principles calculation reveals the evolution of local electronic structure from strong metallization at the edge contact "interline" (1D equivalent of "interface") to semiconductor in the channel region. The short length (

The proposed X-ray spatial light modulator (SLM) concept is based on the difference of X-ray scattering from amorphous and crystalline regions of phase change materials (PCMs) such as Ge2Sb2Te5 (GST). In our X-ray SLM design, the “on” and “off” states correspond to a patterned and homogeneous state of a GST thin film, respectively. The patterned state is obtained by exposing the homogeneous film to laser pulses. In this paper, we present patterning results in GST thin films characterized by microwave impedance microscopy and X-ray small-angle scattering at the Stanford Synchrotron Radiation Lightsource.

Double-gated monolayer two-dimensional (2D) material transistor is expected to offer ideal (~60 mV/dec) subthreshold swing (SS) for gate lengths well below 10 nm. However, the ideal 2D transistor assumes Ohmic contacts whereas a realistic metal/2D Schottky contact can degrade SS. Transport simulations including scattering is necessary to correctly describe carrier thermalization and predict the SS degradation. Scaled 2D transistors with a Schottky barrier height (SBH) smaller than 100 meV and doping concentration in the extension region larger than 2x1013 cm-2 are required to achieve high performance.

The success of semiconductor electronics is built on the creation of compact, low-power switching elements that offer routing, logic, and memory functions. The availability of nanoscale optical switches could have a similarly transformative impact on the development of dynamic and programmable metasurfaces, optical neural networks, and quantum information processing. Phase change materials are uniquely suited to enable their creation as they offer high-speed electrical switching between amorphous and crystalline states with notably different optical properties. Their high refractive index has also been harnessed to fashion them into compact optical antennas. Here, we take the next important step by realizing electrically-switchable phase change antennas and metasurfaces that offer strong, reversible, non-volatile, multi-phase switching and spectral tuning of light scattering in the visible and near-infrared spectral ranges. Their successful implementation relies on a careful joint thermal and optical optimization of the antenna elements that comprise an Ag strip that simultaneously serves as a plasmonic resonator and a miniature heating stage., 14 pages, 4 figures

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

We demonstrate the highest nFET current of 390 μA/μ $m$ at VDS = 1 V based on CVD Mos2 mono layers without intentional doping. The transistor exhibits good subthreshold swing of 109 m V/ decade, large $\mathrm{I}_{\mathrm{ON}}/\mathrm{I}_{\mathrm{OFF}}$ ratio of 4 × 10 8 , and nearly zero DIBL. The high on-current achieved in monolayer Mos2 nFET is mainly attributed to the thin EOT ~ 2 nm of HfO x gate oxide, short gate length of 100 nm, and low contact resistance ~ 1.1 kω- μm.

The energy efficiency of RRAM-based in-memory matrix-vector multiplication (MVM) depends largely on the output sensing mechanism. We design a novel voltage-mode sensing configuration with differential-row weight mapping that achieves a 3.6x improvement in energy per multiply-accumulate (MAC) at the same read voltage compared to current-mode sensing, and avoids the nonlinear source-line dynamics issue that occurs in conventional voltage-mode sensing. We verify the MVM performance of our scheme by performing measurements using a RRAM array monolithically integrated with CMOS voltage-mode neurons. We compare the effects of weight normalization on MVM accuracy under two different weight mapping schemes, and provide guidance in selecting the scheme based on weight sparsity and consistency of the L-1 weight norm across the columns.

Many powerful neural network (NN) models such as probabilistic graphical models (PGMs) and recurrent neural networks (RNNs) require flexibility in dataflow and weight access patterns as shown in Fig. 33.1.1 Typically, Compute-In-Memory (CIM) designs do not implement such dataflows or do so by replicating circuits at the memory periphery such as ADCs/neurons along both the rows and columns of the memory array, leading to an overhead in operation. This paper describes a CIM architecture implemented in a 130nm CMOS/RRAM process, that delivers the highest reported computational energy-efficiency of 74 tera-multiply-accumulates per second per watt (TMACS/W) for RRAM-based CIM architectures while simultaneously offering dataflow reconfigurability to address the limitations of previous designs. This is made possible through two key features: 1) a runtime reconfigurable dataflow with in-situ access to RRAM array and its transpose for efficient access to NN weights and 2) a voltage sensing stochastic integrate-and-fire analog neuron (I&F) that is reused for correlated double sampling (CDS), stochastic voltage integration, and threshold comparison.

Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computational demands of these abundant-data applications, such as deep learning-based AI, far exceed the capabilities of today’s computing systems and cannot be met by isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. This chapter will discuss how new computing nanosystems can deliver radical improvements in the energy efficiency and scalability of abundant-data applications, in the range of 1000×, through major advances across the computing stack: new transistor and memory technologies, new integration approaches, and new architectures for computation immersed in memory. Nanosystems with such massive benefits are essential for enabling new frontiers of applications across a wide range of domains, from highly energy-constrained and deeply-embedded computing systems all the way to the cloud.

One viable solution for continuous reduction in energy-per-operation is to rethink functionality to cope with uncertainty by adopting computational approaches that are inherently robust to uncertainty. It requires a novel look at data representations, associated operations, and circuits, and at materials and substrates that enable them. 3D integrated nanotechnologies combined with novel brain-inspired computational paradigms that support fast learning and fault tolerance could lead the way. Recognizing the very size of the brain’s circuits, hyperdimensional (HD) computing can model neural activity patterns with points in a HD space, that is, with hypervectors as large randomly generated patterns. At its very core, HD computing is about manipulating and comparing these patterns inside memory. Emerging nanotechnologies such as carbon nanotube field-effect transistors (CNFETs) and resistive RAM (RRAM), and their monolithic 3D integration offer opportunities for hardware implementations of HD computing through tight integration of logic and memory, energy-efficient computation, and unique device characteristics. We experimentally demonstrate and characterize an end-to-end HD computing nanosystem built using monolithic 3D integration of CNFETs and RRAM. With our nanosystem, we experimentally demonstrate classification of 21 languages with measured accuracy of up to 98% on >20,000 sentences (6.4 million characters), training using one text sample (≈100,000 characters) per language, and resilient operation (98% accuracy) despite 78% hardware errors in HD representation (outputs stuck at 0 or 1). By exploiting the unique properties of the underlying nanotechnologies, we show that HD computing, when implemented with monolithic 3D integration, can be up to 420× more energy-efficient while using 25× less area compared to traditional silicon complementary metal–oxide–semiconductor (CMOS) implementations.

We study highly confined plasmons in individual single-walled carbon nanohrbe nanoantennas in the mid-infrared regime. This work paves the way for extreme light-matter interactions at the nanoscale and quanttrm plasmonics.

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO 2 - based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) - this new approach makes our multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 106 cycles of endurance and a projected 10-year retention at 120°C. Using measured data from our 2 bits- per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values).

High performance carbon nanotube (CNT) network transistors with on-resistance (R on ) of DDQ ) and have the comparable active power (P ACTIVE ) consumption under the same operation frequency as compared to the operation without the power gating CNT transistors. The fabrication of CNT devices in the BEOL is verified to cause no performance degradation in the underlying FEOL Si CMOS devices. This study has successfully demonstrated heterogeneous integration of advanced Si logic circuits with low-cost and high-mobility CNT transistors in the BEOL fabricated at low, BEOL-compatible temperatures (250 °C).

Neuromorphic computing systems, which use electronic synapses and neurons, could overcome the energy and throughput limitations of today’s computing architectures. However, electronic devices that can accurately emulate the short- and long-term plasticity learning rules of biological synapses remain limited. Here, we show that multilayer hexagonal boron nitride (h-BN) can be used as a resistive switching medium to fabricate high-performance electronic synapses. The devices can operate in a volatile or non-volatile regime, enabling the emulation of a range of synaptic-like behaviour, including both short- and long-term plasticity. The behaviour results from a resistive switching mechanism in the h-BN stack, based on the generation of boron vacancies that can be filled by metallic ions from the adjacent electrodes. The power consumption in standby and per transition can reach as low as 0.1 fW and 600 pW, respectively, and with switching times reaching less than 10 ns, demonstrating their potential for use in energy-efficient brain-like computing. Vertically structured electronic synapses, which exhibit both short- and long-term plasticity, can be created using layered two-dimensional hexagonal boron nitride.

Exponential growth in data generation and large-scale data science has created an unprecedented need for inexpensive, low-power, low-latency, high-density information storage. This need has motivated significant research into multi-level memory devices that are capable of storing multiple bits of information per device. The memory state of these devices is intrinsically analog. Furthermore, much of the data they will store, along with the subsequent operations on the majority of this data, are all intrinsically analog-valued. Ironically though, in the current storage paradigm, both the devices and data are quantized for use with digital systems and digital error-correcting codes. Here, we recast the storage problem as a communication problem. This then allows us to use ideas from analog coding and show, using phase change memory as a prototypical multi-level storage technology, that analog-valued emerging memory devices can achieve higher capacities when paired with analog codes. Further, we show that storing analog signals directly through joint coding can achieve low distortion with reduced coding complexity. Specifically, by jointly optimizing for signal statistics, device statistics, and a distortion metric, we demonstrate that single-symbol analog codings can perform comparably to digital codings with asymptotically large code lengths. These results show that end-to-end analog memory systems have the potential to not only reach higher storage capacities than discrete systems but also to significantly lower coding complexity, leading to faster and more energy efficient data storage.

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Control of cation injection into the switching layer of conductive-bridge random access memory (CBRAM) during switching is a critical factor for CBRAM reliability. Although extrinsic approaches such as the insertion of a transistor in series have proven effective, solutions intrinsic to the CBRAM itself, which are desired for high density cross-point or 3-D vertical memory arrays, are quite limited. In this letter, we show the significant improvement of cycling endurance for Cu-based CBRAM by scaling the switching layer area down to 30 nm in diameter. Further study suggests that the injection of excessive Cu ions into the switching layer is suppressed owing to spatial limitation during the formation of the conductive filament. These results indicate that the area scaling of the switching layer is an effective solution for achieving highly reliable CBRAM devices.

Reliability of 80-, 100-, and 120-nm wide copper interconnects is improved using in situ grown graphene as a capping material. The graphene-capped Cu wires exhibit 2.4–3.5 $\times $ longer electromigration (EM) lifetime than thermally annealed Cu. In addition, the Cu resistivity is reduced by about 12%–30% and the breakdown current density is increased by 5%–7%. The graphene cap improves the Cu EM lifetime by mitigating Cu void formation at the interface. However, low-temperature grown graphene oxidizes readily and thus provides limited oxidation protection for the Cu wires.

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (DLS) of SiO2/Al2O3 insulator. Devices with contact area of 500 $\times $ 20 nm and lengths of $2~ {\mu }\text{m}$ show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the DLS enables a 60% reduction in reset energy compared with SiO2-isolated devices.

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade.

Photoelectrochemical (PEC) hydrogen production makes possible the direct conversion of solar energy into chemical fuel. In this work, PEC photoanodes consisting of GaAs nanowire (NW) arrays were fabricated, characterized, and then demonstrated for the oxygen evolution reaction (OER). Uniform and periodic GaAs nanowire arrays were grown on a heavily n-doped GaAs substrates by metal–organic chemical vapor deposition selective area growth. The nanowire arrays were characterized using cyclic voltammetry and impedance spectroscopy in a non-aqueous electrochemical system using ferrocene/ferrocenium (Fc/Fc+) as a redox couple, and a maximum oxidation photocurrent of 11.1 mA/cm2 was measured. GaAs NW arrays with a 36 nm layer of nickel oxide (NiO x ) synthesized by atomic layer deposition were then used as photoanodes to drive the OER. In addition to acting as an electrocatalyst, the NiO x layer served to protect the GaAs NWs from oxidative corrosion. Using this strategy, GaAs NW photoanodes were successfully used for the oxygen evolution reaction. This is the first demonstration of GaAs NW arrays for effective OER, and the fabrication and protection strategy developed in this work can be extended to study any other nanostructured semiconductor materials systems for electrochemical solar energy conversion.

This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 μm and larger) are demonstrated between silicon device dies and glass dies using this process.