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101. Modeling of the bridge threshold voltage in A2RAM cell

Author: Sebastien Martinie, M. Bawedin, F. Tcheme Wakam, Thierry Poiroux, Joris Lacord, and Sorin Cristoloveanu
Subjects: 010302 applied physics, Materials science, business.industry, Spice, Electrical engineering, Silicon on insulator, 01 natural sciences, Bridge (interpersonal), Threshold voltage, Stack (abstract data type), 0103 physical sciences, Poisson's equation, business, Dram
Abstract: We propose an analytical model of the bridge threshold voltage that governs the operation of the A2RAM capacitorless memory. It was developed starting from the solution of 1D Poisson equation in the unusual A2RAM vertical stack, and it was validated by TCAD simulations.
Published: 2019

102. Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell

Author: Norberto Salazar, Sorin Cristoloveanu, Francisco Gamiz, Carlos Navarro, Carlos Marquez, Philippe Galy, and Santiago Navarro
Subjects: 010302 applied physics, Materials science, Dielectric strength, business.industry, Z2-FET, Dielectric Breakdown, Reliability, 01 natural sciences, Temperature measurement, Electronic, Optical and Magnetic Materials, 1T-DRAM, Stress (mechanics), Capacitorless, Reliability (semiconductor), Fully depleted (FD), Ionization, Logic gate, 0103 physical sciences, Optoelectronics, Weibull, Electrical and Electronic Engineering, business, Weibull distribution, Voltage
Abstract: The experimental time-dependent dielectric breakdown and ON voltage reliability of advanced FD-SOI Z2-FET memory cells are characterized for the first time. The front-gate stress time is shown to significantly modulate the ON voltage and, hence, the memory window. The Weibull slope, β, indicating the device variability to breakdown, and the time to soft breakdown, α, present different trends depending on the cell geometry. This fact highlights the tradeoff between variability and reliability to account for in Z2-FET designs., H2020 REMINDER project (grant agreement No 687931) and TEC2017-89800-R are thanked for financial support.
Published: 2019

103. Z2-FET: a multi-functional device used for photodetection

Author: Xy. Cao, Jing Wan, Junbao Liu, Br. Lu, Maryline Bawedin, Yf. Chen, Sorin Cristoloveanu, and Alexander Zaslavsky
Subjects: 010302 applied physics, CMOS sensor, Materials science, business.industry, Interface (computing), 02 engineering and technology, Photodetection, 021001 nanoscience & nanotechnology, 01 natural sciences, Dynamic coupling, 0103 physical sciences, Optoelectronics, 0210 nano-technology, business, Sensitivity (electronics), Random access, Voltage
Abstract: In this work, we explore the application of Z2-FET in photodetection with TCAD simulation. Dynamic coupling effect is used to build up the carrier injection barrier and restore the feedback mechanism in Z2-FET with thick Si layer. The device is then used for photodetection in two operation modes, where the photoelectron accumulating at the front gate interface reduces the turn-on voltage (V ON ) with a sensitivity up to 10V/(μJ/cm2). With high output current and one-transistor random access ability, Z2-FET can find potential application as compact one-transistor active pixel sensor (1T-APS).
Published: 2019

104. Thin-Film FD-SOI BIMOS Topologies for ESD Protection

Author: Philippe Galy, Maud Vinet, Sorin Cristoloveanu, and Louise De Conti
Subjects: 010302 applied physics, Materials science, business.industry, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, Network topology, 01 natural sciences, Matrix (mathematics), CMOS, 0103 physical sciences, Optoelectronics, Thin film, 0210 nano-technology, Metal gate, business
Abstract: BIMOS devices - fabricated with the 28 nm thin-film high-k/metal gate FD-SOI CMOS technology - are demonstrated to be promising candidates for ESD protection. This manuscript discloses layouts of various BIMOS topologies in the thin-film. Among them, a 2D matrix of BIMOS is proposed. Those novel topologies were conceived, measured and compared at room temperature. DC, TLP and VF - TLP characterization data are provided and discussed for further optimization.
Published: 2019

105. Low-Frequency Noise Characteristics of GaN Nanowire Gate-All-Around Transistors With/Without 2-DEG Channel

Author: Christoforos G. Theodorou, Raphael Caulmilone, Sorin Cristoloveanu, M. Siva Pratap Reddy, Ki-Sik Im, Jung-Hee Lee, Gerard Ghibaudo, Kumoh National Institute of Technology, School of Electronics Engineering, Kyungpook National University, Kyungpook National University, Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Université Grenoble Alpes (UGA), National Research Foundation of Korea Grant funded by the KoreaGovernment (MSIP) under Grant NRF-2018R1A6A1A03025761 andGrant 2013R1A6A3A04057719, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, 2-D electron gas (2-DEG), Infrasound, carrier number fluctuation (CNF), Nanowire, Gallium nitride, gate-all-around (GAA), 01 natural sciences, Noise (electronics), Gallium arsenide, law.invention, chemistry.chemical_compound, AlGaN/GaN, law, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, Scattering, Transistor, Wide-bandgap semiconductor, low-frequency noise (LFN), Electronic, Optical and Magnetic Materials, [SPI.TRON]Engineering Sciences [physics]/Electronics, chemistry, nanowire, Optoelectronics, correlated mobility fluctuation (CMF), business
Abstract: International audience; Two different lateral GaN-based nanowire gate-all-around transistors with and without 2-D electron gas (2-DEG) channel were fabricated using top-down approach, and their noise characteristics were investigated. The nanowire transistor with 2-DEG channel had a relatively larger channel cross section, which consists of regrown AlGaN/GaN plateau on the trapezoidal GaN layer, and exhibited negative threshold voltages ( ${V} _{\textsf {th}}$ ). The transistor without 2-DEG channel consisted only GaN layer with triangular-shaped smaller channel cross section and exhibited a positive ${V} _{\textsf {th}}$ . Both nanowire transistors clearly demonstrated typical $1/{f}$ noise characteristics, but the AlGaN/GaN nanowire transistor with 2-DEG channel showed larger noise magnitude. The noise characteristics of both devices are well explained by the carrier number fluctuation with correlated mobility fluctuation model. Using this model, the interface trap densities and the remote Coulomb scattering parameters were extracted, revealing a worse interface quality for the AlGaN/GaN device on the one hand, but stronger scattering for the narrow GaN transistor on the other hand.
Published: 2019

106. Topology and design investigation on thin film silicon BIMOS device for ESD protection in FD-SOI technology

Author: Ph. Galy, M. Vinet, Sorin Cristoloveanu, G. Delahaye, Lorena Anghel, L. de Conti, STMicroelectronics [Crolles] (ST-CROLLES), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA)
Subjects: Silicon, Computer science, chemistry.chemical_element, Silicon on insulator, Topology (electrical circuits), Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Topology, 01 natural sciences, Porting, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Thin film, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Safety, Risk, Reliability and Quality, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, Electrostatic discharge, 020208 electrical & electronic engineering, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, PACS 8542, chemistry, CMOS, Node (circuits)
Abstract: The electrostatic discharge (ESD) protection is always a challenge for fully depleted silicon on insulator (FD-SOI) CMOS technology. Today, several efficient and robust solutions are available. In the framework of optimized solutions, it is interesting to investigate a protection according to its topology and design. First of all, this study will be based on 3D TCAD analysis of thin silicon film Bipolar MOS (BIMOS) devices with standard topology and with optimized body access. Then the design will be modified by adding new devices or by adjusting the parasitic elements. The aim is to better understand the device behavior and to push the performance. Additionally, silicon demonstrators have been fabricated, characterized and investigated. It appears that each design has advantages and drawbacks and should be chosen in accordance with the final implementation. The proposed design can also be ported to another technology node with an adaptation.
Published: 2019

107. Trap and 1/f-noise effects at the surface and core of GaN nanowire gate-all-around FET structure

Author: Raphael Caulmione, Mallem Siva Pratap Reddy, Ki-Sik Im, Sorin Cristoloveanu, Jung-Hee Lee, Kyungpook National University [Daegu], Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, gate-all-around, Nanowire, 1/f-noise, 02 engineering and technology, Trapping, 010402 general chemistry, 01 natural sciences, Capacitance, Depletion region, General Materials Science, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business.industry, field effect transistor (FET), Conductance, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Cutoff frequency, 0104 chemical sciences, nanowire, GaN trap, Optoelectronics, Field-effect transistor, 0210 nano-technology, business, Noise (radio)
Abstract: International audience; Using capacitance, conductance and noise measurements, we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1D) array of GaN nanowire gate-all-around field effect transistor (GAA FET), fabricated via a top-down process. The surface traps in such a low dimensional device play a crucial role in determining the device performance. The estimated surface trap density rapidly decreases with increasing frequency, ranging from 6.07 × 1012 cm−2·eV−1 at 1 kHz to 1.90 × 1011 cm−2·eV−1 at 1 MHz, respectively. The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (Vgs > Vth = 3.4 V) for all frquencies. In the surface depletion region (1.5 V < Vgs < Vth), the device is governed by 1/f at lower frequencies and 1/f2 noise at frequencies higher than ~ 5 kHz. The 1/f2 noise characteristics is attributed to additional generation–recombination (G–R), mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire. The cutoff frequency for the 1/f2 noise characteristics further shifts to lower frequency of 102–103 Hz when the device operates in deep-subthreshold region (Vgs < 1.5 V). In this regime, the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G–R noise prevails in the entire nanowire channel.
Published: 2019

108. Dispositifs et technologie silicium sur isolant totalement déserté (FD-SOI)

Author: Sorin Cristoloveanu
Abstract: La recente technologie Fully Depleted SOI (FD-SOI) est le prolongement naturel du SOI pour realiser des circuits integres a forte densite, haute frequence et basse consommation. En raison de leurs dimensions nanometriques, aussi bien en epaisseur qu’en longueur, les transistors FD-SOI presentent des mecanismes de fonctionnement et des caracteristiques tres specifiques. L’etat de l’art du FD-SOI est decrit en insistant sur les atouts des composants, les effets physiques particuliers et les techniques de caracterisations dediees. Des exemples de dispositifs innovants concus en filiere FD-SOI sont discutes.
Published: 2018

109. Effects of BOX thickness, silicon thickness, and backgate bias on SCE of ET-SOI MOSFETs

Author: David Chuyang Hong, Yuan Taur, Sorin Cristoloveanu, and Elizabeth Mei-hua Su
Subjects: 010302 applied physics, Materials science, Silicon, business.industry, Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Atomic and Molecular Physics, and Optics, Buried oxide, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Threshold voltage, chemistry, Reverse bias, 0103 physical sciences, Optoelectronics, Work function, Electrical and Electronic Engineering, 0210 nano-technology, business
Abstract: In this work, we investigate the effect of BOX (Buried OXide) and silicon thickness on the SCE (Short-Channel Effects) of ET-SOI (Extremely Thin Silicon-on-Insulator) MOSFETs. It is found that the minimum channel length Lmin is only moderately sensitive to the BOX thickness but strongly dependent on the silicon thickness. For a given threshold voltage, the choice of gate work function in combination with the backgate bias also plays a role on Lmin. Reverse bias mitigates SCE while forward bias aggravates SCE. An empirical expression of Lmin in terms of silicon thickness is given.
Published: 2021

110. Electrical Characterization of FDSOI by Capacitance Measurements in Gated p-i-n Diodes

Author: Maryline Bawedin, Jacques Cluzel, Sorin Cristoloveanu, Francois Andrieu, Carlos Navarro, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-11-JS03-0001,AMNESIA,Dispositifs Mémoires Nanométriques Innovants pour Applications Ultra Basse Consommation(2011), European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), and European Project: 619325,EC:FP7:ICT,FP7-ICT-2013-11,COMPOSE3(2013)
Subjects: Materials science, Capacitance, intergate coupling, Silicon on insulator, 02 engineering and technology, 01 natural sciences, fully depleted (FD), 0103 physical sciences, MOSFET, gated diode, characterization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, threshold voltage, Diode, SOI, 010302 applied physics, business.industry, p-i-n, 021001 nanoscience & nanotechnology, FDSOI, Electrical contacts, Electronic, Optical and Magnetic Materials, Threshold voltage, Logic gate, Optoelectronics, Transient (oscillation), 0210 nano-technology, business
Abstract: International audience; The versatility of split capacitance measurements on the standard SOI gated p-i-n diodes is presented and discussed. The presence of both n + - and p + -type contacts in the same structure eliminates the floating-body and transient effects, and stands as a major advantage over the conventional MOSFETs characterization. We demonstrate the feasibility of simultaneous electrical (threshold voltage for n- and p-channels) and structural (layer thickness) parameter extraction by systematic measurements and TCAD numerical simulations.
Published: 2016

111. A sharp-switching device with free surface and buried gates based on band modulation and feedback mechanisms

Author: Sorin Cristoloveanu, C. Fenouillet-Beranger, Philippe Ferrari, Yohann Solaro, Pascal Fonteneau, Charles-Alexandre Legrand, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)
Subjects: Materials science, Z3-FET, Z2-FET, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, SOI, 010302 applied physics, business.industry, CMOS, Electrical engineering, Swing, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Impact ionization, Sharp switch, Modulation, Band modulation, Free surface, Optoelectronics, 0210 nano-technology, business, Hardware_LOGICDESIGN
Abstract: We propose and demonstrate experimentally a band-modulation device with extremely sharp switching capability. The Z 3 -FET (Zero gate, Zero swing and Zero impact ionization) has no top gate, is processed with FDSOI CMOS technology, and makes use of two adjacent buried ground planes acting as back gates. The buried gates emulate respectively N + and P + regions in the undoped body, forming a virtual thyristor-like NPNP structure with feedback operation. Vertical output I A – V A and transfer I A – V G characteristics over more than 8 decades of current are measured with relatively low gate and drain bias (
Published: 2016

112. High-resolution mobility spectrum analysis of magnetoresistance in fully-depleted silicon-on-insulator MOSFETs

Author: Gilberto A. Umana-Membreno, S.-J. Chang, Maryline Bawedin, Lorenzo Faraone, Jarek Antoszewski, Sorin Cristoloveanu, School of Electrical, Electronic and Computer Engineering [Crawley] (EECE), The University of Western Australia (UWA), Department of Electrical Engineering [Yale University], Yale University [New Haven], Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
Subjects: Electron mobility, Condensed matter physics, Magnetoresistance, Chemistry, Carrier scattering, Induced high electron mobility transistor, FD-SOI Mobility Magnetoresistance Hall-effect Mobility spectrum analysis MOSFET, Silicon on insulator, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Hall effect, Electric field, MOSFET, Materials Chemistry, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering
Abstract: International audience; Multi-carrier transport in planar fully-depleted silicon-on-insulator (FD-SOI) MOSFETs has been investigated employing magnetic-field dependent geometrical magnetoresistance measurements and high-resolution mobility spectrum analysis. The results indicate that electronic transport in the 10 nm thick Si channel layer is due to two distinct and well-defined electron species. Although self-consistent Schrödinger–Poisson numerical calculations indicate significant localization of the total electron population near the back and front interfaces, the results of mobility spectrum analysis suggest that the mobility distributions associated with these spatially localized populations are strongly coupled through carrier scattering processes, and do not have independent and distinguishable mobility distributions. The two detected electron mobility distributions are thus evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs. The mobility maximum of the dominant carrier was found to occur under gate bias conditions that result in a minimum perpendicular effective electric field.
Published: 2015

113. Evidence of Supercoupling Effect in Ultrathin Silicon Layers Using a Four-Gate MOSFET

Author: Sotirios Athanasiou, Ph. Galy, Maryline Bawedin, Sorin Cristoloveanu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015)
Subjects: Materials science, Silicon, Polarity (physics), chemistry.chemical_element, 02 engineering and technology, Electron, FDSOI MOSFET, 01 natural sciences, law.invention, law, 0103 physical sciences, MOSFET, four-gate transistor, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, 010302 applied physics, business.industry, Transistor, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, silicon-on-insulator, chemistry, supercoupling, Optoelectronics, 0210 nano-technology, business, Voltage
Abstract: International audience; The supercoupling effect is demonstrated experimentally by monitoring the electron and hole currents in a field-effect transistor provided with p+ and n+ contacts. According to the polarity of the voltage applied to the front and back gates, only electrons or holes can be detected in 7-nm thick silicon layers. Thicker layers are not affected by supercoupling and can accommodate electrons and holes together.
Published: 2017

114. Photodiode with low dark current built in silicon-on-insulator using electrostatic doping

Author: Alexander Zaslavsky, K.-M. Zhu, M. Arsalan, Jun Liu, Jing Wan, and Sorin Cristoloveanu
Subjects: 010302 applied physics, Materials science, business.industry, Doping, Silicon on insulator, 02 engineering and technology, Photodetection, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Noise (electronics), Electronic, Optical and Magnetic Materials, Photodiode, law.invention, law, 0103 physical sciences, Materials Chemistry, Optoelectronics, Electrical and Electronic Engineering, 0210 nano-technology, business, p–n diode, Diode, Dark current
Abstract: In this paper, we demonstrate experimentally a novel SOI-based photodiode using electrostatic doping and fabricated in a simple, low-cost process. Unlike a conventional ion-implanted pn junction diode, the electrostatically doped devices feature extremely low reverse-bias current. When used for photodetection, our devices exhibit a dark current three decades lower than a conventional photodiode and provide excellent detectivity even under low optical power density. Our electrostatically-doped diodes also feature enhanced response in the near-UV and 1/f low-frequency noise.
Published: 2020

115. Persistent Floating‐Body Effects in Fully Depleted Silicon‐on‐Insulator Transistors

Author: Maryline Bawedin, Hyungjin Park, Jean-Pierre Colinge, and Sorin Cristoloveanu
Subjects: 010302 applied physics, Materials science, business.industry, Transistor, Silicon on insulator, 02 engineering and technology, Surfaces and Interfaces, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, law.invention, law, 0103 physical sciences, Materials Chemistry, Optoelectronics, Electrical and Electronic Engineering, 0210 nano-technology, business, Floating body effect
Published: 2020

116. ICPD: an SOI-based photodetector with high responsivity and tunable response spectrum

Author: Alexander Zaslavsky, Yf. Chen, J N. Deng, Sorin Cristoloveanu, Xy. Cao, Jing Wan, Zx. Guo, Br. Lu, Wz. Bao, Maryline Bawedin, Fudan University, School of Information Science and Engineering, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, Photocurrent, Materials science, business.industry, Transistor, Photodetector, Silicon on insulator, 02 engineering and technology, Substrate (electronics), 021001 nanoscience & nanotechnology, medicine.disease_cause, 01 natural sciences, 7. Clean energy, law.invention, Responsivity, law, 0103 physical sciences, medicine, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Response spectrum, Ultraviolet
Abstract: International audience; A novel photodetector based on a silicon-on-insulator (SOI) substrate is demonstrated experimentally in this work. The device uses the interface coupling effect in an SOI transistor structure to amplify the photocurrent, and thus achieves extremely high responsivity up to 6×10 4 A/W. The responsivity of the device under ultraviolet (UV) light is much higher than that under visible and near-infrared light, which implies potential application in visible-blind UV detection. Furthermore, a MoS 2 gate is combined with the SOI-based photodetector to tune the response spectrum and shift it to the near-infrared band. With high reponsivity and tunable response spectrum, the ICPD device can find many interesting applications.
Published: 2018

117. a new photodetector on SOI

Author: Xy. Caol, Alexander Zaslavsky, Br. Lu, J. Liu, Yf. Chen, Maryline Bawedin, Sorin Cristoloveanu, Jing Wan, Fudan University, School of Information Science and Engineering, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, Silicon on insulator, Photodetector, 02 engineering and technology, 01 natural sciences, 7. Clean energy, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Silicon-on-insulator, Lighting, 010302 applied physics, Substrates, business.industry, Photodetectors, Logic gates, Photoelectric effect, 021001 nanoscience & nanotechnology, Impact ionization, Logic gate, Couplings, Optoelectronics, Current (fluid), 0210 nano-technology, business, Sensitivity (electronics), Switches, Voltage
Abstract: session: SOI devices 1; International audience; In this work, we present a novel type of photodetector based on the Z2-FET (zero impact ionization and zero subthreshold swing) device. A dynamic coupling effect is used to form the carrier injection barriers that block the current flow in the Z2-FET. Our TCAD simulation shows that under illumination, photoelectrons accumulating under the gate effectively reduce the hole injection barrier, modulating the turn-on voltage and leading to photoresponse with excellent sensitivity and unique advantages.
Published: 2018

118. Is FD-SOI immune to floating body effects?

Author: Sorin Cristoloveanu, Hyungjin Park, Kyung Hwa Lee, Jean-Pierre Colinge, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015)
Subjects: 010302 applied physics, GIDL, Materials science, business.industry, Band-to-band tunneling current, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Subthreshold slope, Transient current, Hysteresis, Logic gate, body potential measurement, 0103 physical sciences, MOSFET, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Drain current, business, floating body effect, Quantum tunnelling
Abstract: session: SOI devices 2; International audience; Evidence for floating-body effects (FBE) in fully-depleted SOI with thickness below 25 nm is found from experiments. We investigate several facets of FBE: parasitic bipolar action, kink effect, transient current, hysteresis, steep subthreshold slope and meta-stable dip. The body potential is measured together with the drain current in order to demonstrate their close correlation, in particular for out-of-equilibrium operation. The FBEs are shown to interfere with gate tunneling and super-coupling effects.
Published: 2018

119. a new sharp switch device integrated in 28nm FD-SOI technology

Author: Philippe Galy, Claire Fenouillet-Beranger, Thomas Bedecarrats, Sorin Cristoloveanu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)
Subjects: 010302 applied physics, Materials science, business.industry, Silicon on insulator, body contact, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Temperature measurement, Subthreshold slope, Threshold voltage, Neuromorphic engineering, BIMOS, Logic gate, 0103 physical sciences, Optoelectronics, Sharp-switch, Bicmos integrated circuits, FD-SOI, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Metal gate, business
Abstract: session: tunnel transistors; International audience; A novel 2-components sharp switch device integrated in high-k metal gate UTBB 28 nm FD-SOI technology is presented, analyzed and measured in DC. It features a subthreshold slope of 2 mV/decade and offers several parameters to tune its characteristic, for ESD or neuromorphic applications.
Published: 2018

120. ψ-MOSFET Configuration for DNA Detection

Author: Cécile Delacour, Melania Banu, Mihaela Kusko, Licinius Benea, Maryline Bawedin, Sorin Cristoloveanu, Monica Simion, I. Ionica, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), National Institute for Research and Development in Microtechnologies (IMT-Bucharest), Thermodynamique et biophysique des petits systèmes (NEEL - TPS), Institut Néel (NEEL), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), PHC Brancusi (project 38 395QA), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), and Thermodynamique et biophysique des petits systèmes (TPS)
Subjects: DNA detection, SOI, Work (thermodynamics), Materials science, [SDV.BIO]Life Sciences [q-bio]/Biotechnology, business.industry, 010401 analytical chemistry, Field effect, Silicon on insulator, Charge (physics), 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Fluorescence, 0104 chemical sciences, Threshold voltage, ψ-MOSFET, MOSFET, Optoelectronics, field-effect, Sensitivity (control systems), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, surface functionalization
Abstract: International audience; This work proposes a novel method for DNA detection by using the ψ-MOSFET configuration. Systematic measurements of the drain current vs. gate voltage revealed an important shift of the characteristics corresponding to the charge of the biochemical species attached to the top surface of the device. The results were validated by fluorescent scanning. The advantages of this method are its simplicity and sensitivity.
Published: 2018

121. Second Harmonic Generation: A Non-Destructive Characterization Method for Dielectric-Semiconductor Interfaces

Author: A. Bouchard, X. Mescot, D. Blanc-Pelissier, Sorin Cristoloveanu, A. Kaminski-Cachopo, J. Chanzala, I. Ionica, G. Grosa, Ming Lei, G. Vitrant, M. Gri, D. Damianos, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), INL - Photovoltaïque (INL - PV), Institut des Nanotechnologies de Lyon (INL), Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-École Centrale de Lyon (ECL), Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE), Femtometrix, École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-École Centrale de Lyon (ECL), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)
Subjects: 010302 applied physics, Materials science, Passivation, Silicon, business.industry, Second-harmonic generation, chemistry.chemical_element, 02 engineering and technology, Dielectric, 021001 nanoscience & nanotechnology, 7. Clean energy, 01 natural sciences, [SPI.MAT]Engineering Sciences [physics]/Materials, Semiconductor, chemistry, Photovoltaics, 0103 physical sciences, Optoelectronics, Microelectronics, Thin film, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract: International audience; This paper reviews the application of second harmonic generation (SHG) to characterize dielectric-semiconductor interfaces used in microelectronics and photovoltaics. Based on non-linear optics, the method is non-destructive, so particularly advantageous for thin films. The theoretical background shows the possibility to access the electric field at interfaces and consequently to have a non-destructive measurement for interface state densities or fixed charges in oxides. Two more detailed examples of application of SHG characterization will be shown: field-effect passivation of silicon using thin film deposited alumina and interface analysis of silicon-on-insulator substrates.
Published: 2018

122. Impact of Low-Temperature Coolcube™ Process on the Performance of FDSOI Tunnel FETs

Author: C. Diaz-Llorente, Maud Vinet, Sorin Cristoloveanu, Gerard Ghibaudo, Christoforos G. Theodorou, J.-P. Colinge, C. Le Royer, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, Materials science, business.industry, Process (computing), 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, Noise (electronics), Charge pumping, Logic gate, 0103 physical sciences, MOSFET, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Quantum tunnelling
Abstract: session: 3D technology II; International audience; Tunnel FETs fabricated using the low-temperature Cool Cube TM process are compared with devices made with standard high-temperature (HT) technology. Charge pumping (CP) and low-frequency noise (LFN) measurements were performed to evaluate the impact of low-temperature (LT) process on the device performance. LT devices feature a higher density of source/drain junction defects, due to lower thermal budget, causing higher levels of LFN. These defects enhance the trap-assisted tunneling (TAT) current which is further amplified by the more abrupt junctions obtained using LT processing.
Published: 2018

123. A highly sensitive photodetector based on deepdepletion effects in SOI transistors

Author: Alexander Zaslavsky, M. Arsalan, Br. Lu, Xy. Cao, Maryline Bawedin, Jing Wan, Sorin Cristoloveanu, Yf. Chen, Fudan University, School of Information Science and Engineering, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, Materials science, business.industry, Transistor, 0211 other engineering and technologies, Silicon on insulator, Photodetector, 02 engineering and technology, Photodetection, 01 natural sciences, Signal, law.invention, Responsivity, law, Logic gate, 021105 building & construction, 0103 physical sciences, Optoelectronics, Transient (oscillation), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business
Abstract: session: SOI devices 1; International audience; This work reports a transient effect found in silicon-on-insulator (SOI) substrates, where the current of the transistor changes slowly under a back-gate voltage pulse. We show via TCAD simulation that the operating principle arises from deep depletion in the SOI substrate. This effect is further used for photodetection with extremely high $7.3 \times 10 ^{6}\mathrm {A}/\mathrm {W}$ responsivity and signal read-out without need for charge transfer.
Published: 2018

124. Evidence of fast and low-voltage A2RAM ‘1’ state programming

Author: Joris Lacord, Sorin Cristoloveanu, Maryline Bawedin, Jean-Charles Barbe, Sebastien Martinie, Francois Tcheme Wakam, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), and European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016)
Subjects: 010302 applied physics, Silicon, Computer science, chemistry.chemical_element, 02 engineering and technology, band-to-band tunneling, TCAD simulation, 021001 nanoscience & nanotechnology, programming methodology, 01 natural sciences, 1T-DRAM, Software development process, Matrix (mathematics), Impact ionization, chemistry, 0103 physical sciences, Electronic engineering, State (computer science), impact ionization, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Low voltage, Quantum tunnelling, A2RAM, Voltage
Abstract: session Memoty (7.4); International audience; For the first time, we demonstrate a new concept for programming the `1' state in A2RAM based on the impact ionization in the bridge, which can be assisted by the band-to-band tunneling effect in the top part of the silicon film. This new programming method reduces the programming voltage and writing time, making the A2RAM suitable as 1T-DRAM. Evidenced through TCAD simulation, the feasibility in matrix environment is also demonstrated.
Published: 2018

125. Sharp switching, hysteresis-free characteristics of Z 2 -FET for fast logic applications

Author: Kyung Hwa Lee, S. Sato, Pascal Fonteneau, H. El Dirani, Sorin Cristoloveanu, Maryline Bawedin, STMicroelectronics [Crolles] (ST-CROLLES), STMicroelectronics [Grenoble] (ST-GRENOBLE), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Silicon on insulator, Z2-FET, 02 engineering and technology, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, 7. Clean energy, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Fully Depleted SOI (FDSOI), 010302 applied physics, Physics, business.industry, 021001 nanoscience & nanotechnology, Logic Switch, Subthreshold slope, Anode, Impact ionization, Hysteresis, Dual Ground Planes, Logic gate, Optoelectronics, 0210 nano-technology, business, Dram, band-modulation, Hardware_LOGICDESIGN, Sharp Switch
Abstract: session A4L-F: Emerging Devices and Applications; International audience; A logic switch for integrated circuits is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z 2 -FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a band-modulation device that shows remarkable performance in terms of ON/OFF current ratio and sharp switch (~ 1 mV/decade). The Z 2 -FET capability for ESD protection and capacitorless DRAM has already been documented. However, the presence of an inherent hysteresis effect has inhibited so far fast logic applications. A new generation of Z 2 -FETs with single or dual ground-plane has been fabricated with Ultra-Thin Body and Buried Oxide (UTBB) SOI technology. We demonstrate that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. Systematic measurements reveal the key roles of the device parameters and bias on the speed of operation.
Published: 2018

126. MSDRAM, A2RAM and Z2-FET performance benchmark for 1T-DRAM applications

Author: Mukta Singh Parihar, Jean-Charles Barbe, Francois Tcheme Wakam, Maryline Bawedin, Sorin Cristoloveanu, Carlos Navarro, Joris Lacord, Fransisco Gamiz, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Universidad de Granada = University of Granada (UGR), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and University of Granada [Granada]
Subjects: 010302 applied physics, Hardware_MEMORYSTRUCTURES, Computer science, TCAD simulation, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Benchmark, 021001 nanoscience & nanotechnology, 01 natural sciences, FDSOI, Soi substrate, 1T-DRAM, Computational science, memory, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Benchmark (computing), Calibration, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Dram
Abstract: session Memory (12.4); International audience; In this study, we propose a benchmark of performance between three promising 1T-DRAM device structures on SOI substrate: MSDRAM, A2RAM and Z 2 -FET. For a fair comparison, TCAD simulation with the same basic calibration and typical 28FDSOI technological parameters was used. The merits and limitations of each variant are discussed.
Published: 2018

127. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

Author: J.-P. Colinge, Gerard Ghibaudo, Perrine Batude, C-M. V. Lu, F. Allain, C. Le Royer, C. Fenouillet-Beranger, M. Vinet, Sorin Cristoloveanu, C. Diaz Llorente, Sebastien Martinie, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)
Subjects: Materials science, Fabrication, Tunnel FET, Schottky barrier, Silicon on insulator, 02 engineering and technology, Epitaxy, 01 natural sciences, Planar, TFET, 0103 physical sciences, Materials Chemistry, Low temperature, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Quantum tunnelling, 3D integration, 010302 applied physics, SOI, business.industry, SPER, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Tunnelling BTBT, Electronic, Optical and Magnetic Materials, Threshold voltage, Optoelectronics, 0210 nano-technology, business, Voltage
Abstract: International audience; This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.
Published: 2018

128. Experimental Demonstration of Operational Z 2 -FET Memory Matrix

Author: Carlos Navarro, Maryline Bawedin, Sorin Cristoloveanu, Philippe Galy, Carlos Marquez, Santiago Navarro, Hassan El Dirani, Francisco Gamiz, Andy Pickering, University of Granada [Granada], STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Surecore, Leeds
Subjects: diode, Computer science, Z²-FET, Silicon on insulator, Z2-FET, 02 engineering and technology, 01 natural sciences, 1T-DRAM, Matrix (mathematics), Capacitorless, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Diode, 010302 applied physics, Hardware_MEMORYSTRUCTURES, Matrix, business.industry, Reading (computer), Array, p-i-n, 021001 nanoscience & nanotechnology, matrix, Electronic, Optical and Magnetic Materials, DRAM, Fully depleted (FD), Logic gate, Scalability, silicon on insulator, 0210 nano-technology, business, Computer hardware, Dram, Dram memory
Abstract: In this letter, a functional Z2-FET DRAM memory matrix is experimentally demonstrated for the first time. Word-level operation with simultaneous reading and programming accesses is successfully proved. Disturbance is also explored, and the results demonstrate bitline disturbance immunity. Furthermore, the fabricated memory matrix, which includes only one selector per word-line, facilitates the scalability of the memory for increasing array dimensions., H2020 REMINDER project (grant agreement No 687931), TEC2014-59730and P12-TIC-1996 are thanked for financial support.
Published: 2018

129. Kink effect in ultrathin FDSOI MOSFETs

Author: H.G. Choi, Sorin Cristoloveanu, M. Bawedin, Hyungjin Park, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), TCAD team, DMR group, SK Hynix Inc, and European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016)
Subjects: Materials science, Silicon on insulator, 02 engineering and technology, 01 natural sciences, Super-coupling, MOSFET, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Floating-body effect, Nonlinear Sciences::Pattern Formation and Solitons, Floating body effect, 010302 applied physics, SOI, business.industry, Kink effect, 021001 nanoscience & nanotechnology, Condensed Matter Physics, FDSOI, Electronic, Optical and Magnetic Materials, Body potential, Optoelectronics, lipids (amino acids, peptides, and proteins), 0210 nano-technology, business, Communication channel
Abstract: International audience; Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (
Published: 2018

130. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

Author: Guy Vitrant, I. Ionica, D. Blanc-Pelissier, Ming Lei, D. Damianos, J. Changala, A. Kaminski-Cachopo, Sorin Cristoloveanu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), INL - Photovoltaïque (INL - PV), Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-École Centrale de Lyon (ECL), Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Université de Lyon-Institut National des Sciences Appliquées (INSA)-École Centrale de Lyon (ECL), Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), and Université de Lyon-École supérieure de Chimie Physique Electronique de Lyon (CPE)
Subjects: Materials science, Interface (computing), multilayers, Silicon on insulator, 02 engineering and technology, 01 natural sciences, Signal, [SPI.MAT]Engineering Sciences [physics]/Materials, nonlinear optics modeling, Electric field, 0103 physical sciences, Materials Chemistry, Wafer, Electrical and Electronic Engineering, 010302 applied physics, SOI, business.industry, Charge density, Second-harmonic generation, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Characterization (materials science), Second Harmonic Generation, Optoelectronics, 0210 nano-technology, business
Abstract: International audience; In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.
Published: 2018

131. Bufferless GaN-Based MOSFETs Fabricated on GaN-on-Insulator Wafer

Author: Jung-Hee Lee, Sorin Cristoloveanu, Ki-Sik Im, Raphael Caulmilone, Chul-Ho Won, Kyungpook National University [Daegu], Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, gate‐all‐around, Materials science, business.industry, Nanowire, Insulator (electricity), 02 engineering and technology, Surfaces and Interfaces, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, nanowire, 0103 physical sciences, Materials Chemistry, Optoelectronics, Wafer, Electrical and Electronic Engineering, aluminum gallium nitride/gallium nitride, gallium nitride‐on‐insulator, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, gate controllability
Abstract: International audience; Three types of bufferless GaN‐based FETs are fabricated on GaN‐on‐insulator (GaNOI) wafer: i) recessed‐gate AlGaN/GaN MOSFET with threshold voltage (Vth) of 4 V; ii) AlGaN/GaN nanowire gate‐all‐around (GAA) MOSFET with Vth of −2 V; and iii) GaN nanowire GAA‐MOSFET with Vth of 3.5 V. These devices are characterized and compared. The nanowire GAA‐MOSFET can be easily fabricated by simply removing buried oxide layer of GaNOI wafer. The recessed‐gate AlGaN/GaN MOSFET presents poor on‐current characteristic. On the other hand, the nanowire GAA‐MOSFETs show improved on‐current, reduced subthreshold swing (SS), good pinch‐off characteristics, and negligible current collapse phenomenon.
Published: 2018

132. Evaluation of thin-oxide Z 2 -FET DRAM cell

Author: Carlos Marquez, Maryline Bawedin, H. Park, Kyung Hwa Lee, Sorin Cristoloveanu, Francisco Gamiz, Carlos Navarro, Ph. Galy, Mukta Singh Parihar, Santiago Navarro, Universidad de Granada = University of Granada (UGR), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and University of Granada [Granada]
Subjects: 010302 applied physics, Materials science, business.industry, Silicon on insulator, Insulator (electricity), 01 natural sciences, Anode, Memory behavior, Gate oxide, Logic gate, 0103 physical sciences, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, business, Thin oxide, Dram
Abstract: session 2: Memories; International audience; Advanced 28 nm node FDSOI Z 2 -FETs with thin top-gate insulator are characterized as capacitor-less DRAM cells. Results demonstrate effective Z 2 -FET memory behavior for narrow devices (below 1 μm). As compared with thicker gate oxide Z 2 -FETs, thinning the insulator yields lower performance in terms of retention, variability and stability of the logic states during holding.
Published: 2018

133. Innovative tunnel FET architectures

Author: Jean-Pierre Colinge, Sebastien Martinie, Gerard Ghibaudo, Jing Wan, Carlos Diaz Llorente, Maud Vinet, Cyrille Le Royer, Sorin Cristoloveanu, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Fudan University, School of Information Science and Engineering, and ANR-10-EQPX-0030,FDSOI11,Plateforme FDSOI pour le node 11nm(2010)
Subjects: Materials science, Tunnel FET, Pure Boron, Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, 01 natural sciences, chemistry.chemical_compound, Extended-Source, tunneling, TFET, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Boron, BTBT, Quantum tunnelling, 010302 applied physics, Sharp Tip, SOI, TCAD, business.industry, Doping, 021001 nanoscience & nanotechnology, Silicon-germanium, Anode, chemistry, Logic gate, Optoelectronics, 0210 nano-technology, business, Layer (electronics)
Abstract: session 3: Simulation; International audience; We propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD. The extension of the source (anode) at the bottom of the body generates vertical band-to-band tunneling with a very steep slope and higher ION than lateral tunneling, but only for gate lengths longer than 100 nm. Using a heavily doped boron thin layer at the bottom increases ION even for aggressive gate lengths. Implementation of a tip in the source provides performance similar to the reference TFET. TCAD simulation using SiGe instead of Si shows current drive increase when using the thin boron layer for very thin channels, even for shorter gate lengths.
Published: 2018

134. Nanoindentation effects on the electrical caracterizaron in Ψ-MOSFET configuration

Author: Licinius Benea, Maryline Bawedin, Cécile Delacour, Sorin Cristoloveanu, T. Cerba, I. Ionica, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire des technologies de la microélectronique (LTM ), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Thermodynamique et biophysique des petits systèmes (TPS), Institut Néel (NEEL), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), AGIR-POLE CLEPS, ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and Thermodynamique et biophysique des petits systèmes (NEEL - TPS)
Subjects: 010302 applied physics, SOI, [PHYS]Physics [physics], Materials science, Condensed matter physics, Silicon, nanoindentation, chemistry.chemical_element, Ψ-MOSFET, 02 engineering and technology, Nanoindentation, 021001 nanoscience & nanotechnology, 01 natural sciences, law.invention, metal-semiconductor contact, Pressure measurement, Electrical transport, chemistry, law, 0103 physical sciences, MOSFET, field-effect, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Drain current
Abstract: session poster; International audience; The effect of probe-induced nanoindentation on the electrical transport in Ψ-MOSFET is presented. Systematic measurements were performed in order to evaluate the dependence of the drain current on the probe pressure in different operating regimes. This enabled to investigate the existence of the metallic Si-II crystallographic form of silicon, which emerges at high pressures and shows a significant impact in the accumulation regime.
Published: 2018

135. GDNMOS and GDBIMOS devices for ESD protection in 28nm thin film UTBB FD-SOI technology

Author: Sorin Cristoloveanu, Philippe Galy, Louise De Conti, Maud Vinet, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)
Subjects: Materials science, Silicon on insulator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Thin film, Hardware_ARITHMETICANDLOGICSTRUCTURES, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, NMOS logic, GDBIMOS, 010302 applied physics, business.industry, Electrostatic Discharges ESD, GDNMOS, 021001 nanoscience & nanotechnology, Cathode, Anode, CMOS, Logic gate, Optoelectronics, FD-SOI, Resistor, 0210 nano-technology, business, Hardware_LOGICDESIGN
Abstract: session 7: Characterization; International audience; GDNMOS (Gated Diode merged NMOS) and GDBIMOS (Gated Diode merged BIMOS) were fabricated using the 28nm thin film UTBB FD-SOI CMOS technology. Different connectivity conditions were measured and simulated. The devices are reconfigurable and promising for ESD protection applications.
Published: 2018

136. Towards a magnetoresistance characterization methodology for 1D nanostructured transistors

Author: Lorenzo Faraone, Nima Dehdashti Akhavan, Gilberto A. Umana-Membreno, Sorin Cristoloveanu, Jarek Antoszewski, School of Electrical, Electronic and Computer Engineering [Crawley] (EECE), The University of Western Australia (UWA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, Materials science, Magnetoresistance, business.industry, ComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS, Transistor, Nanowire, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, mobility, Characterization (materials science), law.invention, Magnetic field, nanowires, law, 0103 physical sciences, Optoelectronics, magnetoresistance, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract: session 7: Characterization; International audience; A novel approach to magnetoresistance characterization of ID-like nanoscaled transistor structures is presented. The proposed approach, which is based on the physical magnetoresistance effect (PMR), exploits the reality that carriers have non-discrete velocity distributions even when only a single carrier species is present.
Published: 2018

137. Novel photodetector based on FD-SOI substrate with interface coupling effect

Author: Br. Lu, Yf. Chen, Xy. Cao, Alexander Zaslavsky, Jing Wan, J N. Deng, H B. Liu, Maryline Bawedin, Sorin Cristoloveanu, Fudan University, School of Information Science and Engineering, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, Silicon, business.industry, chemistry.chemical_element, Photodetector, 02 engineering and technology, Substrate (electronics), Electron, 021001 nanoscience & nanotechnology, 7. Clean energy, Responsivity, 020210 optoelectronics & photonics, Semiconductor, chemistry, Logic gate, MOSFET, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business
Abstract: session Contact and Junction Technologies for phonon-electron interaction (S06-01 invited); International audience; We have proposed and demonstrated experimentally a novel semiconductor photodetector based on fully depleted silicon-on-insulator (FD-SOI) substrate. The device utilizes the interface coupling effect uniquely found in FD-SOI MOSFET, in which the photo-generated electrons accumulate at the top interface modulate the hole current at the bottom interface. The responsivity of this device reaches more than 1×10 4 A/W and, unlike other photodetectors based on SOI substrate, increases as the top silicon layer thickness reduces.
Published: 2018

138. Normally-off AlGaN/GaN-based MOS-HEMT with self-terminating TMAH wet recess etching

Author: In Man Kang, Sorin Cristoloveanu, Dong-Hyeok Son, Young-Woo Jo, Jun-Hyeok Lee, Jae Hwa Seo, Jung-Hee Lee, Ji Heon Kim, Jong-Won Lim, Sang-Heung Lee, Chul-Ho Won, Kyungpook National University [Daegu], Electronics and Telecommunications Research Institute [DaeJeon] (ETRI), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, 02 engineering and technology, High-electron-mobility transistor, 01 natural sciences, Normally-off, Ion, Self-terminating wet etching TMAH solution, chemistry.chemical_compound, Etching (microfabrication), 0103 physical sciences, Materials Chemistry, Breakdown voltage, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Negligible hysteresis, business.industry, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Threshold voltage, Hysteresis, Ammonium hydroxide, chemistry, Optoelectronics, 0210 nano-technology, business, Science, technology and society, Gate recess
Abstract: International audience; Normally-off AlGaN/GaN-based MOS-HEMT has been fabricated by utilizing damage-free self-terminating tetramethyl ammonium hydroxide (TMAH) recess etching. The device exhibited a threshold voltage of +2.0 V with good uniformity, extremely small hysteresis of ∼20 mV, and maximum drain current of 210 mA/mm. The device also exhibited excellent off-state performances, such as breakdown voltage of ∼800 V with off-state leakage current as low as ∼10−12 A and high on/off current ratio (Ion/Ioff) of 1010. These excellent device performances are believed to be due to the high quality recessed surface, provided by the simple self-terminating TMAH etching. Previous article in issue
Published: 2018

139. Performance Improvement and Sub-60 mV/Decade Swing in AlGaN/GaN FinFETs by Simultaneous Activation of 2DEG and Sidewall MOS Channels

Author: Yue Xu, Jung-Hee Lee, Ki-Sik Im, Maryline Bawedin, Sorin Cristoloveanu, Nanjing University of Posts and Telecommunications [Nanjing] (NJUPT), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Kyungpook National University [Daegu]
Subjects: Materials science, Transconductance, subthreshold swing (SS), Gallium nitride, 2-D electron gas (2DEG), 02 engineering and technology, 01 natural sciences, law.invention, chemistry.chemical_compound, law, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, AlGaN/GaN fin-shaped field-effect transistor (FinFET), fully depleted, Transistor, Wide-bandgap semiconductor, Swing, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, Threshold voltage, chemistry, Logic gate, Optoelectronics, 0210 nano-technology, business, Fermi gas
Abstract: This paper presents a new concept, supported by 3-D TCAD simulations, for improving the performance and subthreshold swing (SS) of enhancement-mode AlGaN/GaN fin-shaped field-effect transistors (FinFETs). By choosing appropriate device parameters, the formation of 2-D electron gas (2DEG) can be delayed such as to ensure simultaneous activation of 2DEG and sidewall MOS channels at positive threshold voltage for normally off operation. The 2DEG channel starts forming in the middle of the fin, whereas the edges are depleted by the lateral MOS gates. Not only increasing the gate voltage does the 2DEG charge increase, but also the effective width is enlarged being less depleted by the gates. This double-2DEG mechanism adds to the regular MOS channels on the sidewalls and enables enhanced performance. The 3-D TCAD simulations indicate that narrow FinFET (20 nm) can exhibit excellent switching characteristics: very low SS of 55 mV/decade, below the 60 mV/decade limit, high on/off current ratio of 1010, and good current driving capability due to the added 2DEG channel contribution. The maximum transconductance is 350 mS/mm, the drain current reaches 380 mA/mm, and the on resistance is as low as 0.018 $\text{m}\Omega \cdot \text {cm}^{2}$ .
Published: 2018

140. Interface Coupled Photodetector (ICPD) With High Photoresponsivity Based on Silicon-on-Insulator Substrate (SOI)

Author: Sorin Cristoloveanu, Jinhai Shao, Jianan Deng, Maryline Bawedin, Bing-Rui Lu, Alexander Zaslavsky, Yifang Chen, Jing Wan, Fudan University, School of Information Science and Engineering, School of Engineering (Brown Engineering), Brown University, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: Materials science, Interface (computing), Photodetector, Silicon on insulator, 02 engineering and technology, Substrate (electronics), 01 natural sciences, 7. Clean energy, Interface coupling effect, Responsivity, Coupling effect, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Coupling, SOI/GeOI based photodetector, business.industry, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, high photoresponsivity, Optoelectronics, imaging sensor arrays, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Biotechnology
Abstract: International audience; A CMOS-compatible photodetector with high responsivity is reported. This device utilizes the unique interface coupling effect found in fully depleted silicon on insulator (SOI) MOSFETs. Unlike conventional SOI photodetectors, the proposed device shows higher photoresponsivity in thinner Si films due to stronger interface coupling, as confirmed by TCAD simulations. A prototype device fabricated with a simplified process flow achieves a record photoresponsivity up to 3.3 x 104 A/W.
Published: 2018

141. Current Collapse-Free And Self-Heating Performances In Normally Off Gan Nanowire Gaa-Mosfets

Author: Yong Tae Kim, Raphael Caulmilone, Sorin Cristoloveanu, Ki-Sik Im, G. Atmaca, Jung-Hee Lee, Chul-Ho Won, Kyungpook National University [Daegu], Department of Physics, Gazi University, Ancara, Silicon-on-Insulator Technologies (SOITEC), Parc Technologique des Fontaines, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Korea Advanced Institute of Science and Technology (KAIST)
Subjects: Materials science, gate-all-around, Nanowire, Gallium nitride, 02 engineering and technology, Substrate (electronics), GaN-on-insulator, 01 natural sciences, GaN, chemistry.chemical_compound, MOSFET, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, One half, business.industry, Wide-bandgap semiconductor, self-heating, 021001 nanoscience & nanotechnology, dynamic mode, Electronic, Optical and Magnetic Materials, chemistry, Logic gate, nanowire, Optoelectronics, lcsh:Electrical engineering. Electronics. Nuclear engineering, 0210 nano-technology, business, lcsh:TK1-9971, Biotechnology, Voltage
Abstract: International audience; Normally off lateral GaN nanowire gate-all-around MOSFETs have been fabricated on the GaN-on-insulator substrate. The dynamic measurement proved that the devices with various nanowire heights exhibit current collapse-free characteristics implying that the electrons in the isolated nanowire channel do not suffer from trapping effects. However, the dc current level measured at high drain and gate voltage is reduced to approximately one half of the value measured in dynamic mode. This is attributed to the difficulty in heat dissipation because the suspended lateral nanowire channel is thermally isolated from the substrate. However, the heat dissipation is mitigated as the nanowire size increases.
Published: 2018

142. SOI Materials and Devices

Author: Sorin Cristoloveanu and George K. Celler
Subjects: Materials science, business.industry, Optoelectronics, Silicon on insulator, business
Published: 2017

143. Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Author: Joris Lacord, Campbell Millar, Mukta Singh Parihar, Pascal Fonteneau, Hassan El Dirani, Yong Tae Kim, Sorin Cristoloveanu, Maryline Bawedin, Jean-Charles Barbe, Francisco Gamiz, Noel Rodriguez, Siegfried Karg, Paul Wells, Asen Asenov, Binjie Cheng, Carlos Navarro, M. Duan, Philippe Galy, Cyrille Le Royer, Fikru Adamu-Lema, University of Granada [Granada], Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), James Watt School of Engineering [Univ Glasgow], University of Glasgow, Synopsys Inc., STMicroelectronics [Crolles] (ST-CROLLES), IBM Research Laboratory [Zurich], IBM Research [Zurich], Surecore, Leeds, Korea Advanced Institute of Science and Technology (KAIST), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and Universidad de Granada = University of Granada (UGR)
Subjects: Engineering, Z²-FET, Z2-FET, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, eDRAM, Semiconductor memories, 01 natural sciences, fully depleted (FD), 1T-DRAM, Capacitorless, capacitorless, Low-power, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Ground plane, Electrical and Electronic Engineering, Diffusion (business), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Silicon-on-insulator, 010302 applied physics, lifetime, Hardware_MEMORYSTRUCTURES, business.industry, Reading (computer), ground plane, Electrical engineering, Charge (physics), Feedback effect, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, sharp switch, Fully depleted (FD), Sharp switch, T-Dram, Logic gate, feedback effect, State (computer science), 0210 nano-technology, business, silicon-on-insulator (SOI), Lifetime, Dram
Abstract: This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). DOI: 10.1109/TED.2017.2751141, (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.", The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions.
Published: 2017

144. Growth of AlN/GaN HEMT structure Using Indium-surfactant

Author: Jeong-Gil Kim, Yong Tae Kim, Sorin Cristoloveanu, Young-Woo Jo, Jun-Hyeok Lee, Do-Kywn Kim, Chul-Ho Won, and Jung-Hee Lee
Subjects: Electron mobility, Materials science, business.industry, Transconductance, chemistry.chemical_element, Heterojunction, High-electron-mobility transistor, Electronic, Optical and Magnetic Materials, chemistry, Hall effect, MOSFET, Optoelectronics, Electrical and Electronic Engineering, business, Sheet resistance, Indium
Abstract: We have grown AlN/GaN heterostructure which is a promising candidate for mm-wave applications. For the growth of the high quality very thin AlN barrier, indium was introduced as a surfactant at the growth temperature varied from 750 to 1070 ℃, which results in improving electrical properties of two-dimensional electron gas (2DEG). The heterostructure with barrier thickness of 7 ㎚ grown at of 800 ℃ exhibited best Hall measurement results; such as sheet resistance of 215 Ω/□, electron mobility of 1430 ㎠/V·s, and two-dimensional electron gas (2DEG) density of 2.04 ｘ 10 13 /㎠. The high electron mobility transistor (HEMT) was fabricated on the grown heterostructure. The device with gate length of 0.2 ㎛ exhibited excellent DC and RF performances; such as maximum drain current of 937 ㎃/㎜, maximum transconductance of 269 mS/㎜, current gain cut-off frequency of 40 ㎓, and maximum oscillation frequency of 80 ㎓.
Published: 2015

145. Parasitic bipolar effect in ultra-thin FD SOI MOSFETs

Author: Sorin Cristoloveanu, Irina Ionica, Maryline Bawedin, Fanyu Liu, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), ANR-10-LABX-0055,MINOS Lab,Minatec Novel Devices Scaling Laboratory(2010), European Project: CT208,Catrene, European Project: 325633,EC:FP7:SP1-JTI,ENIAC-2012-2,PLACES2BE(2012), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)
Subjects: Materials science, business.industry, Heterostructure-emitter bipolar transistor, Electrical engineering, Silicon on insulator, Ultra-thin FD SOI, Parasitic bipolar transistor, Condensed Matter Physics, Parasitic bipolar effect, Electronic, Optical and Magnetic Materials, Band-to-band tunneling, Materials Chemistry, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, Current (fluid), business, Gate current, Quantum tunnelling
Abstract: International audience; The parasitic bipolar effect is investigated in fully-depleted silicon-on-insulator (FD SOI) n-type MOSFETs with ultra-thin films (5–10 nm). Our measurements show that at low drain bias the drain leakage current is governed by the gate current. Beyond VD > 1.0 V, leakage current amplification is observed in short-channel 10-nm thick devices. With film thickness shrinking, the current amplification is suppressed. We explain this amplification by the turn-on of the lateral parasitic bipolar transistor. TCAD simulations confirm that the parasitic bipolar is activated due to holes generated by band-to-band tunneling at the drain side and accumulated in the floating body. An effective method for the extraction of bipolar gain is proposed based on the comparison of leakage current in short- and long-channel devices. The experimental method is validated through simulations.
Published: 2015

146. Frontiers In Electronics - Selected Papers From The Workshop On Frontiers In Electronics 2015 (Wofe-15)

Author: Sorin Cristoloveanu, Michael S Shur, Sorin Cristoloveanu, and Michael S Shur
Subjects: Electronics--Technological innovations--Congresses, Electronics--Research
Abstract: Rapid pace of electronic technology evolution and current economic climate compel a merger of such technical areas as low-power digital electronics, microwave power circuits, optoelectronics, etc., which collectively have become the foundation of today's electronic technology.This Workshop aims at encouraging active cross-fertilization of the different'species'in this electronic planet. The WOFE2015 had gather experts from academia, industry, and government agencies to review the recent exciting breakthroughs and their underlying physical mechanisms.This Monographs includes ten invited articles; cover topics ranging from Ultra-thin silicon nanowire solar cells, to hydrogen generation under illumination of GaN-based structures and from ultrafast response of nanoscale device structures to Power device optimization.
Published: 2017

147. Gate-induced vs. implanted body doping impact on Z2-FET DC operation

Author: Carlos Sampedro, Seong Il Kim, Noel Rodriguez, Sorin Cristoloveanu, Yong Tae Kim, Carlos Navarro, Francisco Gamiz, Luca Donetti, University of Granada [Granada], Department of Electrical Engineering [Korea Advanced Institute of Science and Technology] (KAIST), Korea Advanced Institute of Science and Technology (KAIST), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])
Subjects: 010302 applied physics, Shockley diode, Materials science, business.industry, Doping, Z2-FET, Thyristor, P i n diode, Biasing, 02 engineering and technology, P-I-N diode, 021001 nanoscience & nanotechnology, 01 natural sciences, Sharp switch, 0103 physical sciences, Optoelectronics, FD-SOI, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, SCR, Diode
Abstract: session: Advanced SOI Devices 2; International audience; The impact of the gate-induced virtual and body implanted doping on the DC Z 2 -FET operation is analyzed under several gate-biasing scenarios. Results are compared with related architectures such as the Shockley and P-I-N diodes or the current-gate thyristor. Gate biasing turns out to be essential to observe the characteristic sharp switch of Z 2 -FET device.
Published: 2017

148. Carrier lifetime evaluation in FD-SOI layers

Author: Mukta Singh Parihar, H-J. Park, Kyung Hwa Lee, Sorin Cristoloveanu, Maryline Bawedin, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016)
Subjects: 010302 applied physics, lifetime, Silicon-on-insulator (SOI), Materials science, business.industry, Doping, p-n diode, Silicon on insulator, Biasing, 02 engineering and technology, Carrier lifetime, 021001 nanoscience & nanotechnology, Gate voltage, 01 natural sciences, 0103 physical sciences, electrostatic doping, Optoelectronics, virtual doping, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Diode, p–n diode
Abstract: session B2L-G: Advanced CMOS Characterization and Reliability; International audience; Virtual P-N diodes are emulated in undoped SOI films by biasing the front and back gates such as to induce electrostatically doped regions. The I-V curves are diode-like and can be engineered via gate voltage. We exploit the characteristics of the virtual diode for lifetime characterization, which was considered as a very challenging task in ultrathin SOI films. Two original methods are proposed and compared based on systematic experiments and simulations. It is shown that the carrier lifetime is very short in 7 nm thick SOI layers.
Published: 2017

149. Comparison for 1/ f Noise Characteristics of AlGaN/GaN FinFET and Planar MISHFET

Author: Young-Ho Bae, Sorin Cristoloveanu, Christoforos G. Theodorou, Jung-Hee Lee, Gerard Ghibaudo, Sindhuri Vodapally, Ki-Sik Im, Kyungpook National University [Daegu], Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and Uiduk university, Gyeongju
Subjects: Materials science, G-R noise, 2-D electron gas (2-DEG), Transconductance, Gallium nitride, 02 engineering and technology, 01 natural sciences, Noise (electronics), law.invention, chemistry.chemical_compound, AlGaN/GaN, law, 0103 physical sciences, Wafer, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, Condensed matter physics, business.industry, Transistor, Wide-bandgap semiconductor, Electrical engineering, Heterojunction, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, chemistry, 1/fnoise, fin-shaped field-effect transistor (FinFET), 0210 nano-technology, Fermi gas, business, metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET)
Abstract: DC and 1/ ${f}$ noise performances of the AlGaN/GaN fin-shaped field-effect transistor (FinFET) with fin width of 50 nm were analyzed. The FinFET exhibited approximately six times larger normalized drain current and transconductance, compared to those of the AlGaN/GaN planar metal-insulator-semiconductor heterostructure field-effect-transistor (MISHFET) fabricated on the same wafer. It was also observed that the FinFET exhibited improved noise performance with lower noise magnitude of ${8.5} \times {10}^{-{15}}~\text{A}^{{2}}$ /Hz when compared to the value of ${8.7} \times {10}^{-{14}}\text{A}^{{2}}$ /Hz for the planar MISHFET. An intensive analysis indicated that both devices follow the carrier number fluctuation model, but the FinFET suffers much less charge trapping effect compared to the MISHFET (two orders lower charge trapping was observed). Moreover, the FinFET did not exhibit the Lorentz-like components, which explains that the depleted fin structure effectively prevents the carriers from being trapped into the underlying thick GaN buffer layer. On the other hand, the slope of the noise is 2 irrespective of drain voltage and apparently showed the Lorentz-like components, especially at high drain voltage in MISHFET device. This explains that the carrier trapping/detrapping between the 2-D electron gas channel and the GaN buffer layer is significant in MISHFET.
Published: 2017

150. A-RAM Family Novel Capacitorless 1T-DRAM Cells for 22 nm Node and Beyond

Author: Noel Rodriguez, Sorin Cristoloveanu, and Francisco Gamiz
Subjects: business.industry, Computer science, Node (networking), business, Dram, Computer network
Published: 2017

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