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This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.

International audience; Low-frequency (LF) noise was studied on 28 nm CMOS technology FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). The noise level was observed to be strongly dependent on the combination of the front and back gate biasing voltages. This was explained by the coupling effect of both Si/High-K dielectric and Si/SiO 2 interface noise sources (channel/front oxide and channel/buried oxide), in combination with the variation of the Remote Coulomb scattering coefficient α. From comparison of the experimental and simulation results, it is illustrated that the main reason of this dependence is the distance between the charge distribution centroid and the interfaces, which is also controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient α. A new LF noise model approach is suggested to include the impact of all these parameters, and also allows us to extract the oxide trap density values for both interfaces.

International audience; Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

In this paper, we present TDDB, HCI and BTI reliability characterization of Nfet and Pfet devices issued from FDSOI and bulk 28nm technologies. 28nm FDSOI devices achieve 32% improved performance, 40% reduced power consumption and improved matching. From device level tests, 28nm FDSOI also demonstrates intrinsic reliability behavior similar to 28 bulk devices, giving confidence in the robustness of this technology.

In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.

In this paper the results obtained for a new process flow that integrates a high performance flash cell for automotive application with a state of the art 65nm CMOS have been presented. Despite the several specific process steps introduced for the first time on embedded technologies, the MOS performances have not been impacted by the integration of the Flash cell and the related HV MOS and the results obtained on a 4Mbit Flash array are very promising.

A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (VTP) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced VMIN variations and access time Taa degradation during burn-in operations. The key findings include (a) demonstration of non-normality of VTP shift distribution (b) NBTI contribution to product VMIN drift arises from both mean VTP drift but also from increased VTP dispersion, and (c) VTP shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.

As SRAM integration scheme becomes more and more aggressive in term of development time, supply voltage and geometric dimension, parameter extraction techniques need to be continuously upgraded to ensure the best support for technology development. An innovative approach for write-margin extraction has recently been published at the ISSCC'2006 conference. This approach makes use of test structure giving access to internal node. Here, this approach is evaluated through our 65 nm process and it is shown that the layout and probing of the innovative test structure induces a write delay. As a consequence an adaptation of this innovative methodology is proposed. The new combined solution gives promising results, in terms of accuracy and spread, to better follow the process development of advanced SRAM.

In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% Ion at constant Ioff for NMOS) are demonstrated on samples using LSA. Excellent IonIoff characteristics (Ion = 940 muA/mum Ioff = 200 muA/mum for NMOS and Ion = 390muA/mum Ioff = 50 nA/mum for PMOS at Vdd = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% Icell for the same 1sb) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform

This work highlights the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl mu/m/sup 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/ CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for both nMOS and pMOS. High density critical lithography levels have been exposed with e-beam direct writing thus contributing to the overall cost-effectiveness of the technology.

This work shows the benefits of using plasma nitrided gate oxide which supports the gate leakage requirements for 65 nm platform development. Electrical data shows gate leakage to be reduced by half a decade compared to conventional NO processing with Ioff at 3nA/um, Vdd=0.9 V for 65 nm general purpose requirements. Extensive device characterization of the plasma nitride process is presented where the reduction in gate leakage offers benefits in terms of a 4/spl times/ reduction in static power, a 6% reduction in dynamic power consumption, comparative analog performance and improved reliability.

This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.

A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully working 0.5 /spl mu/m/sup 2/ bit-cells with 240mV of SNM and 35 /spl mu/A of cell current at 1.2V operation were obtained. The GP transistor drive currents of 875 /spl mu/A/ /spl mu/m and 400 /spl mu/A/ /spl mu/m for NMOS and PMOS respectively are obtained at V/sub dd/ = 1V, Ioff = 100nA/um. Using the same CMOS flow, 65nm analog transistor parameters are derived for the first time, showing Vt matching (Avt=2.2mV. /spl mu/m) and analog voltage gain factor (G/sub m//G/sub d/>2000 for L = 10 /spl mu/m) at the leading edge for this process technology. NBTI criteria at 125/spl deg/C for both LP and GP transistors are presented and characterized at overdrive conditions.

The impact of the gate leakage current on long MOS transistor characterization is investigated in this paper. Particularly for first order parameter extraction, a new method is proposed here to rid the gate current on advanced technologies with thin gate oxides. In linear and in strong inversion regimes, we first demonstrate experimentally a 50/50 partition of the gate current between source and drain nodes. TCAD simulations performed for several oxide thicknesses and biases also confirm this partition. The intrinsic channel current of the MOS transistor can then be isolated to extract first order parameters, especially in the case of large area devices which strongly suffer from gate leakage. We show that this I/sub G/ correction permits to extract these parameters in a more consistent way. Finally, we evaluate the extraction error induced by the gate leakage current for varying oxide thicknesses and channel lengths.

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.

We report a detailed experimental and theoretical investigation of the effect of residual strain, and strain relaxation, which manifests itself at the Si/SiO$_{2}$ interfaces in commercial silicon-on-insulator (SOI) wafers. SOI material is made of a single-crystal silicon overlayer (SOL) on top of an insulator (buried SiO$_{2}$ layer) sitting on a handle silicon wafer. Infrared reflectivity spectra show that the buried SiO$_{2}$ layer relaxes continuously when thinning the SOL. At the same time the SOL surface roughness and the linewidth of optical phonons in Si near the Si/SiO$_2$ interface (probed by micro-Raman specroscopy) increase. In the as-delivered wafers, this comes from a slight expansion of Si on both sides of the buried SiO$_{2}$ layer which, conversely, is compressed. Thinning the SOL modifies these initial equilibrium conditions. To get quantitative results, we have modeled all our Raman spectra using a theory of inhomogeneous shift and broadening for optical phonons, which takes into account the phonon interaction with the static strain fluctuations. From the variation of linewidth versus interface distance, we have found that the mean squared strain continues to relax in the bulk of the wafer through a depth on the order of several $\mu m$. We also show that the SOL surface roughness is related to strain fluctuations near the Si/SiO$_2$ interfaces., Comment: 28 pages, 11 figure, to be published in Phys. Rev. B (Nov 15 2000)

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In this paper, we demonstrate for the first time full integration of highly performant NMOS and PMOS silicon-on-nothing (SON) devices into circuits. We demonstrated fully functional SRAMs cells with very good yield, showing static noise margin (SNM) of 175mV and write margin (WM, stable "read 0") above 500mV. The optimized SON devices show performance for NMOS and for PMOS that is among the best published data (with drive current up to 1100/350/spl mu/A//spl mu/m for 138/20nA//spl mu/m I/sub off/ for NMOS and PMOS devices respectively @V/sub dd/=1.2V, I/sub ox/=16A). Finally, we present also the implementation of the SON process into a new "localized SOI" architecture on bulk. This new and simplified SON process is also demonstrated by fully operational SRAM cells.

This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of “effective body factor” and lesser mobility degradation with increase of the positive back-gate bias.

For the first time, the thermal stability of a 28nm FDSOI CMOS technology is evaluated with yield measurements (5Mbit dense SRAM and 1 Million Flip- flops). It is shown that 500°C 2h thermal budget can be applied on a digital 28nm circuit including State-Of- The-Art Cu/ULK BEOL without yield nor reliability degradation. These results pave the way to the introduction of BEOL between tiers in 3D sequential integration while the thermal budget allowed for the top tier is sufficient to lead to high performance device.