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In this report, the impact of atomic-layer-deposition-derived different laminated gate stacks on the interface chemistry and electrical performance of Yb2O3/GaSb metal-oxide-semiconductor (MOS) cap...

It is a well-known fact that the gate stacking is used to improve the electrostatic behavior of Si0.5Ge0.5 Junctionless Gate-All-Around (JL-GAA) MOSFETs. In gate stacking, the high-k oxide material is stacked with an interfacial silicon dioxide (SiO2) layer. In the recent past, oxide engineering techniques have been investigated as an alternative approach to improve the driving current of JL-GAA MOSFETs. In this paper, oxide engineering has been applied to improve the electrostatic performance of JL-GAA MOSFETs. The comparative study of the three device structures, namely Double Hetero gate oxide (DHGO), Triple Hetero gate oxide (THGO), and Quadruple Hetero gate oxide (QHGO) has been performed for various performance parameters. The objective behind this investigation is to highlight a significant enhancement in the driving current of JL-GAA MOSFETs. The comprehensive analysis shows that the DHGO device offers the highest ON-current, lowest subthreshold swing, and DIBL. Hence, the proposed device will be a perfect match for low power and high-speed communication systems.

This work presents the analog and RF performance evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have been compared with conventional FinFET and GAA FinFET. It has been observed that in comparison to conventional FinFET, leakage current (Ioff) reduces by almost thirty times for the GS-GAA FinFET configuration. Thus, revamping the threshold voltage (Vth), switching ratio (Ion/Ioff), and subthreshold slope (SS) of the proposed device. Also, major analog parameters like transconductance (gm), transconductance generation factor (TGF) enhances considerably with early voltage (VEA) and intrinsic gain (Av) increased by over two times in magnitude for the GS-GAA FinFET configuration. Furthermore, several important RF parameters have been explored, and the outcome of the study is that the GS-GAA FinFET configuration shows superior RF performance. In GS-GAA FinFET configuration, the gain frequency product (GFP) and gain transconductance frequency product (GTFP) amplified by over two times in magnitude with minimal decrease in the cut-off frequency (fT) and maximum oscillation frequency (fmax). Thus, the proposed GS-GAA FinFET device can be looked upon as an appealing option for high-frequency analog/RF applications.

In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (ID), transconductance (gm), transconductance generation factor (TGF), intrinsic gain, output resistance (rout), cut-off frequency, maximum frequency of oscillation (fmax) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.

Today, Fin shaped Field Effect Transistors (FinFETs) are the foundation of the sub-nanometer technology node. The semiconductor industry endorses it in low-power (LP) and high-performance (HP) applications due to its better electrostatic control and exceptional scalability. In this paper, the structure of an inverted funnel-shaped FinFET device with a high-k stacked gate has been optimized using integrated Artificial Neural Network (ANN) and genetic algorithm (GA) approach. The comparative analysis of rectangular FinFET, trapezoidal FinFET and proposed novel shaped FinFET has also been explored. The electrical and analog performance parameters of the novel device present better performance results with respect to the other two transistors. In ANN training, the three datasets have been created by varying the metrics such as equivalent oxide thickness (EOT) and dielectric constant (k) of novel shaped FinFET device in Technology computeraided design simulator (TCAD). The amalgamation technique of ANN and GA optimization provides diminished Subthreshold Swing (SS), reduced off-current (IOFF), enhanced on-current (ION) and improved current ratio (ION/IOFF) corresponding to the optimal value of EOT and k. The new structure designed and simulated with the optimal amount of EOT and k results in outstanding performance parameters. The device metrics values, SS of 62.1 mV/dec, IOFF of 6.56×10-11, ION of 3.938×10-5 and ION/IOFF of 5.95×105 indicate that optimized device has suppressed Short Channel Effects (SCEs). The average deviatION of 3.48% between the value of ANN-GA optimized results obtained through MATLAB and TCAD simulated performance parameters justify the effectiveness of proposed FinFET.

We demonstrate novel analysis on electrical characteristics of ferroelectric-gate field effect transistor (FeFET), especially reverse DIBL (RDIBL) and negative differential resistance (NDR) phenomena through measurements of fabricated FeFETs and technology computer-aided design (TCAD) simulations. The FeFETs are embodied by extracting the ferroelectric properties using metal-ferroelectric-metal (MFM) capacitors and applying it to the gate stack of n-type FeFETs. Then, the device and the model parameters of the FeFETs are calibrated by matching TCAD simulation results to measured electrical characteristics. By the TCAD simulations which reflect the Preisach model considering multi-domain ferroelectric characteristics, it is revealed that RDIBL and NDR result from the local conduction band energy rising at the drain-side with drain voltage increasing. Furthermore, it is found that gate-induced drain leakage (GIDL) accelerates RDIBL with the help of the injection of the generated holes by GIDL in the floating body of FeFETs.

Two-dimensional tungsten disulfide (WS2) is one of the potential channel materials in future nanoelectronics. In this paper, an atomic layer deposition (ALD) process based on low-temperature (low-T...

We report the investigation of BiFeO3 and Y2O3 gate stack for the metal-ferroelectric-insulator-field-effect-transistors (MFIS-FET) for nonvolatile memory applications deposited by sputtering. X-Ra...

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage ( ${V}_{\text {TH}}$ ) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$ ). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT.

In this work, we have demonstrated normally-off $\beta {-}\text {Ga}_{{2}}\text {O}_{{3}}$ metal-oxide-semiconductor field-effect transistor (MOSFET) with the ferroelectric charge storage gate stack structure. Saturation currents of 18.3 and 16.0 mA/mm were achieved in Depletion (D–) and Enhancement (E–) mode device, respectively, which shows negligible current reduction. Steep subthreshold swing (SS) of 72 mV/dec and breakdown voltage of 670 V were also obtained in the E-mode MOSFET. Furthermore, after gate stess test of 10 V for 105 s was performed, the threshold voltage $({V}_{\textit {TH}})$ shift was 26.5 %. These electrical characteristics of the E-mode $\beta {-}\text {Ga}_{{2}}\text {O}_{{3}}$ MOSFET shows the great potential for future power switch application.

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the ID-VG characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-linear behavior of the current in the log scale, which is not observed in conventional devices. Such steepening in the weak inversion regime leads to a significant increase in the achievable current at a constant VDD. At LG = 50 nm, our transistors show a larger than 2X increase in the ON current.

For the development of reliable vertical GaN transistors, a detailed analysis of the robustness of the gate stack is necessary, as a function of the process parameters and material properties. To this aim, we report a detailed analysis of breakdown performance of planar GaN-on-Si MOS capacitors. The analysis is carried out on capacitors processed on different GaN bulk doping (6E18 Si/cc, 6E17 Si/cc and 2.5E18 Mg/cc, p-type), different structures (planar, trench-like) and different geometries (area, perimeter and shape). We demonstrate that (i) capacitors on p-GaN have better breakdown performance; (ii) the presence of a trench structure significantly reduces breakdown capabilities; (iii) breakdown voltage is dependent on area, with a decreasing robustness for increasing dimensions; (iv) breakdown voltage is independent of shape (rectangular, circular). TCAD simulations, in agreement with the measurements, illustrate the electric field distribution near breakdown and clarify the results obtained experimentally., ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][Research for GaN technologies, devices, packages and applications to address the challenges of the future GaN roadmap][UltimateGaN][826392]

This paper examines the DC performance of Dual-Gate MISHEMT with different substrate material such as sapphire, silicon carbide SiC, and silicon. The performance parameters evaluated are th...

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stackgraded channel double gate-Junctionless (TMGS-GCDGJL) strained-Si (s-Si) MOSFET with fixed charge density is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of transconductance-generationfactor (TGF), early voltage, voltage gain, unity-powergain frequency ( f max ), unity-current-gain frequency ( f t ), and gain-transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDGJL s-Si MOSFET has superior analog/RF performance compared to gate stack-graded channel double gatejunctionless (GS-GCDG-JL) s-Si device. However, the proposed MOSFET has less transconductance and less output conductance when compared with the GS-GCDGJL s-Si device in above threshold region, and reverse trend follows in sub-threshold region.

The influence of the processing conditions on the interfacial and electrical properties of the high-k/SiGe gate stacks based on ozone oxidation is investigated. Detailed analyses of the relationship between the interface chemical structures and the corresponding electrical properties, as a function of oxidation time, reveal that the change in the distribution of the Ge atoms is the dominant factor to achieve superior electrical properties. In addition, the increase in the ratio of Si 4+ to Si 3+ of the oxide interlayer can help decrease the interface trap densities. These results provide us an important passivation route for the high-k/SiGe interface based on ozone oxidation, which is to explore an oxidation method that can realize an ultrathin interlayer including as much Si 4+ component as possible over a long oxidation time.

A border trap (BT) evaluation method was established for SiO2/GeO2/Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiO2/GeO2/Ge gate stacks were fabricated by post-passivation thermal oxidation. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from GeO2/Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and the density (Nbt) was in the range of 1017-1018 cm−3. For n-type MOSCAPs, BTs at the position range of 2.8-3.4 nm from the GeO2/Ge interface were measured. The energy of these BTs were distributed in a relatively wide range near to the conduction band edge of Ge, and the Nbt was approximately one order of magnitude higher than those for p-MOSCAPs. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge.

In this paper, for the first time, we have experimentally demonstrated enhancement mode (e-mode) AlGaN/GaN high-electron-mobility transistor (HEMT) operation by integrating p-type high- $\kappa {\mathrm {Al}}_{x}{\mathrm {Ti}}_{1-x}$ O based gate stack. Concentration of Al in Al-Ti-O system was found to be a tuning parameter for the threshold voltage of GaN HEMTs. The high- $\kappa $ properties of ${\mathrm {Al}}_{x}{\mathrm {Ti}}_{1-x}$ O as a function of Al % are studied. Superiority of AlTiO over other p-oxides such as CuO and NiO x is proven statistically. Using the high- $\kappa $ and p-type AlTiO, in conjunction with a thinner AlGaN barrier under gate, 600-V e-mode GaN HEMTs are demonstrated with superior ON-state performance ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}~\sim ~400$ mA/mm and $\text{R}_{ \mathrm{\scriptscriptstyle ON}} ={8.9}\,\,\Omega $ -mm) and gate control over channel ( $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}} = {10}^{{7}}$ , SS = 73 mV/dec, and gate leakage

Electrical properties of Y2O3/SiGe metal-oxide-semiconductor (MOS) capacitors with Al, Au, W and TiN gate electrodes have been evaluated in order to study the impact of the metal gate electrodes on Y2O3/SiGe interface properties. It is found that MOS capacitors with TiN gate electrodes can provide better Y2O3/SiGe MOS interfaces than those with Al, Au or and W gate stacks after post metallization annealing (PMA) at each optimized temperature. The physical origins of interface trap density (Dit) reduction are examined from the viewpoint of the composition and the quality of interfacial layers (ILs).

The evolution of traditional field effect transistor from planar to three-dimensional (3-D) device structure has led to higher package density and high current drive. However, due to continuous sca...

We investigate the impact of gate-stack engineering using W/ZrO2/Al2O3 on the performance of planar-type InGaAs tunneling field-effect transistors (TFETs). It is shown that 1-nm-thick capacitance equivalent thickness (CET) with low leakage current is achieved by using ZrO2 with the dielectric constant of around 40 on In0.53Ga0.47As. On the other hand, the reduction of Dit by insertion of ALD 1–5 cycle Al2O3 interfacial layers (ILs) is found to be mandatory for obtaining TFET performance enhancement. The planar-type InGaAs TFETs using the ZrO2/Al2O3 IL gate-stack with CET of 1 nm exhibit the minimum subthreshold swing (S. $\text{S}_{\min }$ ) of 55 mV/dec and ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $0.88~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, and ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ ). Furthermore, the ZrO2/Al2O3 IL gate-stack is applied to the optimized In0.75Ga0.25As quantum well (QW) channel TFETs. The low S. $\text{S}_{\min }$ of 50 mV/dec and high ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of $1.2~\mu \text{A}/\mu \text{m}$ ( ${V}_{\text {G}}$ – ${V}_{ \mathrm{\scriptscriptstyle OFF}}= \text {0.5}$ V, ${V}_{\text {D}}= \text {0.2}$ V, ${I}_{ \mathrm{\scriptscriptstyle OFF}}= \text {10}$ pA/ $\mu \text{m}$ , and CET = 1.1 nm) are demonstrated by combing the present ZrO2-based gate-stack with the optimum In0.75Ga0.25As QW channel structure.

The main purpose of this paper is to achieve as low as possible leakage current ( $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths $\text{L}_{\mathrm {eff}}$ , gate stacks, gate contact materials, and gate-sidewall spacers ( $\text{L}_{\mathrm {sp}}$ ). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length $\text{L}_{\mathrm {sp}}$ and $\text{L}_{\mathrm {HK}}$ is investigated to get low leakage current keeping $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ as high as possible. Moreover, the effective channel length in subthreshold conduction ( $\text{L}_{\mathrm {eff}}$ ) is maintained greater than the gate length ( $\text{L}_{\mathrm {g}}$ ) and the threshold voltage ( $\text{V}_{\mathrm {th}}$ ) is adjusted by the proper metal gate work function. The performance of the proposed n- and p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ is 17 pA/ $\mu $ m for n-FinFET and 14.7 pA/ $\mu \text{m}$ for p-FinFET which are the lowest leakage currents found in recent publications. The achieved $\text{I}_{\mathrm { \mathrm{\scriptscriptstyle ON}}}/\text{I}_{\mathrm { \mathrm{\scriptscriptstyle OFF}}}$ ratio for both proposed devices is found to be $12.3 \times 10^{6}$ and $11 \times 10^{6}$ , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of $\text{L}_{\mathrm {sp}}=10$ nm and $\text{L}_{\mathrm {HK}}= 5$ nm. In addition, the short channel effects variations with $\text{L}_{\mathrm {HK}}$ have been investigated.

In this paper, we designed and analyzed the performance of FinFET using various hetero dielectric structures. i.e., using SiO 2 & HfO 2 , SiO 2 & $Si_{3}N_{4}$ and HfO 2 & $Si_{3}N_{4}$ to get lower leakage current and higher I on /I off ratio than conventional FinFETs. Among the all configurations HfO 2 & $Si_{3}N_{4}$ gives ameliorated performance in terms of $I_{on},I_{off}$, SS, and DIBL. In all structures high-k dielectric materials are used in top oxide to increase gate control and low-k dielectric materials are used near silicon for better matching of lattice constant with silicon dioxide. Drift-diffusion model and quantum models are used in three dimensional (3D) simulation using Visual TCAD.

The Front Opening Unified Pod (FOUP) is used to protect wafers from the Fab environment when they are not being processed. During Gate stack etch, a process known to be a potential source of etch residuals, wafers are separated in a different FOUP to avoid cross contamination. We show that the FOUP in which the wafers are placed can itself be a source of contamination. The contamination is found through inspection and it can also be shown to have a detrimental impact on product yield. We argue that outgassing of the FOUP is the source of the contamination and that an established cleaning process is insufficient to completely remove the contamination. The issue is eliminated by a change of type of FOUP used to contain the wafers.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to the adoption of high-κ dielectric HfO2 in the gate stack in 2008, which remains as the material of choice to date. Here, we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors and scaled down to ~ 20 Å, the same gate oxide thickness required for high performance transistors. The overall EOT (equivalent oxide thickness) in metal-oxide-semiconductor capacitors is equivalent to ~ 6.5 Å effective SiO2 thickness, which is, counterintuitively, even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. Therefore, our work demonstrates that HfO2-ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the 2 nm thickness regime, provides a new path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

Due to the absence of dangling bonds, the integration of ultra-thin dielectric on 2D semiconductors has become a huge challenge, and its reliability research has been blank before. For the first time, we report the high $-\mathcal{K}$ dielectric reliability on Mos2. By PTCDA crystal as interface layer, we demonstrated excellent reliability of HfO 2 /PTCDA gate stack, including EBD over 8.9 MV/cm, $\mathrm{E}_{\text{BD}}\ ^{10\text{yrs}}$ over 6.5 MV/cm and ultra-low BD rate, all of which show better reliability than HfO 2 /Si.

Scaling from FinFETs to horizontal and vertical single or stacked nanowires and nanosheets directly impacts the low frequency noise performance. The processing choice (e.g. gate stack, junction architecture, metal stack) also plays an important role. The noise power spectral density (PSD) of advanced Si, Ge and III-V devices is studied and compared with each other.

Complementary metal oxide semiconductor (CMOS) device has been successfully evolved with innovative techniques, e.g., stress engineering, high-klmetal-gate, three-dimensional device structure, for the past a few decades. As a new pathway, the adoption of ferroelectric materials in gate stack of CMOS device has been received lots of attention. In this work, the device design guidelines for ferroelectric-gated CMOS device are to be discussed.

In this paper, the thermal oxidation of substrate in SiC gate stack formation is engineered by employing atomic layer deposition of gate oxide and controlling post-deposition annealing (PDA). We find that the interface states density $(\mathrm{D}_{\text{it}})$ in the gate stacks can be substantially lowered by reducing the thickness of thermally formed $\text{SiO}_{2}$ : between deposited $\mathrm{A}1z\mathrm{O}_{3}$ and SiC in PDA. And, it is also reduced by suppressing the thermal oxidation of SiC using deposited $\text{SiO}_{2}$ and low temperature PDA. These results provide new insights into improving the interface performance of SiC MOS devices.

Gate stack process (pre-clean, IL, IL/HK interface, HK, post-HK Nitridation) impact on gate leakage, SILC and PBTI is analyzed. IL and HK thickness, channel/IL and IL/HK energy-barrier offsets impact on gate leakage and SILC response from generated bulk traps inside IL and HK is quantified. Time kinetics of generated IL and HK bulk traps for SILC, and IL/HK interface traps for PBTI are simulated by a generic Reaction-Diffusion-Drift (RDD) framework. Model is validated using measurements from differently processed HKMG stacks.

We have examined the slow electron and hole trap density at TiN/Y 2 O 3 /SiGe MOS interfaces. The effect of trimethylaluminum (TMA) pre-treatment before Y 2 O 3 deposition on the slow trap density has been studied. Also, the dependency of the slow trap density on Ge contents of SiGe has been systematically evaluated and the influence of the composition of interfacial layers (ILs) is examined. It is found that 10-cycle TMA treatment is effective to suppress the formation of slow traps attributable to Ge-O bonds in ILs. On the other hand, the density of electron and hole slow traps in the Y 2 O 3 /SiGe MOS interfaces increases with higher Ge content of SiGe, which can be explained by the formation of vacancy-related defects due to incorporation of Ge-O bonds into SiO 2 IL networks.

In this paper, we have developed a temperature-dependent analytical model to study the effectiveness of DMG-HK Trapezoidal FinFET for high temperature operation. It is demonstrated that the proposed device with incorporation of dual material gate and high K layer leads to less degradation in device performance at high temperature as compared to conventional devices. The improvement is seen in terms of reduced threshold voltage sensitivity and DIBL with change in temperature along with suppressed hot carrier effects and improved subthreshold slope.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al 2 O 3 /UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.

This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge n/pFETs. Through the improvement of those unit modules, the electrical performance and reliability of Ge FinFET and gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for the realization of high performance and reliable Ge n/pFETs will be discussed.

In this paper, investigation of an improved structure of a Junctionless Accumulation Mode (JLAM) MOSFET is done. Using the advantages of both the Gate Stack Engineering and dual material engineering, a Dual-Material Double Gate Junctionless Accumulation Mode Cylindrical Gate All Around (DMDG-JLAM-CGAA) MOSFET with a high-k gate stack, a novel structure is proposed. The impact of dual gate and stacked oxide is investigated. The simulation of this device is performed on ATLAS 3-D device simulator. The analytical study of this device has also been done on MATHCAD and the results are verified with the results that are obtained after simulation. Various electrical parameters of this device have been obtained. This device exhibits an excellent subthreshold swing of 67 mV/ decade.