Search

The effective passivation of germanium surfaces and interfaces has been claimed to be the key to a substantial progress in developing Ge-based microelectronic devices. This paper compares the currently most promising passivation routes, i.e. oxidation and sulfidation, focusing on the underlying atomic scale processes and highlighting similarities and discrepancies between both approaches. The effect of oxidation and sulfidation on electrically active defects is addressed, and the chemical and structural properties of the passivated surfaces are described in detail.

As post-Si era for digital device is incipient, In0.53Ga0.47As is good candidate among n-type active channels with high electron mobility but - unlike Si - it lacks a well-established technology for dielectric gating which may bear aggressive device scaling. Here we propose a viable route for the atomic layer deposition (ALD) of high-κ dielectrics taking advantage from the well-known self-cleaning effect of the trimethylaluminum (TMA) precursor on the III-V compound surfaces. In this respect, the incorporation of Al2O3 cycles both as pre-conditioning surface treatment and inside the ALD growth of a MO2 host matrix (M=Zr, Hf) is here investigated. Al:MO2/In0.53Ga0.47As heterojunctions have been scrutinized by in situ spectroscopic ellipsometry and ex situ chemical depth-profiling analysis which validate a good physical quality of the oxide and elucidate the effect of the pre-conditioning cycles at the interface level. The resulting MOS capacitors have been characterized by means of multifrequency capacitance-voltage measurements and conductance analysis therein yielding a permittivity of 19{plus minus}1 both for Al:HfO2 and Al:ZrO2 and similar electrical quality of the interfaces. On the other hand, Al:HfO2 appears to be electrically more robust against leakage and endowed with a lower frequency dispersion in accumulation.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

Deep levels present in MOS capacitors, fabricated on GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). The gate dielectric is composed of 9 nm Al2O3 deposited by Molecular Beam Epitaxy (MBE) on two different types of Interfacial Oxide Layers (IOL). It is shown that the density of interface traps (Dit) near the valence band edge is significantly reduced for GeSn epilayers compared with the same gate stack on a Ge cap. At the same time, several deep-level traps in the germanium depletion region have been observed, whereof the origin is discussed.

To design a high performance BaTiO3 (BTO)-integrated Si modulator, understanding how BTO domain orientations influence its electro-optical (EO) properties is crucial. The 100-nm-thick BTO films with c-oriented and a-oriented domains are obtained by exploiting various thickness of SrTiO3 buffer layers grown on Si(001) substrates. Then, the electro-optical behavior for 2 differently oriented samples is analyzed using spectroscopic ellipsometry.

This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs/n-Si, and n-InAs/n-Ge; and that 2) a TiSi x /12nm Si:P/n-Ge contact with favorable band alignment between Si:P/n-Ge approaches low effective contact resistivity of 1.4×10−8 Ω cm2, close to a record-low value for n-Ge contacts.

In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.

We will present our work on epitaxially grown III-V on silicon DFB laser arrays, including results of pure InP-based lasers emitting around 900nm and InGaAs-on-InP lasers emitting around 1300nm.

We report In 0.53 GaAs-channel gate-all-around FETs with channel width down to 7nm and L g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g m by 25% compared to InAs S/D. A g m of 1310 µS/µm with an SS sat of 82mV/dec is achieved for an L g =46nm device. At this L g , a record I on above 200µA/µm is obtained at I off of 100nA/µm and V ds =0.5V on a 300mm Si platform.

In the paper, we review our work on heterogeneous integration of InP photonic devices on silicon. We elaborate on two integration technologies that have been widely explored in the Photonics Research group, i.e. the relatively mature adhesive bonding based integration scheme and a newly demonstrated buffer-less epitaxial growth approach. Based on these techniques, we describe a broad range of photonic devices including mode-locked lasers, high speed directly modulated distributed feedback lasers, electro-absorption modulators, photodetectors, super-luminescent light emitting diodes, etc.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

Si CMOS technology is currently changing with the introduction of strain and new materials (Ge, III/V) to increase carrier mobility and devicesaturationcurrent.Recently,excellentGe-basedpMOSchannel performance has been demonstrated with intrinsic hole mobilities far above the universal Si mobility curve which is reflected in a clear increase in device current. 1‐4 However, while relaxed Ge exhibits significantly higher intrinsic hole mobilities than relaxed Si, it does not out-perform the current “state of the art” uniaxially strained Si pMOS devices. For Ge channel pMOS devices, compressive uni-axial and/or bi-axial strain implementation seems essential to substantially increase carriers velocity and to outperform current Si- and Si1-yGeybased devices, which is confirmed by theoretical calculations of the carrier mobility and device current. 5‐7 Ge1-xSnx offers schemes to implement the required strain types and levels in the active part of the device. Recent breakthroughs in low temperature hetero-epitaxial Ge1-xSnx and SiyGe1-x-ySnx growth on Si substrates as e.g. reported in references 8‐14 have triggered the assessment of this material system for such electrical device applications. In this contribution we discuss the use of Ge1-xSnx for future (electrical) device applications and its fabrication with a special attention on recent achievements from imec.

Integrating high electron mobility III–V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III–V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III–V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III–V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III–V materials, a concept has been developed comprising the deposition in “v-grooves” with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these “v-grooves”, the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the “v-grooved” trench. This approach offers a promising m...

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

Germanium is considered to be a potential semiconductor to replace silicon in future high-performance microelectronic devices. Yet, when compared to Si, very little is known about the surface chemistry of Ge surfaces. In this article, we report on the oxygen adsorption on Ge(100)-(2 × 1) surfaces and the related changes in the density of surface states. In particular, the adsorption geometry is examined both in reciprocal- and real-space using reflection high-energy electron diffraction and scanning tunneling microscopy, respectively. Our findings reveal that the insertion of oxygen atoms into the Ge backbonds is not favored under the investigated reaction conditions, i.e., at a moderate O2 exposure. The O2-exposed surface exhibits a local (1 × 1) surface reconstruction, which implies that dimer bonds are destroyed upon oxygen adsorption. Surface states related to Ge dangling surface bonds present on the clean Ge(100) surface are found to be passivated. In addition, a high density of expelled substrate at...

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel for quantum well devices. In this work we first investigated building blocks such as passivation and contact resistances on both GaSb and InAs epilayer in order to define the optimal heterostructure for the quantum well device. In a second part, we focused on the growth studies of the complex heterostructure made with "6.1" semiconductors as well as the importance of the interface engineering with TEM. Finally, the properties of the optimized quantum well stack have been studied by means of photoluminescence and high resolution X-ray diffraction.

Three advanced architectures for ultimate progress in Ge p-Metal Oxide Semiconductor Field Effect Transistors are discussed in this paper. Different routes for stress implementations in Ge channels, either biaxial or uniaxial, are proposed by advanced selective Chemical Vapor Deposition techniques. Selective SiGe Strained Relaxed Buffer growth in Shallow Trench Isolation is first discussed to implement biaxial compressive strained Ge Quantum Wells on top of it. Next, innovative GeSn chemical vapor deposition technique is described in order to build either uniaxial strained Ge channel with GeSn Source/Drain stressors or compressively biaxial strained GeSn Quantum Well channels on Ge buffer layers.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in-situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers.

The integration of higher carrier mobility materials to increase drive current capability in the next CMOS generations is required for device scaling. But a fundamental issue regarding the introduction of high-mobility III–V in CMOS is the electrical passivation of the interface with the high-κ gate dielectric. In this work, we show that in situ H2S surface treatment on GaAs(001) leads to a stable and reorganized oxide/III–V interface. The exposition of the GaAs surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. Finally, MOS capacitors are fabricated to extract interface state density over the band gap. These results highlight a promising re-interest in chalcogenide passivation of III–V surfaces for CMOS applications.

From electron internal photoemission and photoconductivity measurements at the (100)GaSb/Al"2O"3 interface, the top of the GaSb valence band is found to be 3.05+/-0.10eV below the bottom of the Al"2O"3 conduction band. This interface band alignment corresponds to conduction and valence band offsets of 2.3+/-0.10eV and 3.05+/-0.15eV, respectively, indicating that the valence band in GaSb lies energetically well above the valence band of In"xGa"1"-"xAs (0=

A fundamental issue regarding the introduction of high-mobility Ge channels in CMOS circuits is the electrical passivation of the interface with the high-k gate dielectric. In this paper, we investigate the passivation of p-Ge(001) using molecular H"2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses. MOS capacitors are fabricated to extract interface state density, and finally we demonstrate the efficiency of the passivation scheme using a combination with an ultra thin Al interlayer.

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

Si and Se implantations have been systematically investigated in In"0"."5"3Ga"0"."4"7As. Different implant doses and various activation anneals with temperatures up to 700^oC have been examined. Raising Si implant dose from 1x10^1^4 to 1x10^1^5cm^-^2 was found to increase the active doping concentration by about a factor of two. As confirmed by Transmission Electron Microscopy (TEM) and electrical measurements, the rest of the implanted Si ions remain as defects in the crystal and degrade the mobility. It was also confirmed from Secondary Ion Mass Spectrometry (SIMS) that the Si diffusivity in InGaAs is negligible up to 700^oC implant activation anneal making Si a suitable option for the formation of shallow junctions in InGaAs. The activation efficiency, sheet resistance, carrier density and mobility data of 25keV Se and Si implanted InGaAs layers are also presented under various activation anneal temperatures.

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices.

© 2018 Author(s). In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC- 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. ispartof: JOURNAL OF APPLIED PHYSICS vol:124 issue:16 status: published

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nuc...

We present in this paper the use of Gas Source Molecular Beam Epitaxy for the large-scale growth of transition metal dichalcogenides. Fiber-textured MoS2 co-deposited thin films (down to 1 MLs) are grown on commercially 200 mm wafer size templates where MX2 crystalline layers are achieved at temperatures ranging from RT to 550 °C. Raman Spectroscopy and photoluminescence measurements along with X-Ray Photoelectron Spectroscopy show that a low growth rate is essential for complete Mo sulfurization during MoS2 co-deposition. Finally, cross-section Transmission Electron Microscopy investigations are discussed to highlight the influence of SiO2 and Al2O3 used surfaces on MoS2 deposition.

The use of Ge and III/V materials for future CMOS applications is investigated. Passivation of the Ge surface can be obtained by either GeO2 or a thin Si layer. Short channel Ge pMOS devices with low EOT are fabricated. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are investigated and the performance of inversion channel MOSFET's on In0.53Ga0.47As with ALD Al2O3 is discussed.

Different selective epitaxial growth processes to deposit buried SiGe channels with Ge contents in the range of 25-55% and with an ultra thin Si capping layer have been successfully developed and implemented in pMOS device flows. Relatively low deposition temperatures assure the absence of SiGe islands and enable high quality strained SiGe layers. The required low growth temperature governed the choice of precursors used. In this contribution we review in detail the developed SiGe processes together with the deposition of the ultra thin Si cap layer. Electrical data obtained on the devices with incorporated Si0.75Ge0.25 and Si0.55Ge0.45 buried channels are presented as well.

We will shortly review the basic physics of charge carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high temperature CV-measurements are necessary for GaAs MOS characterization. The mid-gap trapping states in GaAs have characteristic emission times of the order of 1000 seconds, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures fasten these emission times, which makes measurements of the mid-gap traps possible with standard CV-measurements. CV-characterizations of GaAs/Al2O3, GaAs/Gd2O3, GaAs/HfO2 and In0.15Ga0.85As/Al2O3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to mid-gap energies, an electron trap peak close to mid-gap energies and an electron trap peak close to the conduction band.

The energy band alignment between Ge, HfO 2 and Al 2 O 3 was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO 2 , Ge 3 N 4 , Si/SiO x ). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO 2 interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO 2 growth using H 2 O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO 2 and Al 2 O 3 deposition suppresses the formation of the narrow-gap Ge oxide.

In the paper, we elaborate our recent work on both monolithic (epitaxial growth) and heterogeneous (BCB bonding) integration techniques that enable integration of various IIIV lasers on silicon.

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

In this paper we show how new materials such as InP epitaxially grown on silicon, graphene and ferroelectric materials with strong electro-optic coefficient can be integrated with silicon waveguides and enhance the functionality of the silicon photonics platform.

Trap spectroscopy by charge injection and sensing method was applied to the In0.53Ga0.47As-Al2O3 system, yielding the spatial and energetic distribution of the traps inside the Al2O3 layer. The trap density inside the atomic-layer-deposited (ALD) Al2O3 layer was found to be significantly reduced by (NH4)2S treatment of the InGaAs surface prior to the Al2O3 deposition. Indium concentration inside the Al2O3 layer was found to be reduced once the InGaAs surface is (NH4)2S treated prior to the Al2O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH4)2S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al2O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs.

Monolithically integrating BaTiO3 on silicon substrates has attracted attention because of the wide spectrum of potential novel applications ranging from electronics to photonics. For optimal device performance, it is important to control the BaTiO3 domain orientation during thin film preparation. Here, we use molecular beam epitaxy to prepare crystalline BaTiO3 on Si(001) substrates using a SrTiO3 buffer layer. A systematic investigation is performed to understand how to control the BaTiO3 domain orientation through the thickness engineering of the SrTiO3 buffer layer and the BaTiO3 layer itself. This provides different possibilities for obtaining a given BaTiO3 orientation as desired for a specific device application.

Optical interconnects require efficient and flexible optical sources. This paper presents results on two technology platforms being developed for realizing these. Integration using wafer bonding technologies is well established now and the focus is on new device types including tunable lasers, multi-wavelength lasers and switching. As an alternative, we also started work on monolithic integration using heteroepitaxy directly on silicon. We here report recent results on low threshold nanowire lasers.

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, L g of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Band-to-band tunneling (BTBT) in bulk group IV and III-V semiconductors is well known [1-2], but BTBT to confined layers is more difficult to calibrate experimentally. The latter occurs in most tunnel-FETs (TFET) and in particular in the promising line-TFETs [3,4]. It is predicted that field-induced quantum confinement (FIQC) and changing density of states near the semiconductor/oxide interface negatively impact the BTBT generation rate [5]. In order to gain insight while avoiding complicated TFET fabrication and analysis, we propose and demonstrate the BTBT MOS-capacitor (MOS-CAP) to characterize the onset and rate of BTBT perpendicular to the gate.

First-principles investigations are used to study the formation of defects in III-V fins grown using the aspect ratio trapping technique. We show that, during the growth of the III-V, the formation of intermediate chemical states with the precursors leads to the creation of in-diffused Mg/Zn and Al 2 O 3 sub-oxide. Our prediction is consistent with the experimental observations. These defect formations could be at the origin of the degradation of the electrical reliability of III-V fin-shaped field-effect transistors and the cause of the increasing difficulties met in the fabrication of III-V fin.

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane’s formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several pþ/intrinsic/nþ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET. ispartof: Journal of Applied Physics vol:115 issue:18 pages:1-9 status: published

This paper gives an overview of measurement techniques to assess border traps in high-k gate dielectrics deposited on high-mobility channel materials, like Ge and InGaAs. A short description of the measurement principle and bulk oxide trap analysis will be provided for three methods, namely, low-frequency (1/f) noise, Deep-Level Transient Spectroscopy and AC transconductance dispersion. Practical application is illustrated either on metal-oxide-semiconductor capacitors or transistors, depending on the technique.

Silicon photonics holds the promise of converging electronics and photonics. The key component, a low-cost high-performance laser, is still missing however within this platform. Although novel solutions have been proposed to increase the light emission directly from silicon (or Ge), compared with their III-V counterparts, these solutions are still in their infancy. Recently, the epitaxial growth of III-Vs on silicon regained a wide interest. III-V nanowire growth has been widely investigated. However, most of the III-V nanowire lasers on silicon require a complex cleaving and transfer process, which make these devices not suitable for dense integration. In addition, the large cavity dimensions along the nanowire axis (several microns) hinder dense integration. Here, we present the first room-temperature operation of an ultra-short InP nanowire laser that is epitaxially grown on an exactly [001] oriented silicon substrate. The sub-micron sized laser cavity largely enhances the interaction of the lasing mode with the gain medium, and a large spontaneous emission factor has been obtained.

In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship < 100 > BTO(001)//< 110 > Ge(001) with the substrate, describing a 45 degrees lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I-(001)/I-(002), I-(101)/I-(002), and I-(111)/I-(002) derived from omega - 2 theta scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. Published by AIP Publishing.