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Using micro-Raman and photoluminescence (PL) techniques, the channel temperature profile is probed in AlxGa1-xN/GaN high electron mobility transistors (HEMTs) fabricated on a 200 mm diameter Si(111) substrate. In particular, RuOx-based gate is used due to the semitransparent nature to the optical excitation wavelengths, thus allowing much accurate thermal investigations underneath the gate. To determine the channel temperature profile in devices subjected to different electrical bias voltages, the GaN band-edge PL peak shift calibration with respect to temperature is used. PL analyses show a maximum channel temperature up to 435 K underneath the gate edge between gate and drain, where the estimated thermal resistance in such a HEMT structure is about 13.7 KmmW-1 at a power dissipation of ~10W/mm. The temperature profiles from micro-Raman measurements are also addressed from the E2-high optical phonon peak shift of GaN, and this method also probes the temperature-induced peak shifts of optical phonon from Si thus showing the nature of thermal characteristics at the AlN/Si substrate interface. [ABSTRACT FROM AUTHOR]

For the first time, the random telegraph signal (RTS) and its corresponding flicker noise (1/ƒ) were investigated in gate-all-around p-type Si-FinFETs. For a device with gate width of ∼ 100 nm (fin height) and length of ∼ 200 nm, the typical RTS capture/emission time constants were ∼ 0.1-1 ms. Very large RTS amplitudes (ΔId/Id up to 25%) were observed, which is an effect attributable to the extreme device scaling and/or interface quality of FinFETs. The estimated scattering coefficients (α ∼ 10-12 - 10-13) are found to be higher than typical values obtained from MOSFETs. These findings demonstrate the relevance of RTS for FinFET operation. [ABSTRACT FROM AUTHOR]

This letter reports on a device layer transfer (based on thermal bonding and grinding backside Si) process and device characteristics of Si MOSFETs on a flexible substrate, focusing mainly on the mechanical bendability of the device and resistance to fatigue. The results demonstrated a well-optimized bonding process, as indicated by the nearly indiscernible performance difference (e.g., subthreshold slope, Vth, and Idsat) before and after the bonding of Si with the flexible substrate. The device characteristics indicate excellent bendability of Si MOSFETs on flexible substrate (e.g., for radius tested down to ±72 mm) and good immunity to fatigue (e.g., negligible performance drift tested up to 103 bending cycles with a radius of ±126 mm). Results suggest the feasibility of this approach in achieving high-performance MOSFETs for applications in performance-sensitive and flexible electronics. [ABSTRACT FROM AUTHOR]

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SO!) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (ϵ ∼ -1.07%) strained-Si0.55Ge0.45 and the n-MOSFET in tensile-strained Si over the relaxed Si0.80Ge0.20 exhibited significant hole (enhancement factor ∼ 1.9) and electron (enhancement factor ∼ 1.6) mobility enhancements over the Si reference. [ABSTRACT FROM AUTHOR]

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with ≤5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (∼ 63 mV/dec), low drain-induced barrier lowering (∼ 10 mV/V), and with ION/IOFF ratio of ∼ 106. High drive currents of ∼ 1.5 and ∼ 1.0 mA/μm were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body. [ABSTRACT FROM AUTHOR]

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (∼0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average ΔId/Id ∼ 10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (Lg ∼ 55 nm -0.530 μm/W ∼2-20 μm). The p-MOSFETs also Exhibited Id-improvement by ∼7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects. [ABSTRACT FROM AUTHOR]

Capacitance versus voltage (C-V) and deep level transient spectroscopy (DLTS) characterization was performed on rapid thermal oxides (RTO) on Si[sub 0.887]Ge[sub 0.113] and Si[sub 0.8811]Ge[sub 0.113]C[sub 0.0059] alloys. A high interface trap density (∼10[sup 12] eV[sup -1] cm[sup -2]) and a high apparent doping level were obtained for the SiO[sub 2]/Si[sub 0.8811]Ge[sub 0.113]C[sub 0.0059] samples. The C-V results at different temperatures showed that the high apparent doping levels of the SiO[sub 2]/Si[sub 0.8811]Ge[sub 0.113]C[sub 0.0059] samples might be due to the formation of SiC-related defects introduced by the high temperature oxidation process. [ABSTRACT FROM AUTHOR]

Pseudomorphic Si1- xGe x and partially strain compensated $${\text{Si}}_{1 - x - y} {\text{Ge}}_x {\text{C}}_y $$ layers with different Ge and C fractions have been grown at 500 °C by ultra high vacuum chemical vapor deposition on Si (100) substrates. The degree of strain compensation of the layers has been investigated by high resolution X-ray diffraction and simple application of the linear elasticity theory. The surface morphology of the layers has been characterized by atomic force microscopy. The dependence of Si–Si Raman mode vibrations on strain and composition of binary and ternary alloys have been explained with experimental and theoretically calculated results. The Hall hole mobility is found to increase with decreasing compressive strain or effective Ge content in the layer throughout the temperature range of 120–300 K. [ABSTRACT FROM AUTHOR]

Gas source molecular beam epitaxy has been employed for the growth of a high quality strained-Si layer on a completely relaxed step-graded Si1−xGex buffer layer. As-grown strained-Si layers have been characterized using secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, and spectroscopic ellipsometry for the determination of composition, thickness, crystalline quality, and surface roughness. Heterojunction conduction and valence band offsets (ΔEc, ΔEυ) of strained-Si/SiGe heterostructure have been determined from measured threshold voltages of a strained-Si channel p-metal oxide semiconductor field effect transistor (MOSFET) fabricated using grown films. MOS capacitance-voltage profiling has been employed for the extraction of strained-Si layer thickness and apparent doping profile in the device. [ABSTRACT FROM AUTHOR]

PtSi/p-strained-Si1-xGex (x=0.19 and x=0.29) Schottky barrier diodes have been fabricated and characterized for the determination of barrier height, ideality factor and the interface state density distribution with energy. Diodes having an epitaxial layer thickness of 20 and 52 nm were modeled with emphasis on comparison with experiment. To achieve better agreement with experimental data, an interfacial layer and associated series resistance were included in the model. The capacitance–voltage (C–V) technique has been used for the determination of the energy distribution of interface state density. The interface state density distribution for the Si0.81Ge0.19 and Si0.71Ge0.29 diodes is found to decrease with increasing energy from the valence band edge. [ABSTRACT FROM AUTHOR]

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD HfO2 has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation. [ABSTRACT FROM AUTHOR]

Ultrafast progressive breakdown has been observed in a TaN/TiN metal gate metal-oxide-semiconductor field effect transistor (MOSFET) compared to a polycrystalline silicon gate MOSFET. Physical analysis by transmission electron microscopy and electrical characterization shows that the ultrafast progressive breakdown is likely to be associated with a metal-like filament formation of the breakdown path. It has been observed that the metal-like filament of the breakdown path is detrimental to the metal gate MOSFET progressive breakdown lifetime. [ABSTRACT FROM AUTHOR]

The chemistry of dielectric-breakdown-induced microstructural changes in HfO2 high-κ/polycrystalline silicon gate nMOSFETs under constant voltage stress has been studied. Based on an electron energy loss spectrometry analysis, the hafnium and oxygen chemical bonding in the breakdown induced Hf-based compounds of a “ball-shaped” defect is found to be different compared to the stoichiometric HfO2 and SiO2. The formation of possibly HfSixOy and HfSix compounds in the “ball-shaped” defect is attributed to a thermochemical reaction triggered by the gate dielectric breakdown. [ABSTRACT FROM AUTHOR]

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (∼1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO2, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800 °C-1000 °C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000 °C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000 °C. [ABSTRACT FROM AUTHOR]

The in situ deposition process of SiGe nanocrystals on SiO2 and HfO2 substrates was studied using Auger electron spectroscopy, atomic force microscopy, and x-ray photoelectron spectroscopy. The Ge concentration in SiGe nanocrystals increased with deposition time at equal Si/Ge flow rates. Analysis indicated that the nucleation of Ge takes place preferentially on prenucleated Si on the dielectric. Memory transistors were fabricated using SiGe nanocrystals and HfO2 tunneling/control dielectrics as a gate stack. Memory effects from floating SiGe nanocrystals in HfO2 were clearly observed at room temperature from metal–oxide–semiconductor field effect transistor devices with a threshold voltage shift of about 0.5 V with the application of +4 V. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Temperature dependence of electrical properties of split-N[sub 2]O grown oxides on strained SiGe layers by rapid thermal oxidation is reported. The reliability and thermal stability of ultrathin oxides have been examined by high frequency capacitance–voltage and current density versus electric field measurements. It is observed that at a low (<6 MV/cm) electric field, the shallow trap-assisted conduction mechanism is responsible for the leakage current below 100 °C and the Frenkel–Poole conduction dominates above 100 °C. At a high (>11 MV/cm) electric field, however, the leakage current is mainly governed by the Fowler–Nordheim tunneling. Charge-to-breakdown measurements at a constant current stressing show a higher reliability for the split-N[sub 2]O grown oxides. © 2002 American Institute of Physics. [ABSTRACT FROM AUTHOR]

A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-µm gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The n+-p junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in OFF-state leakage (~5 ×) and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors. [ABSTRACT FROM AUTHOR]

The fabrication of lateral ultra-narrow fin body (thickness ≤10 nm) gate-all-around MOSFETs, which exhibit excellent gate electrostatic control over the channel, is presented. The narrow fins were formed using alternating phase DUV lithography and low temperature oxidation of Si. The device characteristics are completely free from substrate bias effects. [ABSTRACT FROM AUTHOR]

Gate-quality ultrathin silicon dioxide films on strained-Si[sub 0.74]Ge[sub 0.26] layers have been deposited by microwave plasma-enhanced chemical vapor deposition technique using tetraethylorthosilicate. Effect of nitric-oxide (NO)-plasma treatment on the electrical properties of the deposited oxides have been studied using a metal-insulator-semiconductor structure. A significant improvement in the interface trap level density (D[sub it]) and charge trapping behavior under Fowler-Nordheim constant current stressing is observed for NO-plasma treated deposited oxide films. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The electrical characteristics of rapid thermal oxides on Si[sub 1-x-y]Ge[sub x]C[sub y] layers are reported. X-ray photoelectron spectroscopy results indicate segregation of Ge at the SiO[sub 2]/Si[sub 1-x-y]Ge[sub x]C[sub y] interface, a thin GeO[sub 2] layer at the oxide surface, and elemental Ge at the interface and in the oxide. The interface state density of the samples ranges from 3.0x10[sup 11] to 3.6x10[sup 12] eV[sup -1] cm[sup -2]. All the samples show electron trapping behavior and the trap generation rate decreases with increasing C concentration. The charge-to-breakdown value and the oxide breakdown field are higher for Si[sub 0.887]Ge[sub 0.113] than for Si[sub 1-x-y]Ge[sub x]C[sub y] samples, and these values decrease with increasing C concentration. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Introduction. The presence of Hürthle cells (HC) in fine needle thyroid biopsy (FNAB) is a real concern for a cytologist and also for an endocrinologist. We aimed to demonstrate if the presence of HC is associated with specific cytological features in FNAB results. Material and Methods. This retrospective study analyzed 89 patients diagnosed with thyroid nodules, with FNAB; were two groups of patients: the study group A (HC+) (22 patients) with HC and control group B (HC-) (67 patients) with no HC; for both groups we analyzed the presence of 9 cytomorphologic features: overall cellularity, background colloid, lymphocyte infiltration, chronic inflammation, large nucleoli, small nucleoli, syncytial infiltration, nuclear pleomorphism/atypia, cellular pleomorphism. Results. We found no statistical differences between age and gender. Nodules with diameter greater than 2 cm were present, more frequently in the group without HC, 43 (64.18%). The presence of HC is correlated with cellular pleomorphism (p=0.042) and nuclear pleomorphism (p < 0.0001) with no correlation between the other investigated parameters. The presence of colloid was correlated with the absence of HC (p= 0.014). In group with HC was a positive correlation with cellular pleomorphism and fibrosis. In the presence of fibrosis, HC was correlated with nuclear pleomorphism (p=0.03). In the group with HC without fibrosis there are more characteristic the sets with positive nuclear pleomorphism, positive large nucleoli and negative small nucleoli (p= 0.002). Conclusions. The presence of HC in FNAB results is associated with colloid in small amounts, associated with nodules smaller than 2 cm, correlated with cellular pleomorphism and nuclear pleomorphism. Fibrosis can be a protective feature against malignancy because cellular parameters were not significantly associated with HC except the cellular pleomorphism. [ABSTRACT FROM AUTHOR]

Microwave plasma oxidation (below 200 °C) of partially strain-compensated Si[sub 1-x-y]Ge[sub x]C[sub y] (Ge:C=20:1 and 40:1) with and without a Si cap layer is reported. The electrical properties of grown oxides have been characterized using a metal–oxide–semiconductor structure. Fixed oxide charge density and mid-gap interface trap density are found to be 2.9×10[sup 11]/cm[sup 2] and 8.8×10[sup 11]/cm[sup 2]/eV, respectively, for directly oxidized Si[sub 0.79]Ge[sub 0.2]C[sub 0.01] film. The oxide on samples with low C (0.5%) concentration, exhibits hole trapping, whereas electron trapping is observed for oxides on alloys containing 1% C. © 1998 American Institute of Physics. [ABSTRACT FROM AUTHOR]