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The existence of hardware description languages (HDLs), the recent increase in performance, density and radiation tolerance of field programmable gate arrays (FPGAs), and intellectual property (IP) cores provides the technology for reprogrammable systems on a chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. To investigate the flexibility of this technology, the core of the central processing unit and input/output processor of the space shuttle AP101S computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

A large number of traffic accidents are caused by the driver fatigue or drowsiness. These misfortunes can be avoided by keeping a close watch on tired characters of the driver and making a warning signal immediately. This function is implemented by a FPGA based vehicle driver surveillance system presented in this paper. Several well-known image processing algorithms like gray scale projection, edge detection with Prewitt operator and complexity function are combined together to judge whether the driver has his eyes closed. Their hardware architectures have been modeled using the Altera DSPBuilder and integrated as a co-processor to the main Nios II processor which controls the whole system. All of the algorithm hardware implementations have been achieved in a parallel and pipelined way and discussed in detail. The final system is based on the Altera Stratix II EP2S60 FPGA devices and has been proved to meet the basic requirements of drowsiness detection.

This paper describes a versatile and extensible software tool called QUI2VER to support integration of custom components for research prototyping in programmable logic. From higher-level specifications of components and interconnections in an input file, QUI 2VER generates an output VHDL file with a desired system configuration. The value of QUI2VER stems from how abstract interfaces can be specified in support of component interconnection for system-level configuration. Because it is an original research tool, QUI 2VER can also be readily modified and enhanced to serve research needs. The utility of QUI2VER is illustrated by describing its use in the prototype implementation of a multibank embedded memory architecture in an Altera Stratix logic chip as part of ongoing system-on-chip research

This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field programmable gate arrays (FPGAs). Previous techniques developed for mapping into asynchronous embedded memories cannot be used because modern FPGAs do not have asynchronous embedded memories. After technology mapping, an area-prediction cost function is used to guide the selection of logic cones to be placed in embedded memories. Extra logic is added to compensate for missing asynchronous functionality on the synchronous memories. Experiments conducted on Altera's Stratix device family indicate that this embedded memory mapping technique can provide an average area reduction of 6.2% and up to 32.5% on a large set of industrial designs. A small architecture change that increases the size of the FPGA fabric by 0.05% can increase the average area reduction to 14.1% and up to 59.1% on the same design set.

Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper presents an implementation of edge detection in an FPGA, the Altera nios2 development kit. The paper focuses on providing the often missing link from the algorithm development to the FPGA implementation. In addition to a discussion of the edge detection algorithm, memory access and data transfer to the FPGA is discussed. Memory access is achieved by developing a generic component that handles the memory transfer on the Avalon Bus. The design is open so other memory intensive algorithms can be used with only a slight modification of components. In addition the testing software and firmware development is described. The results show how a highly parallel algorithm can run faster on a 50 MHz FPGA then a modern PC in the GHz.

As more embedded systems are designed to transfer data digitally nowadays, the security of transmission become increasingly important. A reliable algorithm to encrypt and to decrypt data is necessary to fulfill such need and also to keep up with the fast data rates required by modern communication standards. One of the widely used cryptography algorithms, the Rivest-Shamir-Adleman (RSA) is computationally complex because of the very-long integer modular and multiplication operations; these two issues make difficult to implement RSA in embedded software. This paper analyses an RSA implementation on a reconfigurable platform consisting of a NIOS processor augmented with Stratix FPGA. Specifically, we consider Montgomery Modular Multiplication (MMM) to replace the expensive multiplication and modular operations, and provide reconfigurable hardware support for the MMM and Montgomery Modular Exponentiation (MME) that internally calls MMM. To incorporate the MME unit into the NIOS processor, a new custom instruction is defined. Preliminary results indicate that since the speed-up of the reconfigurable solution versus pure-software solution is at least 5x, the approach that is being proposed is promising.

For high data rate, new mechanisms such as Block Ack and frame aggregation are currently being discussed in IEEE 802.11e and IEEE 802.11n, respectively. These mechanisms need a short response time in each MPDU processing. In this paper, we propose an efficient design of CCMP for IEEE 802.11i to support these new MAC mechanisms. The proposed design adopts the mode toggling approach, in which MIC calculation and data encryption are sequentially performed for each 128 bits of the packet in only one AESCCM core. In our design, the response time is reduced to a short constant period, which takes only 44 clock cycles. In addition, we can reduce hardware complexity and power consumption, because our design uses one AES-CCM core and obtains the reasonable data throughput and response time at even low clock frequency. We have implemented the proposed design, which is targeted to Altera Stratix FPGA device. As a result of the experiments, the CCMP features 285 Mbps data throughput and 0.88 μs . response time at 50 MHz frequency.

In modern radio location systems based on passive coherent location (PCL), one of the key problems is an efficient and accurate computation of the cross ambiguity function (CAF). This function is related to the direct signal and signals reflected from localized targets. CAF represent power spectral density distribution of the cross-correlation between direct and reflected signals. In this paper we present an attempt to implement (numerically effective and sufficiently accurate) the CAF computation accelerator on FPGA. The results show that this accelerator could be used to compute CAF in real-time in the future PCL systems. The presented design has been implemented in PC accelerator cards based both on Xilinx Virtex IV and Altera Stratix II devices. The presented contribution gives overall information about the algorithms, accelerator architecture design and achieved performance. The possibilities of the future enhancements are discussed.

In order to benchmark the performance of the new generation optical routers, we developed an OC-48 traffic generator using the High-Speed Development Kit, Stratix GX Edition, available from Altera. This paper describes our architecture and its implementation. It also shows the characterization of the 2.488 Gbps Small Factor Pluggable (SFP) and the graphical user interface.

A transverse damping system is used in the Recycler at Fermilab to damp beam instabilities which arise from large beam intensities with electron cooling. Initial tests of electron cooling demonstrated beam loss due to transverse beam motion when the beam was cooled past the beam density threshold. The transverse damper system consists of two horizontal and two vertical pickups whose signals are amplified and passed into an analog hybrid to generate a difference signal from each pickup. The difference signals are input to a custom digital damper board which digitizes the analog signals at 212MHz, performs digital processing of the signals inside a large Altera Stratix II FPGA, then provides analog output at 212MHz via digital to analog converters. The digital damper output is sent to amplifiers which drive one horizontal and one vertical kicker. An initial prototype digital damper board has been successfully used in the Recycler for over six months. Currently, work is underway to replace the prototype board with an upgraded VME version.

This paper presents high speed digital scan converter (DSC) capable of providing more than 100 images per second for the cardiac imaging of the mouse where the heart rate is 3-5 beats per second. To achieve the desired performance, the developed DSC adopted linear interpolation algorithm to minimize the time consumption of fetching stored samples to carry out data interpolation and look-up table method for coordinate transformation. The imaging system can generate more than 100 images per second: scan conversion for an image pixel spends 3 clock cycles and data transfer rate between DSC and a personal computer (PC) to display the scan converted images on a monitor is more than 266 Mbytes per second. The designed imaging system was implemented by using a single FPGA (Stratix EP1S60F1020C6, Altera Corporation, San Jose, CA) and software programs written by C++. By experiment, it is shown that the implemented system is capable of acquiring up to 190 images per second. The display rate of the images is currently 80 images per second due to the limitation of a monitor's capability although all scan converted images can be stored in the hard disk of PC

A novel method of synchronization for RFID digital receiver is presented in this paper. The receiver can adaptively demodulate the burst mode receiving date from 31.2kHz to 780.8kHz and achieve fast synchronization and decoding, which is robust to plusmn2.5% frequency deviation within one frame. Meanwhile the power spectrum density of the receiving code is calculated and analyzed. The implementation is verified on Altera Stratix II EP2S60 and the testing results are given

We propose a run-time re-configurable parametric architecture (Fabric) for local neighborhood image processing. The proposed architecture is composed of polymorphous cells where each cell accesses neighborhood data from a local cell memory, and executes a neighborhood function sequentially. The architecture is flexible since different neighborhood functions can be implemented by rewriting a cell’s software micro-code. High throughput is achieved because many cells execute concurrently. We show that for a satellite image feature extraction application, our architecture, implemented on Stratix II and Virtex 2 Field Programmable Gate Arrays, achieves similar performance, hardware resource utilization, and throughput as a fully pipelined systolic array architecture, yet offers improved flexibility to the developer. We compare and contrast these two architectures for their usability to the image processing community.

A high-speed and area-efficient Viterbi decoder is presented in the paper, and a new survivor path structure including RAM blocks and trace-back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chip's area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2300 LEs are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 163 MHz. The proposed Viterbi decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast

The increasing system resources available on field-programmable gate arrays (FPGA) enable the integration of complex system on one programmable chip. This paper focuses on the design and implementation of a hierarchy-bus based multi-processor system-on-chip (MPSoC) integrating 4 ARM processors on FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% adaptive look-up tables (ALUTs) of Altera Stratix II EP2S180 and a maxim performance speedup of 3.2

Based on the single tone power evaluation (STPE), a self-calibration algorithm of I/Q mismatch is proposed for the IEEE 802.11a WLAN systems. The self-calibration algorithm is performed by the digital baseband at transceiver start-up to measure the signal power of the single tone signal, which is located at the double frequency band at the receiver. Furthermore, the residual I/Q mismatch is tracked during the physical data transmission. Therefore, the design requirements of the RF front-end for the WLAN OFDM transceiver are alleviated. According to the proposed algorithm, the residual signal-to-noise ratio (SNR) degradation is totally less than 0.5-dB with plusmn5% gain mismatch (DeltaG) and plusmn5deg phase mismatch (Deltathetas) in the transmitter and receiver respectively, and carrier frequency offset (CFO = plusmn232kHz). Finally, the prototype of the IEEE 802.11a WLAN baseband is realized by the Altera Stratix EP1S80 DSP development board with about 32000 logic elements at 40MHz

First to introduce the concepts of Variable order Markov Modelling into a hardware core. The combination of this powerful statistical modelling technique and arithmetic coding delivers excellent compression ratios superior to classical dictionary-based compression techniques such as ZIP or ARJ. Statistical algorithms are recognized as optimal but software implementations run at orders of magnitude slower than dictionary-based techniques. The innovative hardware architecture obtained in this work overcomes these problems. An EPSRC grant was obtained based on this work to add support for multimedia content. This paper presents a practical realization in hardware of the concepts of variable order Markov modeling using multisymbol alphabets and arithmetic coding for lossless compression of universal data. This type of statistical coding algorithm has long been regarded as being able to deliver very high compression ratios close to the information content of the source data. However, their high computational complexity has limited their practical application in embedded environments such as in mobile computing and wireless communications. In this paper, a hardware amenable algorithm named PPMH and based on these principles has been developed and its architecture and implementation detailed. This novel lossless compression core offers innovative solutions to the computational issues in both stages of modeling and coding and delivers high compression efficiency and throughput. The configurability features of the core allow efficient use of the embedded SRAM present in modern FPGA technologies where memory resources range from a few kilobits to several megabits per device family. The core has been targeted to the Altera Stratix FPGA family and performance, coding efficiency, and complexity measured for different memory configurations.

The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is dedicated to generate two context-symbol pairs per clock cycle. A novel method called dynamic significance state restoring (DSSR) allows reduction of on-chip memories. The overall design is described in VHDL and synthesized for FPGA and ASIC technologies. Simulation results show that for FPGA Stratix devices, the engine can process about 22 million samples at the frequency of 66 MHz

Particle graphics simulations are well suited for modeling phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normal realized in software, as pan of an interactive graphics application, such as a video game. Their use in such applications is limited by the computational burden and resource competition they create for a host application. We present the design of a hardware particle machine, for implementation in an FPGA, intended for accelerating real-time panicle graphics in applications such as video games. The particle machine is a system that completely contains, manages, and executes particle graphics simulations and rendering. The particle machine is a system comprised of particle memory, a controller, and the panicle pipe, a pipelined particle update processor. The panicle pipe has been synthesized to 130 MHz, on an Altera Stratix FPGA, resulting in a potential throughput of 2.1 million PPF (panicles per frame). This throughput is achieved with minimal load on application and main system performance.

This paper presents a system-on-programmable chip approach for a Schnorr-Euchner strategy based sphere decoder. The decoding algorithm is partitioned with the division intensive matrix computation part on embedded microprocessor and the iterative lattice decoding function on programmable logics. Efficient hardware architectures are developed with three levels of parallelism. The system prototype of the decoder shows that it supports 35.75 Mbit/s data rate on an Altera Stratix EP1S10 FPGA located on Nios development board for a four antenna system with 16-QAM signal constellation, and is about 20 times faster than its implementation on a DSP.

This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be applied to any FPGA architecture containing embedded multiplication, however this paper focuses on using the DSP blocks of Altera Stratix and Stratix II architectures. The transformation is combined with other resource transfers and integrated in a synthesis flow targeting designs implemented on heterogeneous FPGAs. The main advantage of such a system is in handling user constraints on each type of resource: DSP block, LUT and ROM, in addition to timing-related constraints. The flow is based on an extension to the Altera Quartus II synthesis software and Quartus University Interface Program (QUIP) framework. Results are provided for implementations of benchmark algorithms and it is shown through a design-space exploration that the set of achievable designs for the algorithms has been extended by the use of the proposed methods.

This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has completed, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decompositions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental placement step. Experiments conducted on Altera's Stratix and Stratix II device families indicate that this functional decomposition technique can provide average performance improvements of 6.1% and 5.6% on a large set of industrial designs, respectively.

A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.

This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial product lines in order to speed-up the carry propagation along the array. The Hybrid multiplier architecture was previously presented in the literature using Ripple Carry Adders (RCA) in the partial product lines. In our work we present improvements in this multiplier by using a faster CSA along the circuit. The results we present show that the Hybrid architecture with CSA compares favorably in area, performance and power with the architecture with RCA. In this work we also compare the Hybrid multiplier against the Modified Booth multiplier, both using CSA. The results we have obtained show that after using CSA in the partial product lines, the Hybrid multiplier is significantly more efficient than the Modified Booth circuit. Power savings close to 25% are achievable. We compare the multipliers in terms of area, delay and power by using Altera Quartus II tool. Synthesis and simulation of the multipliers are performed for Altera Stratix device.

We describe a FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the central outer tracker (COT) in the CDF experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC, which is implemented as a 9U VME card, has been built around two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHZ LVDS inputs, multiple phase locked clock modules, and abundant memory. The TDC system would operate with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each wire input can accept up to 7 hits per collision. Memory pipelines are included for each channel to allow deadtimeless operation in the first-level trigger; the pipeline has a depth of 5.5 /spl mu/s to allow the data to pass into one of four separate level-two buffers for readout. If the level-two buffer is accepted, the data are passed through a processor implemented in the FPGA to encode the relative time-to-digital values by using the memory positions and addresses of the transitions due to the input pulses. This processing and moving of the data takes 12 microseconds; the results are then loaded into an output VME memory. A separate memory contains the resulting word count, which is used in performing a VME 64-bit chain block transfer of an entire sixteen-card crate. The TDC must also produce prompt trigger flags for a tracking trigger processor called the extremely fast tracker (XFT). This separate path uses the same input data but passes the stream through a special processor, also implemented in the FPGA, to develop the trigger data delivered with a 22 ns clock to the XFT through a high-speed transmission cable assembly. The full TDC design and multi-card test results will be described.

Low-density parity-check convolutional codes complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice and video and packet switching networks. In this paper we introduce these codes and propose a memory-based decoder architecture that is well suited for implementation on field-programmable gate arrays. We present an overview of the architecture and demonstrate its efficiency over register-based architectures. We then discuss a realization of this architecture that can trade performance for throughput and can achieve up to 120 Mb/s of information throughput and a BER as low as 2 /spl times/ 10/sup -6/ at an Eb/Nq of 3 dB on an Altera Stratix FPGA. For a first-generation implementation this compares favorable with current block-oriented decoder implementations.

An FPGA offers an excellent platform for a system-on-chip consisting of intellectual property (IP) blocks. The problem is that IP blocks and their interconnections are often FPGA vendor dependent. Our HIBI (heterogeneous IP block interconnection) network-on-chip (NoC) scheme solves the problem by providing a flexible interconnection network and IP block integration with an open core protocol (OCP) interface. Therefore, IP components can be of any type: processors; hardware accelerators; communication interfaces; memories. As a proof of concept, a multiprocessor system with eight soft processor cores and HIBI is prototyped on FPGA. The whole system uses 36,402 logic elements, 2.9 Mbits of RAM, and operates at 78 MHz frequency on the Altera Stratix 1S40, which is comparable to other FPGA multiprocessors. The most important benefit is significant reduction of the design effort compared to system specific interconnection networks. HIBI also presents the first OCP compliant IP-block integration in FPGA.

We present a digital phase shift beamformer system for medical ultrasound imaging applications. By starting with an overview of the system structure, we focus our discussion on the digital circuit implementation of the complex envelope signal phase shifting by employing the CORDIC algorithm. We analyze the phase delay error tolerance based on a statistical signal model to nd out the minimum number of iterations to be executed in the CORDIC algorithm. We adopt the pipeline strategy to fulfill the CORDIC iterative operation for the efficient usage of hardware resources. Beam pattern simulation results indicate that the proposed system achieves satisfactory performance for beam focusing. Finally, we implement the CORDIC rotator on the Altera Stratix/spl reg/ FPGA to investigate its data processing capability and the consequent hardware savings compared with the complex multiplier by examining its critical path delay.

This paper describes the development of the hardware and software support for a FPGA based accelerator initially conceived for MonteCarlo Metropolis simulations and then evolved to an application specific processor for accelerating floating point calculations. The accelerator is implemented onto an Altera commercial board lodging last generation Stratix family components; its simulation already showed that it is able to outperform modern processing systems in executing floating point operations. In particular the interface block, for communicating with a PC host computer and the memory handler, needed for a quick access to elaboration data, without a time consuming communication are widely described.

In this paper we present the implementation of a successful neurochip, the TotemNC3003 Twinchip by Neuricam, on an FPGA based board lodging the last generation Stratix device from Altera. We already evaluated the performance of the chip in typical neuronal applications, showing that it can outperform a PC, due also to the reactive tabu search algorithm it implements during training and generalising phases. Now, aim of the project is to add a further acceleration degree, by employing a technology which allows to fully integrate the neural algorithm straight onto the hardware and to modify the chip architecture for a more efficient implementation of the neural elaboration.

This work aims to compare several tools and SoC platforms according to the following key parameters: FPGA architecture, coprocessor and accelerator integration, RTOS and HW-SW refinement tools. These key parameters are required to select a flexible and efficient SoC platform (and the associated tools) in order to implement an efficient PACM (processor-accelerator-coprocessor-memory) architecture model. A case study for the PACM architecture model has been targeted in order to validate proposed key parameters. Four platforms were candidate to implement the PACM architecture model. Finally, a Nios development kit (Quartus, SOPC builder and STRATIX device) is used as a prototyping platform for PACM architecture and a shading algorithm for 3D image treatment was implemented as an application to prove the SoC platform adequacy with our PACM architecture model.

In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on "full search block matching" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD's engine with VHDL description. The proposed design is implemented on a "stratix" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using "ModelSim" simulator and synthesis using the "Quartus" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.

In this paper, we propose a parallel hardware architecture for 2-D discrete wavelet transform (DWT) based on the lifting scheme. The architecture is consisted with two row processors and one column processor. The proposed architecture has the 4-way data scheduling, which decreased the initial latency of column direction transform. The transform results of the row processors are directly feed to the column processor, and this method can reduce the internal memory, which stored row processor's results. The column processor, which has the buffer memory to store the filter's intermediate values, can calculate the filter values every clock cycles. This architecture shows that the internal memory size is reduced with around 30% compare to the previous works, and total computational timing improved to N/sup 2//4+a. Finally, the architecture has been implemented in behavioral VHDL. The estimated timing of the maximum clock is 100 MHz in altera stratix device.

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of 10.49 Gbps by using 40 M4Ks. Compared with the unrolling implementation that achieves a throughput of 20.48 Gbps by using 80 M4Ks on the same FPGA, implementations with the PPR architecture reduce the amount of memory up to 75% while increasing the memory efficiency (i.e., throughput divided by the size of memory for core) up to 9.6%.The PPR architecture.lls the gap between unrolling and rolling architectures,and.ts on less expensive FPGAs.

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger.more » The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.« less

This paper presents a design space exploration on the forward 4/spl times/4 Hadamard transform used in the H.264/AVC video coding standard. Five implementations alternatives for this transform were designed. These implementations were described in VHDL and their synthesis was directed to an Altera Stratix device. It is important to point out that the throughputs of all the presented implementations are enough for its use in H.264 codecs for HDTV. The implementations throughputs vary from 146 millions to billions of samples per second.

The JPEG2000 block decoder consists of the bit plane decoder (BPD) tightly coupled with the arithmetic decoder (AD). The BPD generates contexts which are used by the AD to decode sample bits from the compressed bit-stream. The context generation process depends on the decoded bits and thus the BPD has to stall in most cases before it can load a new stripe-column to process. In this paper we present a new selection based sample skipping strategy to restrict the dependence of context generation on decoded bits. This enables the BPD to generate 1 context/clock-cycle for non-empty stripe-columns without stalling to load a new stripe-column. Further we propose speculative technique to improve the operating frequency of our architecture at the expense of extra hardware. The proposed BPD is implemented on an Altera Stratix FPGA. The implementation results show that the proposed architectures yield 50.1-107.1% increase in throughput with only a 27-37% increase in the hardware cost.

This paper presents a novel design for real-time histogram equalization based on field programmable gate arrays (FPGAs). The design is implemented using non-conventional schemes to compute the histogram statistics and equalization in parallel. Counters are used in conjunction with a dedicated decoder specially designed for this purpose. The hardware is fast, simple, and flexible with reasonable development cost. The proposed system is implemented using Stratix II family chip type EP2S15F484C3. The maximum clock frequency can reach up to 250 MHz. In this case, the total time required to perform histogram equalization for an image of size 256 /spl times/ 256 is 0.262 ms.

At the low compression ratio, the EBCOT engine of the JPEG 2000 encoder does not have to process all input data to achieve an optimal codestream in the sense of the rate-distortion criteria. This property is exploited in the architecture presented in this paper to allow higher throughputs of the JPEG 2000 encoder. An impact of the code block size and the internal FIFO size on the resultant speed is considered. The architecture is described in VHDL and synthesized for commercial FPGA technology. Simulation results show that at low compression ratios and for FPGA Stratix II devices, the single engine can support HDTV standards.

This paper presents the design and study of an architecture able to perform 10 Gbit/s GFP frame delineation with single bit error correction on an FPGA. The design targets the development of a system-on-chip (SoC) platform for the design of next generation network processing. In order to achieve the high processing rate, the circuit is designed with a 64-bit data-path and is targeted to Altera Stratix II FPGA technology. The circuit operates at a clock rate of 165 MHz. The circuit utilises 8 parallel CRC HEC calculators and comparators, a PLI frame counter and a single bit error correction mechanism.

In this paper, the authors presented a new linear-time retiming algorithm that produces near-optimal results. The implementation is specifically targeted at Altera's Stratix FPGA-based designs, although the techniques described are general enough for any implementation medium. The algorithm is able to handle the architectural constraints of the target device, multiple timing constraints assigned by the user and implicit legality constraints. It ensures that register moves do not create asynchronous problems such as creating a glitch on a clock/reset signal.

In this paper, we explore the issues of designing a shared buffer architecture for buffering fixed and variable sized packets. The design and implementation of a shared buffer circuit based on Altera Stratix 2 FPGA technology is presented. The proposed architecture is economic from the resource sharing point of view and is capable supporting buffer bandwidths in excess of 6 Gbit/s using standard FPGA technology.

In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial product lines in order to speed-up the carry propagation along the array. The Hybrid multiplier architecture was previously presented in the literature using Ripple Carry Adders (RCA) in the partial product lines. In our work we present improvements in this multiplier by using a faster CSA along the circuit. The results we present show that the Hybrid architecture with CSA compares favorably in area, performance and power with the architecture with RCA. In this work we also compare the Hybrid multiplier against the Modified Booth multiplier, both using CSA. The results we have obtained show that after using CSA in the partial product lines, the Hybrid multiplier is significantly more efficient than the Modified Booth circuit. Power savings close to 25% are achievable. We compare the multipliers in terms of area, delay and power by using Altera Quartus II tool. Synthesis and simulation of the multipliers are performed for Altera Stratix device.

We present a 5 GSPS ADC/Data processing module with up to 64 channels and 2048 cells per channel, designed for fast-sampling, front-end applications. This is a 6U VME board that incorporates 16 pieces DRS4 ( http://drs.web.psi.ch , [1] ) Switched Capacitor Array chips developed at Paul Scherrer Institut, Switzerland. The 16 DRS4 chips are grouped in four independent input blocks. A block, with a geometric size of 43×120 mm, has four pieces DRS4 chips, four pieces AD9222 converters, and one Altera Stratix III FPGA. Each DRS4 chip has eight channels and each channel has 1024 sampling cells, which can be daisy-chained for larger sampling depth. This feature allows for a great level of flexibility in choosing the number of channels relative to capacitor array size, for a particular application. The first prototype Printed Circuit Board (PCB) was designed for a sampling depth of 2048 cells and 16 channels in a 42 mm wide block, i.e. 64 channels for the 6U VME board. This compact form factor allows for these input blocks to be used as front-end electronics for the Cherenkov Telescope Array (CTA) cameras. In this VME board, the four blocks are fully independent and can run each in different modes without any conflict. A global FPGA, also a Stratix III device, provides control and interfacing. The module can run with a local oscillator or with input system clocks in the range of 20–550 MHz. The front panel is fitted with a 2.5 Gbps serial link transceiver.

The development of turbo codes has allowed for near-Shannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate decoding techniques, the circuit complexity and power consumption of turbo decoder implementations can often be prohibitive for power-constrained systems. To address these issues, we have developed a reduced-complexity turbo decoder specifically optimized for contemporary FPGA devices. Our key power-saving technique is the use of decoder run-time dynamic reconfiguration in response to variations in the channel conditions. If less favorable channel conditions are detected, a more powerful, less power-efficient decoder is swapped into the FPGA hardware to maintain a fixed bit error rate. More favorable channel conditions result in the opposite effect. Through experimentation on a stratix-based NIOS development board, we show that dynamic reconfiguration can result in a 52% power reduction versus a static decoder implementation. Comparisons with contemporary microprocessors illustrate a 100/spl times/ performance improvement.

A novel implementation of the QR decomposition based recursive least squares (RLS) algorithm on Altera Stratix FPGAs is presented. CORDIC (coordinate rotation by digital computer) operators are efficiently time-shared to perform the QR decomposition while consuming minimal resources. Back substitution is then performed on the embedded soft Nios processor by utilizing custom instructions to yield the final weight vectors. Analytical resource estimates along with actual implementation results illustrating the weight calculation delays are also presented.

A system-on-a-programmable-chip (SOPC) using an Altera FPGA (Stratix EP1S10) and a Nios embedded processor to develop drive system for permanent magnet synchronous motor (PMSM) is presented in this paper. In this SOPC, it has two modules to construct a fully digital drive controller. One module performs the function of the speed/position loop control and motion trajectory control of PMSM drives. The other module performs the function of the current loop control for PMSM drives, which includes vector control, SVPWM generation, coordinate transformation, PI controller and the pulse detection of the quadrature encoder. The former is implemented by software using Nios embedded processor due to the need of complicated control algorithm and low sampling frequency control (motion trajectory control & position control: less than 1kHz). The latter is implemented by hardware due to the need of high sampling frequency control (current loop: 16 kHz, PWM circuit: 4/spl sim/8 MHz) but simple computation. To confirm the effectiveness of the proposed SOPC, an experimental system with a PMSM, a FPGA experimental board, an inverter and a rectifier has been set up and some experimental results have been validated with the theoretical ones.