Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit

Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper presents an implementation of edge detection in an FPGA, the Altera nios2 development kit. The paper focuses on providing the often missing link from the algorithm development to the FPGA implementation. In addition to a discussion of the edge detection algorithm, memory access and data transfer to the FPGA is discussed. Memory access is achieved by developing a generic component that handles the memory transfer on the Avalon Bus. The design is open so other memory intensive algorithms can be used with only a slight modification of components. In addition the testing software and firmware development is described. The results show how a highly parallel algorithm can run faster on a 50 MHz FPGA then a modern PC in the GHz.