Design of a radix-2m hybrid array multiplier using carry save adder format

In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial product lines in order to speed-up the carry propagation along the array. The Hybrid multiplier architecture was previously presented in the literature using Ripple Carry Adders (RCA) in the partial product lines. In our work we present improvements in this multiplier by using a faster CSA along the circuit. The results we present show that the Hybrid architecture with CSA compares favorably in area, performance and power with the architecture with RCA. In this work we also compare the Hybrid multiplier against the Modified Booth multiplier, both using CSA. The results we have obtained show that after using CSA in the partial product lines, the Hybrid multiplier is significantly more efficient than the Modified Booth circuit. Power savings close to 25% are achievable. We compare the multipliers in terms of area, delay and power by using Altera Quartus II tool. Synthesis and simulation of the multipliers are performed for Altera Stratix device.