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Because of the coefficient of thermal expansion and the hygroscopic swelling mismatches on plastic packaging materials, stress and reliability issues on microelectronic packaging structures are extremely important for the packaging industry. Through the self-design test chips with the piezoresistive microstress sensors, this paper presents the experimental methodologies for stress and reliability monitoring on typical plastic ball-grid-array packaging. To this end, coefficients of the sensors are first calibrated, and stress monitoring is next performed with simultaneously thermal and hygroscopic loadings under steady-state and cyclic environments, respectively. The Weibull reliability model is next applied based on the experimental data and the parameters of the model are extracted. After real-time monitoring on stress variations during the reliability test, about 0.8 MPa of stress decrease is measured on each reliability cycle.

This paper introduces two advanced high-power diode packaging designs, respectively named Z-type and A-type from the Zowie Technology Corp., and analyzes temperature and thermo-stress distributions in the two diode packaging structure. To this end, different currents were first provided to the experiments and temperatures on diode surfaces were recorded to extract suitable thermal convective coefficients. The followed simulations were performed and the mechanical behaviors of the two packaging designs are obtained. This paper finally compared the simulation results with discussions.

Moisture is one of the major contributing factors in fracture and reliability issues for microelectronic packaging. To characterize the moisture-induced stress distribution inside the packaging structure, an in situ, quantitative, and nondestructive experimental methodology is needed. This paper proposes the use of piezoresistive sensors to measure moisture-induced stress in a plastic low profile, fine pitch, ball grid array (LFBGA) packaging. The measurements include hygroscopic swelling stress extractions and real-time stress monitoring of the popcorn phenomenon, and the results associated with gravimetric analyses are reported. Postreflow scanning acoustic microscope (SAM) inspection results and cross section observations are used as experimental verification. Comparing with thermal stresses previously measured on the same package, it is found that the hygroscopic mismatch stress is significant and important for package engineers. In addition, piezoresistive sensors were proven useful in this work for recording popcorn occurrence and monitoring the stress drops at the popcorn initiation.

In this work, a simple assembled structure was designed and fabricated so that the calibration procedures on piezoresistive stress sensors for microelectronic packaging can be simpler, more accurate, and more efficient. After comparing with the previous work results, validity of the aforementioned new structure has been demonstrated through experimental data. Since many accessory experimental facilities employed in traditional calibrations become unnecessary, the new methodology takes great advantage on piezoresistive coefficient extractions, especially for calibration at temperature other than room temperature.

In our previous works, the piezoresistive sensors have been demonstrated to be accurate and efficient tools for stress measurements in microelectronic packaging. In this study, we first designed test chips with piezoresistive stress sensors, temperature sensors as well as heats, and the test wafers were next manufactured through commercialized IC processes. Piezoresistive sensors on silicon strips, which were cut directly from silicon wafers at a specific angle, were then calibrated, and highly consistent piezoresistive coefficients were extracted at various wafer sites so that both normal and shear stress on the test chips can be measured. Finally, we packaged the test chips into 100-pin PQFP structures with different batches and measured internal stresses on the test chips inside the packaging. After measuring packaging induced stresses as well as thermal stresses on several batches of PQFPs, it was found that the normal stress diversities were obvious from different batches of the packaging structure, and the shearing stresses were approximately zero in all of the PQFPs at different chip site.

Through Silicon Via (TSV) is the key technology for the 2.5D and 3D packaging, but reliability evaluations on the new technology products are limited because of the complexity of the environmental issues. To this end, reliability experiments on self-design TSV samples under combinations of several different environmental variables were proposed and performed in this study. The Weibull distribution model was next employed for reliability analyses and the parameters for each of the experimental results were extracted. After analyzing the Weibull parameters, factors that accelerate TSV unreliability are compared with discussions. This paper finally presents failure analyses through OM/SEM observations.

Stress measurements in microelectronic packaging through piezoresistive sensors take the advantage of both in-situ and nondestructive. In this study, test chips with both p-type and n-type piezoresistive stress sensors, as well as a heat source, were first designed, then manufactured by a commercialized foundry so that the uniformity of the test chips was expected. Both temperature and stress calibrations were next performed through a special designed MQFP (Metal Quad Flat Package) and four-point bending (4PB) structure, respectively. Measurements of stresses which are produced due to both manufacturing process and thermal effects on the test chips were finally executed, and approximately linear relationships were observed between stress and temperature as well as stress and input power. It is concluded that n-type piezoresistive stress sensors are able to extract stress in microelectronic packaging with good accuracy.

With the assistances from iteration methodology for heat dissipation property analyses and the effective material properties for the relatively complex PCB structures, this paper extracts the thermal resistance and the transient thermo-mechanical behaviors during reflow for two compactable high power diode packaging through the ANSYS software. After the simulations, further improvements on packaging structure designs were discussed according to the temperature and stress results.

Due to the carrier mobility changes with the mechanical loading and its small size, the MOSFET (metal-oxide-semiconductor field-effective-transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging. In this work, a complete and accurate approach to calibrate the coefficients for both types of MOSFET stress sensors under thermal and mechanical loadings was investigated quantitatively. Through data from different measurement modes on different types of MOSFET, the optimal experimental methodology was next proposed for the sensor applications on packaging stress extraction. The thermomechanical coupling coefficients for the selected experimental mode were finally extracted so that packaging stress measurements with MOSFET under elevated temperature can be performed more accurately.

The MOSFET (Metal-Oxide-Semiconductor Field-Effective-Transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging because the measurements are nondestructive, in-situ, real-time, and the sensor is relatively small. To this end, this paper studies the stress behaviors of both types of the MOSFET micro stress sensors. In this work, a self-developed four-point bending (4PB) measurement methodology is employed and the stress coefficient calibrations on the MOSFET sensors were next performed. After measurements, stress coefficients for both types of the MOSFET were successfully extracted with discussions. After comparing with the previous extracted temperature coefficients on the same devices, it is also concluded that the temperature effect is extremely important for the MOSFET sensor applications.

It is well known that the CTE mismatch and the hygroscopic swelling mismatch in a plastic packaging lead reliability issues so that a suitable extraction methodology on packaging stress and failure parameters are needed. To this end, we first designed and made the piezoresistive stress sensors for packaging stress measurements and performed the sensor calibrations. Test chips were next packaged into a typical plastic packaging and the hygroscopic stress were measured. Finally, a reliability test was performed to extract the long-term effects and the reliability parameters. It is concluded from the works that the hygroscopic mismatch stress is about 50 MPa and it is significant for the packaging. It is also concluded that the Weibull reliability model is suitable for the PBGA packaging, and the Weibull parameters were successfully extracted.

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/°C and 0.60 MPa/°C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency, different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Stress measurements in microelectronic packaging through the MOSFET devices have attracted great attentions because the measurement is in-situ and nondestructive. In this study, a new assembled methodology was designed and applied so that the calibration procedures on MOSFET stress sensors can be simpler and more accurate. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on linear relationships between drain current variation and the mechanical and/or thermal effects, and the results suggested that the MOSFET devices is a useful in-situ stress sensorsin electronic packaging. It is concluded that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

In this work, we studied the availability of p-type MOSFET with 1 mum channel width and 0.15 mum channel length as a stress sensor. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on a new measurement methodology, and linear relationships between drain current variation and stress and/or thermal effects were obtained. According to the measurement data, the extremely important thermal effect was also noted. It is concluded in this work that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications.

The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper.

Piezoresistive sensor has been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, square test chips with four piezoresistive stress sensors and the accompanied diode temperature sensors have been first designed, fabricated and calibrated. A heater was also laid at the chip center. We next packaged test chips into 196-ball LFBGA (Low profile, Fine pitch BGA) packaging and measured stresses on chip surfaces inside the packaging. After measuring the packaging-induced stresses as well as stresses under constant environment temperatures, it was found that compressive stresses were obtained at room temperature, and the compressive stresses are relaxed as temperature increases. It was also found in the same experiments that the average slopes of the temperature-stress curves are between 0.45 Mpa//spl deg/C/spl sim/0.65 Mpa//spl deg/C, and localized stress distributions are observed. For thermal stress experiments, temperatures on chip surfaces at different power levels were first derived. Compressive chip stresses were next measured and the stresses then become tension as the chip power increased. Since all of the measured stresses are much less than the yielding stress, it is concluded that chips inside 196-ball LFBGA packaging will not failure due to thermomechanical effects during regular operations.