Search

3-D nonequilibrium Green's function simulations reveal the presence of oscillations of gate capacitance in multigate silicon nanowire FETs as the gate voltage is increased. These oscillations are due to the filling of successive energy subbands by electrons. The effect is due to both the 1-D distribution of the density of states and a change of position of the charge centroid location with gate voltage in the confined structure. This paper also proposes a model for the gate capacitance that allows one to better understand the nature of the oscillations and shows that the oscillations are mostly due to the particular shape of the 1-D density of states. The change of position of the charge centroid location contributes to a few percents in the total variation of the gate capacitance. The gate-capacitance to oxide-capacitance ratio remains low even at high gate voltages and worsens when the gate oxide thickness is decreased. [ABSTRACT FROM PUBLISHER]

We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon-on-insulator nanowires with a trigate structure using a 3-D numerical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The constrictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the ID–VGS characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors. [ABSTRACT FROM AUTHOR]

We investigate planar fully depleted silicon-on-insulator (SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported. [ABSTRACT FROM AUTHOR]

Abstract: Trigate SOI transistors have been modeled using the Poisson and Schrödinger equations. In devices with a large enough cross section, inversion channels form at the Si/SiO2 interfaces, but in devices with a small section, volume inversion is clearly visible. A transition between a one-dimensional density of states to a two-dimensional density of states is observed when the height of the fin is increased. Current oscillations are experimentally observed when the gate voltage is increased. These are due to a quantum-wire effect in which electron mobility is affected by intersubband scattering. [Copyright &y& Elsevier]

A self-consistent Poisson-Schrödinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm x 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections. [ABSTRACT FROM AUTHOR]

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple, gate device with sidewalls extending into the buried oxide (hereby called a "Π-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications. [ABSTRACT FROM AUTHOR]

Presents the simulation of a silicon-on-insulator nano-flash memory device. Simulation procedure; Device fabrication; Memory operation; Conclusion.

Describes the advantages of using fully-depleted (FD) silicon-on-insulator (SOI) for analog applications at low and high frequencies. Voltage gain of a metal-oxide semiconductor field-effect transistors (MOSFET); Information on basic analog circuits; Details on microwave devices; Conclusion.

Presents the original solutions that were developed for the characterization of silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Measurement procedure; Device fabrication and modeling; Details on extraction method; Discussion of results; Conclusion.

This letter presents the properties of nMOS junctionless nanowire transistors (JNTs) under cryogenic operation. Experimental results of drain current, subthreshold slope, maximum transconductance at low electric field, and threshold voltage, as well as its variation with temperature, are presented. Unlike in classical devices, the drain current of JNTs decreases when temperature is lowered, although the maximum transconductance increases when the temperature is lowered down to 125 K. An analytical model for the threshold voltage is proposed to explain the influence of nanowire width and doping concentration on its variation with temperature. It is shown that the wider the nanowire or the lower the doping concentration, the higher the threshold voltage variation with temperature. [ABSTRACT FROM AUTHOR]

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5–400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6 × 1017 cm-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO2 interfaces, shows up at temperatures lower than 150 K. [ABSTRACT FROM AUTHOR]

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the ID(VG) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm²/Vs, is measured in the subbands at T = 4.4 K. Subband mobility, decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q. [ABSTRACT FROM AUTHOR]

A simple model based on the representation of capacitive coupling effects between the front- and back-gate and the channels, has been developed for tri-gate and pi-gate SOI MOSFETs. The model has been validated using numerical simulation of the body factor in such devices, as well as by experimental results. The body factor is much smaller than in regular, single-gate silicon-on-insulator devices because of the enhanced coupling between gate and channel and because the lateral gates shield the device from the electrostatic field from the back gate. [ABSTRACT FROM AUTHOR]

Analyzes the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage metal oxide semiconductor (DTMOS) devices. Use of both low and high stress gate voltages; Comparison of the temperature dependence of the hot-carrier effects in DTMOS devices with those in SOI partially depleted MOS field effect transistors.

Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the “Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications. [Copyright &y& Elsevier]

Abstract: The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs. [Copyright &y& Elsevier]

The characteristics of SOI DTMOS transistors are measured at various temperatures and compared with those of partially depleted SOI MOSFETs. The temperature dependence of threshold voltage and subthreshold characteristics is investigated both theoretically and experimentally. DTMOS devices operating at elevated temperature are shown to have higher drive current and transconductance and a lower temperature dependence of threshold voltage and subthreshold characteristics than partially depleted SOI MOSFETs. [Copyright &y& Elsevier]

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power. [Copyright &y& Elsevier]