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The ion implantation, oxide isolation with scaling (IMOX-S) bipolar IC processing technique has been utilized to significantly improve the processing speeds and chip densities of VLSI circuits without the expected concommitant increase in power consumption. Power requirements were reduced by optimizing the interrelationships between successive steps of the IMOX-S processing techniques. Greater processing speeds and higher chip densities have been achieved by IMOX via use of oxide isolation and walled-emitter structures, and elimination of capacitances that tend to reduce switching speeds. Details of the IMOX-S process are illustrated with diagrams and photographs.

The PAL 32R16, developed by Monolithic Memories, is the equivalent of 1600 gates and operates at eighteen MHz. Based on the novel product-term sharing technique, the active state of PAL 32R16 may be programmed low or high. The TTL-compatible 32R16 is listed at $50 each in lots of 100. A photograph is shown.

Impact (Implanted Advanced Composed Technology) is a new bipolar process in which all critical components of a very large- scale integrated circuit are placed at the same time with a single mask. Impact combines faster speed than C-MOS with the density of MOS. Fully composed masking allows components to be placed closer together which, along with its fully walled structure, reduces capacitance and boosts density. Impact is suitable for harsh environments. It will likely be targeted for high-speed display processors, superminicomputers and array processors as well as other high speed, high performance applications. Diagrams of the Impact process, graphs of relative performance and a sample applications circuit diagram are included.

A new CMOS process, the self-aligned contact CMOS, or Sacmos, process produces chips with 1.5 to three times the miniaturization attained by the ordinary CMOS process, when both are using the same rules. The chip density achieved by Sacmos when using four-micrometer design rules is the same as that attained by ordinary CMOS utilizing 2.5-micrometer rules. A diagrammatic illustration of the Sacmos process which also permits easier layout, is given. The easy to implement Sacmos is compatible with existing MOS processes. Other theoretical details about Sacmos are given.

Semiconductor products and the competing technologies used to produce them are discussed. Several companies and the particular technologies they use in IC chip fabrication are also detailed. In 1983 IC chip production was worth twelve billion dollars. The market was about equally divided between bipolar and CMOS chips although the trend is towards a shift to CMOS. CMOS memory claimed about three billion dollars of the market. Prodded by the United States DOD and the Japanese government GaAs IC chip production is underway. Diagrams and photographs are shown of some of the technology.

Led by increased density monolithic memory fabrication, several shifts are presented as taking place in the direction of advance of component technology. Instead of merely producing miniaturized, speedy chips a major goal noe is increased density. X-ray semiconductor manufacturing is taking over from the optical variety. 32-bit CMOS microprocessors are predicted. Even the 5-volt standard for power supplies may fall victim to the miniaturization trend. A diagram of a multiplier is shown.

The problems of LSI and VLSI packaging and surface-mounting of components on PC boards are described as being on the way to getting solved. For mounting VLSI, three competing methods are via leadless ceramic chip carriers, pin-grid arrays, and a modification of the latter, the Pinbell, designed by Bell Labs. These methods are detailed and compared. The problems of miniaturized and efficient mounting of passive components have been resolved with the introduction of integrated circuit type passive component packages. Machines have also been built for automatic mounting of packages. The machines may cost anywhere from $50,000 to $200,000. Diagrams and photographs illustrate the new products and packaging schemes.

Wafer Hyper Interconnection Package (WHIP), designed by Mosaic Systems Inc. of Troy Michigan, is a new wafer-scale integration technology. Still under development, WHIP will facilitate cheap, elegant, and simple wafer-integration via electrical programming of chip interconnections. Details of the technology are given. The heart of the packaging scheme is the sandwiching of amorphous silicon between metal interconnections on the wafer. The insulating amorphous silicon may then be crystallized via applied voltage. Prototypes are expected in the spring of 1984. Photographs and diagrams illustrate the WHIP technology, the use of which will result in smaller, low power, and high speed chips.

Still in its development stage, a new memory IC packaging scheme, designed by Wang Laboratories Inc., Lowell MA, will enable efficient, high-density packaging of dynamic RAM. The single in- line memory module (SIMM) allows eight times RAM memory to be fit in the same area as a DIP chip packaging scheme. Several IC chip makers have been contracted by Wang to utilize SIMM. A photograph shows one such chip, a megabyte size of which should cost $200.

Second-generation, 3-micrometer, bipolar, isoplanar integrated- injection logic (I3L), VLSI technology has been used to produce an extremely dense, highly optimized, high-speed, 16-bit, real-time microprocessor, the F9450. Incorporating microcoded architecture to implement floating-point instructions, the F9450, also implements military-standard instruction-set architecture (ISA), MIL-STD-1750A. F9450 is optimized for use in high- speed, high-precision, real-time applications such as is needed in automatic flight control, inertial navigation, and industrial control. Details of the architecture and capabilities of the F9450 are given, including circuit and architectural diagrams.