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We report an ultralow power consuming and forming-free hybrid flexible resistive random access memory device fabricated with poly(4-vinylphenol) (PVP):MoS2 composite and HfO x bilayer, exhibiting threshold switching with ultralow ON-current of 500 nA. While the higher concentration of MoS2 imparted the higher leakage current in the devices, the lower concentration devices exhibited decent switching with set and reset powers as low as 270 and 0.1 nW, respectively. The ultralow switching current indicates the formation of multiple weak nanosized conductive filaments created due to electromigration of Ag atoms under external bias. Moreover, heating temperature-dependent study of switching behavior confirms the metallic nature of the filament as the low resistance state (LRS) current falls significantly with rising temperature. Furthermore, these devices exhibited remarkable mechanical strength on flexible substrate with demonstration of nondestructive switching characteristics at a bending radius as low as 2.5 mm and after 100 consecutive compressive and tensile strain cycles at ±5-mm radius. The ultralow switching current with high flexibility indicates the capability of devices for advancement toward future low-power flexible memories and computing systems.

Resistive switching behavior of poly (4-vinylphenol):graphene oxide (PVP:GO) composite and ultrathin HfO x hybrid bilayer was explored for developing high-performance flexible resistive random access memory (RRAM) devices. These devices, fabricated with a PVP:GO equivolume solution spin-coated and atomic layer deposited ultrathin HfO x as an active bilayer, exhibited excellent bipolar switching behavior with set and reset voltages as low as 0.6 and −1.46 V, ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of >105, and ac and dc switching endurance of over 1400 and 800 cycles, respectively. The same device configuration realized over a flexible polyethylene terephthalate (PET) substrate exhibited a memory window of >103 even after undergoing large mechanical strain (correspoding to a 5-mm bending radius). In addition, after 150 cumulative cycles of consecutive tensile and compressive strain at a 5-mm bending radius, flexible RRAMs demonstrated a clear memory window of $4\times 10^{{3}}$ for 104 s. Overall, the incorporation of GO into the PVP solution resulted in achieving better control over conductive filament (CF) growth and, therefore, improved repeatability and reliability. This article indicates that the strategy of incorporating composite and organic–inorganic active bilayer can lead toward the development of high-performance flexible RRAMs.

Reducing the operating voltage and processing temperature are the crucial factors in the progression of organic field-effect transistors (OFETs) in flexible portable applications. Here, we have dem...

In this work, a combination of a thin layer of Copper (II) phthalocyanine (CuPc) and TIPS-pentacene crystal was used to enhance the photo-sensing spectrum of photo- sensitive organic field-effect transistors (photo-OFETs). In TIPS-pentacene/CuPc bi-layer devices, the different conduction path not only reduced the total number of traps but also enhanced the sensing spectrum. It was found that, though the TIPS-pentacene was able to sense only blue and green colour well, and CuPc was able to sense only red and green colour well; the TIPS-pentacene/CuPc bi-layer were able to sense all three colors, enhancing the range of sensing. On illumination, bi-layer TIPS-pentacene/CuPc OFETs exhibited higher values of shift in threshold voltage (|ΔVTH|) compared to neat TIPS-pentacene and bare CuPc OFETs, due to change in the spatial distribution in the trap state density and associated pattern of trapping of photo-generated charge carriers. It was also found that the values of photo-responsivity (Rmax) and photo-detection time for the bi-layer OFETs were in between that for OFETs with TIPS-pentacene or CuPc.

Physics behind the improvement in breakdown voltage of AlGaN/GaN HEMTs with carbon-doping of GaN buffer is discussed. Modeling of carbon as acceptor traps and self-compensating acceptor/donor traps is discussed with respect to their impact on avalanche breakdown. Impact of carbon behaving as a donor as well as acceptor traps on electric field relaxation and avalanche generation is discussed in detail to establish the true nature of carbon in GaN that delays the avalanche action. This understanding of the behavior of carbon-doping in GaN buffer is then utilized to discuss design parameters related to carbon doped buffer. Design parameters such as undoped channel thickness and relative trap concentration induced by carbon-doping are discussed with respect to the performance metrics of breakdown voltage, leakage current, sheet charge density, and dynamic ON-resistance.

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer.

Lowering the processing temperature is a crucial factor in the development of flexible electronic devices. Here we report the fabrication of high-performance OFETs based on room temperature deposited Ba0.5Sr0.5TiO3 (BST) as a high-k dielectric layer. The fabricated devices exhibited excellent performance while operating at a low voltage of -3 V along with demonstrating high operational stability when tested for 1 h bias stress and continuous transfer measurement cycles. In addition, inverter circuit performance is also investigated with these devices by connecting them to external loads.

Performance of symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) in universal gates and ring oscillator were investigated. Charge carriers in SOI at emitter and collector regions are induced with two unique approaches, i.e., the charge plasma (CP) and polarity control (PC). Four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) was used for bipolar CMOS type NAND and NOR gates. Excellent transient response with rise and fall time less than 5 ns and propagation delay less than 2.4 ns were obtained.

Flexible devices have been in focus for their applications in wearable electronics, displays, sensors, and memory. $\mathrm{PVP}/\mathrm{HfO}_{\mathrm{x}}$ based hybrid resistive random access memory devices were demonstrated on flexible PET substrates to study their resistive switching characteristics and memory application. These RRAM devices exhibited decent repeatability of more than 100 cycles with excellent $I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{off}}$ of ~106 at 0.2 V as read voltage. With retention time of more than 6000 s and reliable switching operation, the fabricated devices have potential to be embedded in flexible electronic applications. Moreover, conduction mechanism in devices was found to be ohmic at lower voltage levels in high resistance state (HRS) and space charge limited conduction at higher voltage levels, occurring mainly due to traps sites available in PVP and $\mathrm{HfO}_{\mathrm{x}}$ . The AFM image confirms the presence of pinholes at PVP surface which will eventually assist in filament formation.

Hybrid CBRAM devices based on PVP/HfOx bilayer were investigated for their switching performance. A reliable and low voltage bipolar resistive switching operation was observed in these devices with repeatability of 300 cycles, Ion/Ioff of 80, set (Vset) and reset (Vreset) voltages of 1.03 V and −0.68 V, retention time of 7200 s, and switching endurance of >2000 cycles in devices with 2.5 wt% PVP concentration. Low device-to-device variation was observed with 10 devices tested showing nearly similar switching parameters. Weibull's distribution of Vset and Vreset voltages have indicated reliable switching performance in devices. The pinholes formation in PVP layer guides the confined growth and dissolution of Ag conductive filament (CF) in the bilayer structure resulting in a stable, reliable and low voltage switching operation. PVP film roughness and pinholes depth have shown downtrend with PVP concentration. During the set process, a CF formed across the electrodes constitutes of Ag atoms, due to pinholes assisted electro-migration of Ag ions. Whereas in the reset process, the diffused Ag+ ions migrate back towards top electrode due to the electrochemical and joule-heating assisted rupture of CF in the PVP/HfOx bilayer structure.

BiFeO3 thin films are deposited on FTO coated glass substrates using a simple sol-gel deposition technique, limiting thickness about 70 nm and Ag/BiFeO3/FTO RRAM devices are prepared. The devices showed low-voltage bipolar switching with the maximum Ion/Ioff ~ 450, and low set and reset voltages ~ 1.1 V and -1.5 V, respectively. The devices are stable against on-off cycles with ~ 104 s retention time without any significant degradation. The variations in the set and reset voltages are 0.4 V and 0.6 V, respectively. We found that ohmic and trap-controlled space charge limited conductions are responsible for low and high resistance states, respectively. The resistive switching mechanism is attributed to the formation and rupturing of the metal filament during the oxidation and reduction of Ag ions for the set and reset states., 15 Pages, 4 Figures, Submitted for publication in Journal of American Ceramic Society

In this report, we have demonstrated the optical non-volatile memory characteristics using CuPc OFET. The memory operation was comprehensively demonstrated with different programming conditions. It was found that the programming of CuPc OFET with an electric pulse at the gate terminal under UV-light photo-illumination compared to other programming conditions, could substantially increase the memory window due to massive charge trapping in the polymer electret layer, which causes shift in the device transfer characteristics from low-conduction state (“OFF state”, or logic 0) to high conduction state (“ON state”, or logic 1) at VGS = 0V. From device operation at −50V, a memory window of greater than 45V could be achieved by applying a programming voltage of +70 V at the gate terminal under UV-light photo-illumination. Moreover, it was completely erased by applying −100 V at the gate terminal in dark.

Atomic layer deposited AlO x based resistive random access memories were fabricated with a new multi-temperature deposition (MTD) scheme, where a 40 nm thick AlO x film was deposited with temperature-thickness sequence of 150 °C (10 nm)/80 °C (20 nm)/150 °C (10 nm). Electrical characteristics of thus fabricated devices demonstrate improved bipolar resistive switching behavior with lower set and reset voltages of 0.65 V and − 1.15 V respectively, decent repeatability of 75 cycles, reliable data retention upto 10 3 s, small variation of 0.29 V and 0.17 V in set and reset voltages respectively, and symmetric current-voltage curves. The conduction mechanism has been explained as ohmic and space charge limited conduction at lower and higher voltages respectively. Due to different deposition temperature, oxygen vacancy concentration was different in each layer of the MTD film, which led to formation of a conductive filament with nonhomogeneous strength and dimensions across the film. Localization of effective switching phenomenon in the region with weaker conductive filament yielded an improved performance with lower switching voltages in corresponding multi-temperature devices.

Effect of ultra-violet (UV) irradiation (λpeak = 365 nm) on the electrical characteristics of solution processed flexible TIPS-pentacene organic field-effect transistors (OFETs) has been investigated. Pristine TIPS-pentacene OFETs demonstrated average field-effect mobility of 0.1 cm2 V−1 s−1, with near zero threshold voltage and current on-off ratio of ∼104. On UV irradiation, OFETs displayed a joint photoconductive and photovoltaic effect due to photo-generated excitons. The maximum current modulation and photo-responsivity obtained from these OFETs were ∼500 and ∼43 mA/W respectively at an intensity of 1.8 mW/cm2 while operating at a low voltage of −5 V. On increasing the irradiation time, a positive shift in the threshold voltage was observed. At larger values of irradiation time, a roll-off in maximum drain current and mobility values were observed, which was attributed to slight deterioration in crystallinity due to prolonged UV exposure, as confirmed from X-ray diffraction studies. Similar trend was observed for mobility and threshold voltage values, when gate bias during UV irradiation was increased. In addition, transistors exhibited a repeatable dynamic response to periodic pulses of UV irradiation.

Photo-response of solution processed flexible TIPS-pentacene organic field-effect transistors is evaluated under illumination with visible light of red, green, and blue colors having minimum wavelengths of 620, 520, and 460 nm. For −10 V operation, pristine photo-OFETs exhibited average field-effect mobility of 0.11 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ , near zero threshold voltage, and current ON–OFF ratio of ~105. These photo-OFETs exhibited prevalent photovoltaic characteristics with shift in the threshold voltage upon illumination, which was found to increase with rising intensity, illumination time, and gate bias during illumination. For low-voltage operation at −5 V, maximum current modulation of $4\times 10^{4}$ and 102, and photo-responsivity of 17 mA/W and 35 mA/W, respectively, were achieved for blue (intensity of 1.7 mW/cm2) and green (intensity of 0.4 mW/cm2) light illuminations. However, these photo-OFETs did not show significant response to red light. A fast dynamic response to periodic pulses of illumination was also observed. For a gate bias of +10 V and illumination time of 500 s, maximum current modulation of 105 was achieved for blue light illumination.

BiFe 0.99 Cr 0.01 O 3 thin film is deposited on FTO glass using sol-gel technique. The deposited film is used in Ag/ BiFe 0.99 Cr 0.01 O 3 /FTO configuration to understand its potential as RRAM device. The device showed forming free bipolar RRAM characteristics with Ion/Ioff~80. The device showed non-volatile behaviour by maintaining its LRS and HRS states for 104 s. The device exhibits excellent reproducibility up to 100 cycles and reliability of V set and V reset voltage is observed. The endurance characteristics for 200 cycles ensures the stability of the device, further, conduction mechanism is attributed to filament formation and switching mechanism is assigned to migration of silver ion inside the film.

In this work, we have explored the effect of TIPSpentacene: polystyrene (PS) blend on electrical performance and photo-response of solution processed organic field-effect transistors (OFETs). It was observed that though the blend OFETs show better electrical performance, the photo-responsivity (R) of neat TIPS-pentacene OFETs was significantly better. This study was performed for different color lights such as blue, red, and green, as well as for ultraviolet light (UV). R was highest for blue color (~2600 mA/W for neat, ~230 mA/W for blend), and smaller for other cases. Low R value in blend devices is attributed to less trapping of photo-generated charge carriers during photo-illumination compared to their neat counterparts.

We report the UV curing of poly(4-vinylphenol) (PVP), which is a widely used polymer dielectric for flexible organic field-effect transistors. OFETs with UV cured PVP dielectric outperformed the classical long-term high temperature annealed PVP OFETs in electrical performance with lower hysteresis, lower threshold voltage shifts in 100 continuous transfer scans and lower normalized drain current decay when bias stressed for 1 h.

We report on the fabrication of bottom gate top contact organic field effect transistors with hybrid gate dielectric and TIPS-Pentacene:PS blend as active layer on PowerCoat™ HD 230 paper substrate. The hybrid dielectric layer leads the devices operated at relatively low voltage of −10 V with avg. and maximum field effect mobility of $0.52(\pm 0.16)$ and 0.78 cm2 V−1 S−1 respectively, with near zero threshold voltage and on-off current ratio approaching ~104. The devices have shown excellent operational stability when tested with DC bias stress of $\mathrm{V}_{\mathrm{DS}}=\mathrm{V}_{\mathrm{GS}}=-10\ \mathrm{V}$ for 1 h and minuscule changes in electrical characteristics were observed with continuous multiple transfer cycle scans. In addition, we have demonstrated a resistive load inverter circuit with varying the load resistance with these paper OFETs.

High-performance operationally stable organic field-effect transistors were successfully fabricated on a PowerCoat HD 230 paper substrate with a TIPS-pentacene:polystyrene blend as the active layer and poly(4-vinylphenol)/HfO2 as the hybrid gate dielectric. The fabricated devices exhibited excellent p-channel characteristics with a maximum and av field effect mobility of 0.44 and 0.22(±0.11) cm2 V–1 s–1, respectively, av threshold voltage of 0.021(±0.63) V, and current on–off ratio of ∼105 while operating at −10 V. These devices exhibited remarkable stability under effects of gate bias stress and large number of repeated transfer scans with negligible performance spread. In addition, these devices displayed very stable electrical characteristics after long exposure periods to humidity and an excellent shelf life of more than 6 months in ambient environment. Thermal stress at high temperatures however deteriorates the device characteristics because of the generation and propagation of cracks in the active ...

Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.

This paper for the first time presents a comprehensive computational modeling approach for AlGaN/GaN high electron mobility transistors. Impact of the polarization charge at different material interfaces on the energy band profile as well as parasitic charge across the epitaxial stack is modeled and studied. Furthermore, impact of surface and bulk traps on two-dimensional electron gas, device characteristics, and gate leakage is accounted in this paper. For the first time, surface states modeled as donor type traps were correlated with gate leakage. Moreover, a new approach to accurately model the forward gate leakage in Schottky gate devices is proposed. Finally, impact of lattice and carrier heating is studied, while highlighting the relevance of carrier heating, lattice heating, and bulk traps over the device characteristics. In addition to this, modeling strategy for other critical aspects like parasitic charges, quantum effects, S/D Schottky contacts, and high field effects is presented.

BiFeO3 based resistive random access memory (RRAM) devices are fabricated using a low-cost solution process to study the effect of an Al top electrode on switching behavior and reliability. Fabricated devices demonstrated bipolar switching characteristics with a moderate Ion/Ioff ratio, set and reset voltages of ∼−1.3 V and ∼0.8 V, DC and AC endurance of more than 250 cycles and 7100 cycles, respectively, and a retention time of over 104 s, confirming the non-volatile resistive switching behavior. The ohmic and trap filled space charge limited conduction dominates the conduction mechanism in the devices at lower and higher voltages, respectively. Moreover, impedance spectroscopy measurements substantiate the presence of an AlOx layer at the Al/BiFeO3 interface resulting from the Al–O interaction at the junction, which is the possible rationale of reliable complementary switching in these RRAM devices. The switching mechanism is elucidated using the formation and rupture of the oxygen vacancy mediated filament, assisted by the participation of a thin AlOx layer at the Al/BFO interface. The role of the thin AlOx layer is explained by modeling of impedances.

A PMMA based Ag/PMMA/Ti/Glass RRAM devices are reported for their resistive switching behavior. Switching performance was tested on three samples fabricated at different PMMA annealing temperatures. The switching voltages have shown a down trend with increasing annealing temperature. The Current on/off ratio and retention time also degrades with annealing temperature. The devices exhibited significantly low switching voltages (

In this work, a TCAD based approach is presented to model electrical behavior of TIPS-Pentacene: polymer blend organic field-effect transistors (OFETs). Stress induced and temperature induced effects are also captured, thereby accurately modeling the device behavior under different operating conditions. The framework is validated against experimental results and is then used to estimate the effect of temperature on characteristics of inverter circuit using this device.

For the very first time, influence of traps on avalanche breakdown of AlGaN/GaN HEMTs is discussed. Impact of surface and bulk traps on breakdown voltage and device scaling is discussed with associated physics. Surface trap's were found to cause distinct breakdown characteristics with breakdown point varying from gate edge to drain edge, depending on nature, type and concentration. Buffer traps too influence the electric field near gate edge and leakage through the device, thereby affecting breakdown voltage accordingly.

The bias-stress stability of low-voltage organic p-channel and n-channel thin-film transistors (TFTs) based on five promising organic semiconductors and fabricated on flexible polyethylene naphthalate (PEN) substrates has been investigated. In particular, it has been studied to which extent the bias-stress-induced decay of the on-state drain current of the TFTs is affected by the choice of the semiconductor and by the gate-source and drain-source voltages applied during bias stress. It has been found that for at least some of the organic p-channel TFTs investigated in this study, the bias-stress stability is comparable to that of a-Si:H and metal-oxide TFTs, despite the fact that the organic TFTs were fabricated at significantly lower process temperatures, which is important in view of the fabrication of these devices on plastic substrates.

Flexible resistive switching memory device is an excellent option for future high density memory and flexible electronics applications. Here, bipolar resistive switching behavior in Al/HfO x /Au resistive random access memory (RRAM) devices fabricated on ultra-flexible polyimide substrates is demonstrated. These devices can be programmed at read-write voltages as low as 0.18 V with on-off current ratios (I on /I off ) of 18, resistance ratio of ∼41 in high and low resistance states (HRS & LRS) and stable set and reset voltages over 16 cycles of operation. The mechanism of resistive switching in these devices is explained with help of filament formation and rupture process due to oxygen vacancy and oxygen ions migration. Ohmic conduction prevails in HRS and LRS whereas conduction mechanism is dominated by space charge limited conduction (SCLC). These flexible RRAM devices could be an excellent option for future high density memory applications.

Inverter circuits based on neat TIPS-pentacene and TIPS-pentacene: polystyrene blend organic field-effect transistors (OFETs) with external resistive load has been studied. Resistive loads of 28 ΜΩ, 40 ΜΩ, 68 ΜΩ and 108 ΜΩ were used to study the inverter transfer characteristics. Transfer characteristics of both types of inverters are improved with increasing load resistance. Inverter with a representative OFET with neat TIPS-pentacene shows a DC voltage gain of −6.9, swing of 40 V, and static power dissipation of 9.5 μW with load of 108 ΜΩ and 50 V power supply. Similarly, inverter with a representative TIPS-pentacene: polymer blend OFET shows a DC voltage gain of −8.7, swing of 44 V, and static power dissipation of 10.2 μW with the same load. For both neat TIPS-pentacene and TIPS-pentacene: polymer blend inverters, maximum DC gain and voltage swing are achieved with highest value of resistive load. However, switching thresholds near V DD /2 are obtained with moderate resistive loads.

Organic field effect transistors (OFETs) have been widely explored for their popular applications in flat panel displays and various kinds of affordable sensors. The overall performance of the device depends on the quality of semiconductor-dielectric interface, and degree of crystalline order in the active layer, close to the above said interface. In the special league of solution processed OFETs, semicondutor: polymer blends have been reported as one of the best possible ways to achieve an intimate, uniform and defect free semiconductor-dielectric interface in a single step. In addition, degree of crystalline order can be further ameliorated through solvent vapor annealing (SVA), which essentially controls the evaporation time of the solvent.

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al2O3 bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm2 V−1 s−1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.

Performance of pentacene organic field-effect transistors (OFETs) is significantly improved by treatment of SiO2 with octyltrichlorosilane (OTS-8) compared to octadecyltrichlorosilane (OTS-18). The average hole mobility in these OFETs is increased from 0.4 to 0.8 cm2/Vs when treating the dielectric with OTS-8 versus OTS-18 treated devices. The atomic force microscope (AFM) images show that the OTS-8 treated surface produces much larger grains of pentacene (∼500 nm) compared to OTS-18 (∼100 nm). X-ray diffraction (XRD) results confirmed that the pentacene on OTS-8 is more crystalline compared to the pentacene on OTS-18, resulting in higher hole mobility.

We report on vertically stacked complementary inverters implemented with a solution-processed [6,6]-phenyl c 61 butyric acid methyl ester (PCBM) n -channel thin-film transistor (TFT) fabricated on top of a 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) and poly(triarylamine) (PTAA) blend p -channel TFT. With a shared common gate electrode positioned between two dielectric layers, bottom-contact p - and top-contact n -channel TFTs showed saturation mobility values of 0.25 and 0.004 cm 2 /V s and threshold voltages of −3.9, and 0.3 V, respectively. The inverter yielded a gain value of −24 V/V with a switching threshold voltage value of 3.3 V at a supply voltage of 7 V. This demonstration of the use of solution-processed semiconductors in a vertically stacked complementary inverter geometry is a step forward towards the development of low-cost complementary electronics.

An amphiphilic diketopyrrolopyrrole-based oligothiophene (DPPamphi) has been prepared that displays robust self-assembly behavior in the bulk, in solution, and on surfaces. The material has been used as the active component in organic field-effect transistors and molecular bulk-heterojunction solar cells.

The contact resistance in pentacene organic field-effect transistors (OFETs) is found to be significantly reduced by selectively doping the organic semiconductor region beneath the source/drain electrodes. A 10 nm co-evaporated (1:1 ratio) layer of molybdenum tris-[1,2-bis(trifluoromethyl)ethane-1,2-dithiolene] and pentacene was deposited under the metal electrodes for this purpose. The width-normalized contact resistance (varying channel lengths of 25–200 μm used for the study) in contact-doped devices was lowered significantly (0.5 kΩ-cm) in comparison to reference devices (3.4 kΩ-cm) in the accumulation regime (VGS = −30 V). Doping of the contacts did not affect the stability of the devices under continuous bias stress significantly.

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al2O3) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (VGS = VDS = −10 V for 1 h), resulting in a negligible drop (∼2%) in saturation current (IDS) in comparison to that in devices with OTS (∼12%), and to a very high decay (∼30%) for the devices with BCB.

A different strategy to form dielectric thin films using atomic layer deposition is proposed, where the dielectric stack consists of three layers in which the middle layer is deposited at a higher temperature than the top and bottom layer. This multi-temperature dielectric stack in metal-insulator-metal capacitor offers improved electrical properties compared to a dielectric film deposited at a single temperature. A multilayer 40 nm thick Al2O3 deposited with temperature and thickness sequence of 80 °C - 10 nm, 150 °C - 20 nm, and 80 °C - 10 nm offers reduced leakage current density by more than one order of magnitude compared to that for a 40 nm Al2O3 deposited at 150°C, and offers higher capacitance density compared to that for 40 nm Al2O3 deposited at 80 °C, and low values of voltage coefficients of capacitance. The changes in the capacitance density and leakage current are found to be strongly dependent on the various roughness values in the devices.

In an attempt to improve ON current and current ON/OFF ratio in tunnel field-effect Transistors (TFETs), a new wedge shaped structure for TFET named Wedge-TFET (WTFET) is proposed. This proposed device is a double gate structure, showing ∼3 times higher ON current compared to planar double gate TFET device working at supply voltage of 0.6 to 1.0 V. This increase is mainly due to increase in the tunneling area. In addition to increased current, W-TFET also shows high current ON/OFF ratio of the order ∼1012. The subthreshold swing values are slightly higher for W-TFET compared to our simulated DG-TFET, however, both of them fall in the range of 40 to 50 mV/dec. The W-TFET device with higher ON current and current ON/OFF ratio and with almost same area requirement can be a potential candidate for future low voltage applications.

In this paper, the influence of gate-source and drain-source bias on the bias-stress stability and lifetime of pentacene-based low-voltage (−3 V) organic thin-film transistors (TFTs) built on plastic substrate has been investigated. The 10%-current-decay lifetime is used for analyzing the influence of applied bias on the bias-stress stability of TFTs, and to compare various biasing conditions. Our results show a 3 to 4 times higher 10%-current-decay lifetime when magnitude of gate-source and drain-source voltage are equal and less than 2.5 V during bias stress, compared to that when drain-source voltage is kept at −3.0 V.

Organic thin-film transistors (TFTs) have potential as pixel drivers in flexible active-matrix organic light-emitting diode displays [1]. Hence it is essential to analyze the charge-carrier injection and extraction dynamics of organic TFTs to gain a better understanding of the trapping and detrapping at the TFT interfaces. From the current-voltage characteristics of the TFTs, many important parameters can be extracted, such as carrier mobility, threshold voltage, on/off ratio, subthreshold slope and transconductance. But to quantitatively evaluate the trapping and detrapping dynamics, displacement current measurements on two-terminal long-channel capacitors (LCCs) are far more useful [2, 3]. The cross-section and the layout of an LCC are schematically shown in Fig. 1. Unlike a TFT, an LCC has only one contact, so that carriers are injected into and extracted from the semiconductor through the same contact. To increase the signal-to-noise ratio, a very large channel length (up to 6 cm) is employed. While Liang et al. have performed displacement current measurements on pentacene-based LCCs [2,3], we report here on displacement current measurements on LCCs based on four different organic semiconductors: pentacene, dinaptho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT), 2,9-didecyl-DNTT (C 10 -DNTT) and diphenyl-DNTT (DPh-DNTT). In TFTs, these semiconductors show hole mobilities ranging from 1 to 7 cm 2 /Vs. The goal of the displacement current measurements reported here is to study how the choice of the semiconductor affects the trapping and detrapping dynamics in organic TFTs.

This paper reports the use of hot-wire chemical vapour deposited (HWCVD) Silicon nitride as a passivation layer for Organic Field Effect Transistors (OFETs). Firstly, the degradation study of the OFETs is done with time. A thin (10–20 nm) layer of silicon nitride is deposited on the OFETs, at a low temperature (

In this letter, the integration of a high-k gate dielectric has been demonstrated for achieving low-operating-voltage organic field-effect transistors (OFETs) and circuits based on solution-processed poly(3-hexylthiophene) (P3HT). We have successfully demonstrated all-p-type organic circuits based on P3HT operating at below 4 V supply voltage. The switching behavior is improved by using the bootstrapping technique, with the boot-strapped inverter showing good results with a dc gain (A(v)) of -1.7 and V(OH) and V(OL) values of 3.3 and 0.35 V, respectively. The output swing of the bootstrapped inverter is improved by about 40% when compared to that of simple all-p-type inverters, as demonstrated by using experimental characterizations.

The use of organic semiconducting material sensors as total dose radiation detectors is proposed, wherein the change in conductivity of an organic material is measured as a function of ionizing radiation dose. The simplest sensor is a resistor made using organic semiconductor. Furthermore, for achieving higher sensitivity, organic field effect transistor (OFET) is used as a sensor. A solution processed organic semiconductor resistor and an OFET were fabricated using poly 3-hexylthiophene (P3HT), a p-type organic semiconductor material. The devices are exposed to Cobalt-60 radiation for different total dose values. The changes in electrical characteristics indicate the potential of these devices as radiation sensors.

Multi-frequency transconductance technique is successfully applied in this work for the first time for interface characterization of OFETs. Standard charge pumping measurements are used on silicon MOSFETs for the validation of MFT technique. The method is implemented on pentacene as well as the P3HT based OFETs with SiO2 as the gate dielectric. Our results show interface state densities in the range of 1012/cm2/eV for both the samples. The P3HT films are also shown to have additional trap centres which respond to frequencies above 100 kHz. Our results therefore clearly indicate that the MFT technique is indeed a highly useful technique for interface characterization of OFETs.

Pentacene organic field effect transistors are fabricated using polymethyl methacrylate (PMMA) as a gate dielectric on flexible polymeric substrates like the indium tin oxide coated polyethylene terephthalate (ITO coated PET), and polyethylene napthalate (PEN) in top contact configuration. The ITO and aluminium (evaporated on PEN) act as the gate materials for the OFETs. The devices on ITO coated PET show electron mobility up to 0.07 cm2/V-s and the on/off ratios in the order of 103.

A systematic and comprehensive study on the charge-carrier injection and trapping behavior was performed using displacement current measurements in long-channel capacitors based on four promising small-molecule organic semiconductors (pentacene, DNTT, C10-DNTT and DPh-DNTT). In thin-film transistors, these semiconductors showed charge-carrier mobilities ranging from 1.0 to 7.8 cm2 V−1 s−1. The number of charges injected into and extracted from the semiconductor and the density of charges trapped in the device during each measurement were calculated from the displacement current characteristics and it was found that the density of trapped charges is very similar in all devices and of the order 1012 cm−2, despite the fact that the four semiconductors show significantly different charge-carrier mobilities. The choice of the contact metal (Au, Ag, Cu, Pd) was also found to have no significant effect on the trapping behavior.

Low-voltage pentacene organic field-effect transistors are demonstrated (operating voltage of −3 V) with high-κ hafnium dioxide gate dielectrics grown by atomic layer deposition at 200 °C. A high hole mobility of 0.39 cm2/V s with low threshold voltage (