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In this paper, a novel cut-off degradation of output current induced by high fluence neutron radiation is investigated for high-voltage silicon-on-insulator lateral double-diffused MOSFET (HV SOI LDMOS). Unlike low/middle fluence, severe current collapse occurs at low drain voltage. Combining experiments and energy band analysis, we reveal that a secondary charge removal effect leads to cut-off degradation, which is closely related to the field enhancement and high-density defects at high neutron fluence. Although the gate channel can be turned on after radiation, below drain threshold voltage (VDT), electron drift is blocked by a potential barrier caused by the local space charge region with low trap occupation rate, rather than the global impact at low fluence. In addition, the influences of structural parameters on the cut-off degradation and VDT are studied to guide the rad-hardening design of HV SOI LDMOS.

Total-ionizing-dose (TID) radiation response on unclosed edge termination is investigated for high voltage silicon-on-insulator (SOI) laterally diffused metal–oxide–semiconductor (LDMOS) in this article. Radiation-induced dual-channel leakage current model is proposed to reveal the mechanism of leakage current generation at OFF-state. Radiation causes a mass of positive oxide trapped charges generated in field oxide (FOX) layer and buried oxide layer. Owing to the P-SOI layer with significantly low doping concentration, two inversion channels are formed at the surface and bottom in the edge termination region, which provides parallel conduction paths. Electrons from the source N+ are pulled down and flow along the bottom channel while punchthrough occurring. The radiation-induced leakage current could be suppressed by thinning FOX layer, increasing the doping concentration of the P-SOI layer, and thickening the SOI layer.

Recently, Shu et al. published “Numerical and Experimental Investigation of TID Radiation Effect on the Breakdown Voltage of 400 V SOI NLDMOS.” This short article is an extension of that earlier article. The breakdown voltage of 400-V silicon-on-insulator n-channel laterally diffused metal–oxide semiconductor field-effect transistors with different drift region lengths are examined after exposure to total ionizing dose. The variation observed is analyzed using technology computer-aided design simulation.

Titanium dioxide (TiO2) is one of the most promising candidates for photoelectrochemistry applications. For a high photoelectrochemistry performance, the control of crystal structure and crystal facet is essential. The phase transformation of TiO2 is conventionally achieved by thermal annealing. Here, we report an approach for selective phase transformation of TiO2 containing exposed reactive facets with improved photoelectrochemistry performance. After femtosecond laser processing, TiO2 nanotubes with exposed reactive anatase {010} facets are prepared, and they have a maximum photocurrent density more than 5 times that of pure anatase. Additionally, this strategy can induce phase transformation in a selective area, which shows the advantages of patterning processing. Our method constructs a promising strategy for preparing functional nanomaterials with high performances and functionality.

The electrical characteristics of silicon-on-insulator (SOI) n-channel laterally diffused metal oxide semiconductor field effect transistors (NLDMOSFETs) are examined after exposure to the total ionizing dose (TID). The devices are partially radiation hardened in that the gate oxide (GOX) and the field oxide (FOX) have undergone a hardening process, but not the buried oxide (BOX). Two bias conditions, OFF-state and all terminals grounded, during irradiation are examined. The irradiated device shows that the OFF-state leakage current ( $I_{L}$ ) of these devices increases with the accumulated dose. The physical mechanisms for the $I_{L}$ are analyzed by technology computer-aided design (TCAD) simulation. The OFF-state leakage current ( $I_{L}$ ) can be explained due to the effects of radiation-induced trapped charge at the BOX silicon interface.

A shield gate trench MOSFET (SGTMOS) featuring narrow gate (NG) architecture and low-k dielectric layer (LDL), namely NL-SGTMOS, is proposed in this letter. By eliminating the middle portion of gate polysilicon without additional mask, and employing LDL between control gate and the grounded field plate (FP), the NL-SGTMOS can greatly reduce parasitic gate-to-plate capacitance induced by the FP, which is a common issue in conventional SGTMOS structure. T-CAD simulations and experiments are performed for evaluations of the proposed device. The fabricated 1-mm2 device (only with NG) achieved on-resistance of 4.57 $\text{m}\Omega $ and gate charge of 7.46 nC at gate voltage of 10 V, which show progressive performance among other existing technologies.

A novel high trigger current NPN transistor (HTC-NPN) with excellent double-snapback performance is developed in $0.5\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. A new floating N+ (FN) layer fabricated in drift-region not only induces two-stage snapback, but also achieves high trigger current ( ${I}_{\text {tr}}$ ) to provide ESD protection for high-voltage (HV) output port without being accidentally triggered on and latch-up like. The operational mechanism and the applied range of the HTC-NPN are discussed in detail, and the double-snapback process induced by the FN is explained via T-CAD simulation as well. From transmission line pulse (TLP) tested results, the proposed HTC-NPN achieved high ${I}_{\text {tr}}$ up to 1.5 A and controllable double-snapback characteristic, thus matching load line from HV output circuit well.

A depletion MOS controlled (DMC) current regulator diode (CRD) based on bipolar carrier transport mechanism is proposed and experimentally demonstrated in this paper. Compared with the conventional CRD based on unipolar junction field effect transistor, DMC CRD features a highly doped p-type substrate. On the one hand, the P+ substrate provides hole injection, which makes the output characteristics of DMC CRD resemble a PIN rectifier when operating in the linear region with a small anode voltage. Accordingly, DMC CRD gets a large slope of output characteristic to realize a lower knee voltage (VK) in comparison to the conventional CRD for a same anode current. On the other hand, the P+ substrate and N-type epitaxial layer can form a reverse PN junction to withstand a high reverse breakdown voltage, which allows DMC CRD to be applied in AC circuit. The initial experimental result demonstrates that a low VK of 1.2 V and a high reverse breakdown voltage (BVR) above 250 V are achieved in a 30-mA-level DMC CRD.

This paper proposed a novel integrated low capacitance transient voltage suppressor (ILC-TVS) for system-level Electrical Over Stress or Electro-Static discharge (EOS or ESD) protection. Compared with the regular TVS, the new one can be fabricated using standard bipolar technology and also possesses the good system-level ESD robustness. By a newly-proposed anode extension technology (AET), the input common-mode capacitance at "0 bias" state is suppressed from 0.78 pF down to 0.65 pF, which realizes the smoother capacitance curve with bias voltage increasing from 0~5 V. According to the standard EOS/ESD tests, the novel ILC-TVS gets the IEC 61000-4-5 EOS peak current (I PP ) of 5.26 A and endures the IEC 61000-4-2 contact mode ESD stress of ± 11 kV. Therefore, the ILC-TVS can provide robust ESD protection for high-speed data interface by on-chip or off-chip design.

In this work, a high-voltage (HV) junction field effect transistor (JFET) with voltage class extended to 800 V is proposed, which obtains a satisfactory on-state breakdown voltage (ON-BV) performance. For the traditional HV JFET, ON-BV is much lower than OFF-BV, which cannot meet the requirement for the application of high voltage start-up circuit. In pursuit of a high ON-BV and making it close to OFF-BV, a dilute-doped resistance region is introduced in the HV JFET to mitigate space-charge-modulation (SCM) effect without additional mask and area. By appropriately increasing the dose of Deep N-Well (DNW), ON-BV can be further increased without degrading OFF-BV. At last, the proposed JFET obtains a high OFF-BV of 900 V and a high ON-BV of 965 V without sacrificing the competitive current capacity above 0.11 mA/μm. Besides, the mechanism of power loss (P LOSS ) induced by substrate current (I SUB ) and gate current (I Gate ) during charging process is also revealed, which is associated with SCM. Benefit by the mitigation of SCM, I SUB +I Gate is reduced significantly in the proposed structure.

The forward-biased diode has been widely applied in electrostatic discharge (ESD) protection projects. In this Letter, various diodes with finger-shaped topology are studied by transmission line pulse (TLP) and emission microscope (EMMI) experiments. Among them, a novel mix-mode diode with P-well and floating deep N-well, called MMDIO, is fabricated by the same process and footprint, except that some discrete N+ regions are being added to the original anode P+ region. This approach forms a combination of a parasitic NPN transistor and a PNPN structure, which can significantly optimise the ESD current efficiency and clamping voltage (V CL). According to the comprehensive comparison, the MMDIO with overlapped anode N+ layout could endure the failure current 1.25 times higher than that of a regular diode under the same junction capacitance (C j), while the V CL is reduced by 20%. Accordingly, the MMDIO is an attractive solution to pass the higher ESD level without any negative influence.

Breakdown voltage (BV) shifting behavior induced by total-ionizing-dose (TID) irradiation is investigated for high-voltage SOI LDMOS, in this letter. The BV increase caused by irradiation is present for the first time, and the degradation mechanism is revealed by modeling and simulation. Irradiation-induced electric field modulation exerts an impact on the competition between the lateral BV and vertical BV and results in BV shifting. The dielectric field is enhanced by irradiation-induced positive oxide trapped charges in the BOX layer, which is responsible for the BV increasing after irradiation. A TID radiation hardening approach is proposed so that the lateral BV is required to be properly higher than vertical BV instead of pursuing equality.

SiC MOSFET with three-section edge termination is investigated in this paper. The edge termination for SiC MOSFET is divided into three sections with different field limited rings and the space between rings, which benefits to achieve uniform electric field and high breakdown voltage (BV). The degradation mechanism of BV and on-resistance during high temperature reverse bias (HTRB) and high temperature gate bias (HTGB) experiment are revealed. For HTRB, positive oxide trapped charge generation on SiC/SiO2 surface enhances the electric field peak at breakdown point, which is responsible for BV decreasing. For HTGB, negative oxide trapped charge generation on SiC/SiO2 surface is responsible for the increase of threshold voltage and on-resistance.

The distribution of radiation induced positive oxide trapped charges (N ot ) in buried oxide (BOX) with different applied electric fields for high-voltage (HV) SOI LDMOS is investigated. In contrast to the traditional model which depends upon N ot buildup near the interface that the field line points to, the verified experimental results in this work indicated that there are still a non-negligible set of N ot generated in SOI/BOX interface even if the electric field plays a negative role (field line perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX). The improved model on BOX damage induced by TID considering this set of N ot and its saturation effect is proposed and adopted in accurate simulated analysis to predict the post-irradiation device behavior. The mechanism of HV SOI LDMOS degradation during irradiation is also revealed. The radiation hardening LDMOS in this work keeps breakdown voltage above 120 V at D=500 krad(Si).

A new narrow gate (NG) trench MOSFET with stepped field plate (SFP) and polysilicon bridge (PB), named NSP-MOSFET, is proposed and discussed in this paper. The SFP can smooth electric field profile along trench, thus improving doping concentration of epitaxial layer and reducing specific on-resistance (R ON,SP ). The NG reduces parasitic gate capacitance and gate charge (Q G ). In addition, the PB can partly offset the increase of internal gate resistance induced by the NG. T-CAD simulations are performed to evaluations of fundamental performances. Benefiting from structural improvements, the proposed device obtains about 22 % and 9.5 % reductions in R ON,SP ×Q G compared with conventional trench MOSFET and SFP trench MOSFET, respectively.

Hot-hole induced burnout phenomenon in a high-voltage triple reduced surface field (RESURF) LDMOS with sandwich N-P-N layer is investigated in this work. The sandwich N-P-N structure is employed in the drift region of LDMOS to obtain a further optimized trade-off between specific on-resistance (R$_{on,sp}$) and breakdown voltage (BV). However, experimental results show that the BV drops in the off-state with a period time of 2.7 s and the device burns out. To solve this problem, the corresponding burnout mechanism is analyzed and its countermeasure is proposed and demonstrated by simulation and experiment. As a result, a competitive performance with a low R$_{on,sp}$ of $32.38 \mathrm{m}\Omega \cdot cm^{2}$ and a high BV of 535 V without burnout is achieved for the triple RESURF LDMOS with sandwich N-P-N layer.

An ultra-low specific on-resistance 700 V lateral double-diffused MOSFET (LDMOS) with a buried super junction (BSJ) layer is proposed. [1–9] Buried P-pillars in the LDMOS can be depleted by neighboring N-pillars, overlying and underlying N-drift regions simultaneously, thus allowing a higher doping concentration. Consequently, the doping concentration of either the N-drift regions or N-pillars, or both, may also be increased therewith to compensate the surplus charges in the P-pillars. Compared with conventional surface super junction (SSJ) LDMOS, in which the super junction layer is implemented at the upper surface of the drift region, and P-pillars can only be depleted by the adjacent N-pillars and the N-drift regions beneath, the proposed novel LDMOS structure may have a lower specific on-resistance (Ron,sp) while maintain the same breakdown voltage (BV). Simulation results indicate that the Ron,sp of the novel structure is only 80.5 mΩ cm2 with a high BV of 750 V, which is reduced by 17% in comparison with the Ron,sp of a conventional SSJ LDMOS.

In this work, a split gate trench MOSFET (SGT) with shield layer (SL) is proposed to improve electrical characteristics. The SL modulates charge division of ionized donor atoms in drift region during depletion spreading. As a result, ionized donors electrically coupled to gate are dramatically reduced, thus lowering gate-drain charge (QGD). On the other hand, the SL structure increases energy band of channel region to address drain induced barrier lowering (DIBL) issue while maintaining a lower channel length and doping concentration. Significant reductions in on-resistance (RON), gate charge (QG), and total power losses are confirmed by simulations. The proposed SGT with SL achieves a switching figure of merit (RON × QG) of 30.46 mΩnC, which is 35.5% smaller than conventional trench MOSFET technology, but almost without impacting other fundamental parameters.

The electrical characteristics variations of 400V SOI NLDMOS after exposure to total dose irradiation are discovered. The mechanisms of these variations are analyzed and confirmed by TCAD simulations.

A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage (V h). Compared with the measured V h of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the V h of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current (I t2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.

An ultra-low specific on-resistance (R on,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that R on,sp is 8.5 mΩ·mm2 while BV is 43 V.

Single event burnout (SEB) of NLDMOSFETs on SOI initiated by pulsed laser irradiation is demonstrated for the first time. The sensitive region of the device for SEB and the effects of reverse voltage and laser energy are explored. The data indicate that the device is most sensitive to laser pulses in the drift region near the P-well. This is influenced by the electric field distribution in the drift region of the LDMOSFET at the time of the laser pulse. The SEB threshold depends on both the applied reverse voltage and the laser pulse energy. The laser pulse energy at a given reverse voltage required to initiate SEB is inversely proportional to the laser spot distance from the P-well. Simulation results for the device drain current following the radiation pulse indicate that the behavior of the npn parasitic bipolar transistor inherent in the LDMOS structure can explain the observations.

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

Cost-effective mask-sharing technology for the 200 V silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) and p-channel lateral double-diffused MOS (PLDMOS) are proposed in this paper. N-well and P-body implantations are shared as an N-buffer implantation of the LIGBT and P-buffer implantation of the PLDMOS, respectively, which reduces two masks compared with the conventional process. The structure and process parameters for LIGBT and PLDMOS with the new process are optimized by simulation to achieve good performance. The experimental results indicate that the LIGBT and PLDMOS using the new process maintain the same performance compared to the conventional devices.

A high-voltage thick layer SOI field p-channel LDMOS (pLDMOS) with multiple field plates based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. Multiple field plates constructed by polysilicon and metal layer are adopted to modulate electric field distribution of the depleted drift region. The SOI field pLDMOS with off-state breakdown voltage (BV) of −240 V is experimentally realized, which can be widely used for simplifying the design of level shifting.

A novel low turnoff loss carrier stored (CS) silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with trench gate barrier (CS SOI TGLIGBT) is proposed. The proposed CS SOI TGLIGBT features a trench gate inserted between the pwell and n-drift. Firstly, the trench gate acts as a hole barrier to prevent the hole from injecting directly into pwell in the on-state, which introduces carrier stored effect and realizes a uniform carriers distribution in the n-drift region, resulting in a decrease of the on-state voltage drop (Von). Secondly, due to the carrier stored effect and the assisted depleted effect induced by the trench gate, large number of carriers can be quickly removed at the initial turnoff process, leading to a decrease of turnoff loss (Eoff). The influences of gate trench barrier on Von and Eoff are investigated. Simulation results show that the proposed CS SOI TGLIGBT can achieve a 59% lower Eoff compared with the conventional SOI trench gate LIGBT at the same Von of 1.15 V.

The back gate (BG) induced breakdown mechanisms for thin layer SOI Field P-channel LDMOS (FPLDMOS) are investigated in this paper. Surface breakdown, bulk breakdown and punch-through breakdown are discussed, revealing that the block capability depends on not drain voltage (Vd), but also BG voltage (VBG). For surface breakdown, the breakdown voltage (BVs) increases linearly with VBG increasing. An expression of BVs on VBG is given, providing a good fitting to measured and simulated results. Bulk breakdown with a low breakdown voltage is attributed to high VBG. VBG induces depletion in n-well, giving rise to punch-through breakdown. A design requirement for the thin layer SOI FPLDMOS is proposed that breakdown voltages for the three breakdown mechanisms are compelled to be higher than the supply voltage of switching IC.

High-voltage (HV) integrated power devices are widely used in many applications, including alternating current/direct current (AC/DC) power converter, HV gate driver integrated circuit (IC) and light emitting diode (LED) driver IC, etc. Among these applications, AC/DC power converter is essential for almost all power systems operated in the DC conditions. As a power switch in the AC/DC converter, the fundamental performance requirement of these power devices is to withstand a high voltage of 500–900 V and simultaneously have a low power loss for its efficient conversion. Therefore, several device technologies have been proposed to realize a high breakdown voltage (BV) and a low specific on-resistance (Ron,sp), such as reduced surface field (RESURF) technology, lateral super-junction (SJ) structure, lateral insulated-gate bipolar transistor (LIGBT), integrated vertical structure and junction termination technology. In this paper, a comprehensive review of the development and prospect of these technologies in AC/DC switching application is presented. Furthermore, analytic Ron,sp-BV models for some typical device structures, the possible strategies of Bipolar - Complementary metal oxide semiconductor - Double-diffused metal oxide semiconductor (BCD) platform integrated with vertical SJ devices, partial silicon-on-insulator (SOI) BCD technology, low gate charge (Qg) HV integrated power devices and wide bandgap technology are also described.

Total Ionizing dose effect induced current degradation for 300V SOI NLDMOS is investigated in this paper. The degradation mechanism of conduction drain current at on-state and leakage current at off-state is revealed by simulation and experiment. The conduction current increasing is ascribed to the reduction of the on-resistance by trapped charges in multiple interfaces. The leakage current increasing is ascribed to the weak inversion layer under filed oxide layer induced by trapped charges. Experiment result shows the annular termination structure benefits to suppress the degradation of leakage current.

Total-ionizing-dose radiation response for 600V ultra-thin layer SOI LDMOS transistor is investigated. Radiation conduction modulation model is proposed to reveal the degradation mechanism of conduction current and breakdown voltage. Multi-interface irradiation damage cause positive net trapped charge, which reduces on-resistance equivalently and enhance conduction current. Meanwhile, they suppress the depletion in the drift region at off-state and then decrease breakdown voltage. Based on the model, irradiation induced net trapped charge density are extracted to evaluate the irradiation damage in drift region.

An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson’s equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer ( $Q_{\textrm {ntop}}$ ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model.

A novel simulation approach for the breakdown characteristics of SOI high-voltage (HV) PMOS in a fixed power supply application is proposed. The different optimized parameters for the SOI HV PMOS can be achieved by the conventional and proposed simulation approaches. A SOI variation of lateral doping (VLD) field PMOS, which is widely used in the level-shift circuit is investigated by the conventional and novel simulation approaches. For the level-shift circuit with power supply of 400 V, the breakdown voltage (BV) of the optimized SOI VLD field PMOS increases from 520 V with the conventional simulation approach to 646 V with the proposed simulation approach. Moreover, the corresponding optimized doping concentration of p-drift region with the proposed approach is higher than that with the conventional approach, thus greatly reducing the specific on-resistance ( R on,sp ). The SOI VLD field PMOS actually has a more robust breakdown voltage and lower R on,sp in the fixed power supply. The BV and R on,sp of SOI HV PMOS can be truly reflected and the effect of reduced bulk field (REBULF) is revealed in the fixed HV power supply by employing the novel simulation approach.

The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure.

This paper proposes a 700 V narrow channel region triple-RESURF (reduced surface field) n-type junction field-effect transistor (NCT-nJFET). Compared to traditional structures, low pinch-off voltage ( V P ) with unobvious drain-induced barrier lowering (DIBL) effect and large saturated current ( I Dsat ) are achieved. This is because p-type buried layer (Pbury) and PWELL are introduced to shape narrow n-type channel in JFET channel region. DIBL sensitivity ( S DIBL ) is firstly introduced in this paper to analyze the DIBL effect of high-voltage long-channel JFET. Ultra-high breakdown voltage is obtained by triple RESURF technology. Experimental results show that proposed NCT-nJFET achieves 24-V V P , 3.5% S DIBL , 2.3-mA I Dsat , 800-V OFF-state breakdown voltage (OFF-BV) and 650-V ON-state breakdown voltage when V GS equals 0 V (ON-BV).

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance ( R on,sp ) and breakdown voltage (BV). With the n-drift region length of 80 μm, the NBL PSOI LDMOS obtains a high BV of 1243 V which is improved by around 105 V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature ( T max ) of 333 K at a power ( P ) of 1 mW/μm which is reduced by around 61 K. Meanwhile, R on,sp and T max of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I esd ) path to improve the holding voltage (V h ) and failure current (I t2 ). The relation between V h and base-concentration (N b ) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V h by changing N b . The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I ESD distribution and V h . The longer ESD current path improves the V h by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I t2 . DC and dynamic TLP simulation results show the V h = 5.3 V of proposed SCR is achieved with a higher failure current (I t2 ) of 1.68e-2A/μm.

A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the R on, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with R on, sp of 96.2 mΩ·cm2 and BV of 758 V is experimentally achieved, which breaks the conventional R on, sp -BV silicon limit of double RESURF technology.

This paper proposes a novel LDMOS structure with ultra-shallow trench isolation (USTI) and p-buried layer in 0.18um BCD technology platform. This platform offers 18V to 40V LDMOS devices which has best-in-class specific on-resistant (R on, sp ) with respect to similar technologies. USTI structure is implemented in LDMOS drift region to reduce specific on-resistance (R on, sp ) by shortening the current flow path and smooth the surface electric field. Meanwhile P-buried layer is introduced to assist depletion and enhance the charge density of drift region, which reduces R on, sp further and keep higher breakdown. The R on, sp of proposed USTI-LDMOS devices is very competitive, 18V LDMOS has BV DSS =27V and R on, sp =7.1 mΩ·mm2; 20V LDMOS has BV DSS =30V and R on, sp =8.8mΩ·mm2; 30V LDMOS has BV DSS =42V and R on, sp =14.5mΩ·mm2; 40V LDMOS has BV DSS =52V and R on, sp =20.5mΩ·mm2.

This paper presents three-dimensional (3-D) edge termination design of a 700-V triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with n-type top (n-top) layer. It is found that breakdown characteristics deterioration related to the electric field crowding and the local charge imbalance in the edge termination. The two crucial parameters L P and L 2 in the layout of the transition region of the edge termination were studied by 3-D numerical simulations and experiments to overcome these issues. As implantation dose of n-top layer (D ntop ) increases from 0.8 × cm−2 to 1.2 × cm−2, progressive performance with Fs from 805 V to 711 V and R on, sp from 86.49 mΩ· cm2 to 80.56 mΩ·cm2 is experimental obtained and the novel LDMOS demonstrates maximum figure of merit (FOM) in the latest existing 700-V LDMOS technologies.

A new reverse conducting lateral insulated-gate bipolar transistor (LIGBT) structure with a non-local band-to-band tunnelling junction is proposed and its operating principle is demonstrated in detail for a power-switching device. By utilising the reverse bias characteristics of the tunnelling junction, the proposed LIGBT can operate successfully in the freewheeling diode mode without an external anti-parallel diode. Analysis has illustrated that the proposed LIGBT can achieve a reverse knee voltage of −1 V and a lower reverse conduction voltage drop of −1.4 V at a current density of 100 A/cm2. It also shows a good temperature effect on the forward and reverse current. Moreover, it exhibits a better soft reverse recovery performance and about two times higher soft factor than the lateral P-i-N diode.

A novel vertical field plate (VFP) lateral device with ultralow specific on-resistance (RON,sp) is proposed in this paper. The VFP surrounded by oxide is inserted in the bulk of the drift region. Compared to the surface local depletion of the conventional lateral field plate (LFP), the depletion layer of the VFP expands to the bulk of the drift region, which enhances the bulk electric field. Therefore, ultralow RON,sp is realized in the VFP device due to high drift-region doping (Nd) and short cell pitch. An analytical FP model is developed to describe the behavior of the VFP, in which the breakdown voltage (BV) and Nd are found to be proportional to the FP factor k. Then the uniform-doped VFP laterally diffused MOSs and the step-doped VFP laterally diffused MOS are proposed. The optimized device exhibits a BV of 945 V and a RON,sp of 34 mΩ·cm2 which are superior to those of similar devices and the silicon limit.

The equivalent substrate (ES) model and the accordant optimized structure for the lateral super junction (LSJ) device are proposed in this paper. The ES, defined as the combination of the depleted substrate under the reverse voltage and the charge compensation layer (CCL) in the substrate, is treated as a whole to analyze the modulation impact of the compensation electric field ΔE on the total electric field of the LSJ. The analytical formulas for the surface electric field profiles of the LSJ are deduced from the 3-D Poisson equation and the Green function. The ES model reveals the essence and the suppression of the substrate-assisted depletion effect in the LSJ, from which the optimized substrate conditions are achieved. The optimized substrate condition allows the LSJ device featuring a similar breakdown voltage to that of the vertical super junction. Then four typical doping concentrations of the CCLs with four different compensation electric field strengths ΔEs are compared. The developed novel device with optimized CCL delivers a breakdown voltage of 301 V, realizing 157% improvement compared with the conventional LSJ with Ld=15 μm, which shows a superior performance to the LSJ devices reported. It is noteworthy that the ES model can also be used to analyze other LSJs.

A low turnoff loss (Eoff) silicon-on-insulator lateral insulated gate bipolar transistor with p-buried layer and double gates (DG-PB SOI LIGBT) is proposed. The proposed LIGBT features a p-buried layer (PB) in the n-drift region and an additional trench gate. Due to the large capacitance effect and hole extraction path induced by PB, larger number of the carriers is removed under low anode voltage (VA), which contributes to a fast turnoff and low turnoff loss (Eoff). What's more, the double gates (DG) structure can reduce the overall stored carriers in the on-state, further improving the Eoff ∼ Von tradeoff. Simulation results show that the DG-PB SOI LIGBT can achieve an 83 % lower Eoff compared with the conventional SOI LIGBT at the same Von of 1.05 V.

NBTI of BOX layer induced degradation for thin layer SOI field p-channel LDMOS is investigated by experiment, modeling and simulation. Decrease in drain current (Id) under high negative BG voltage (VBG) stressing is observed, which is ascribed to the positive fixed oxide charge and interface charge in BOX layer induced by NBTI. The NBTI conduction modulation model is proposed to elevate the positive charge density (ΔQp) generation in the BOX layer. The total on-resistance is enhanced because of hole concentration in the accumulation layer reduced by the positive charges. Simulated Id shift with applying the corresponding ΔQp in the BOX layer shows a good fitting with the measured result. Meanwhile, ΔQp in the BOX layer relaxes the electric field peak at the p-drift/n-well junction on the SOI/BOX interface, which is responsible for breakdown voltage (BV) increasing.

A 200-V SOI p-channel pLDMOS with thick gate oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. The influences of key parameters on on-state breakdown voltage (BV ON ) and off-state breakdown voltage (BV off ) of the SOI pLDMOS are discussed. The SOI pLDMOS with BVoff of −240 V is experimentally realized, and is successfully applied to HV driving IC.

A novel high-voltage (HV) thick layer silicon-on-insulator (SOI) field p-channel lateral double-diffused metal-oxide semiconductor (pLDMOS) with single trench isolation is developed for HV switching IC based on 11-µm-thick silicon layer and 1-µm-thick buried oxide layer. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The deep trench is adopted to realize the compatibility between HV pLDMOS and LV CMOS. The device parameters T, Y for the HV SOI field pLDMOS are optimized to reduce the device size and satisfy the off-state breakdown voltage (BV). The HV SOI field pLDMOS with a BV over 200V is experimentally realized and successfully applied to a 96-bit output driver integrated circuit (IC).

In this paper, the effect of field implantation (FI) on off-and on-state characteristics for thin layer SOI field P-channel LDMOS (FPLDMOS) is investigated. FI effect mechanisms are revealed by modeling, simulating, verifying experimentally. The channel discontinuity gives rise to current step in output curve due to strong electric field and impact ionized generation. Back gate (BG) punch-through breakdown weakens severely block capability. Process parameters for FI technology are optimized to avoid channel discontinuity and BG punch-through breakdown. The rugged thin layer SOI FPLDMOS with channel continuity and punch-through breakdown voltage of −329 V is realized experimentally, and successfully applied in 200-V switching IC.

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R on,sp ) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R on,sp and high BV of above 730 V are achieved by the JITR LDMOS. R on,sp of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV 2 /R on,sp ) in comparison to the published SJ LDMOS.

An ultra-low R on,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BV ds, R on,sp is only 10.7 Ω · mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce R on,sp which also suppress the JFET effect of the triple RESURF LDMOS.