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We present and discuss the infrared properties of molybdenum silicide thin films, molybdenum silicide photonic crystals and the electromigration of molybdenum silicide. Magnetronsputtered and annealed molybdenum silicide layers were investigated via infrared spectral ellipsometry. Simulations of optical properties of molybdenum silicide photonic crystals [metal-insulator-metal structures] show that properties influenced by the size of the structures differ to those of widely used photonic crystals made of Ag. The infrared absorption of MIM-structures comprising of a solid molybdenum silicide layer and one molybdenum silicide layer in form of disks were simulated for different disk diameters and layer thicknesses. A first maximum of absorption (at about 2740 nm) is almost independent of the diameter of the molybdenum silicide disk. A second maximum of absorption (7120 nm -7750 nm) shows an increase of its resonance wavelength with increasing disk diameter. A third maximum of absorption (at about 11000nm) instead shows a respective decrease. In the simulations the thicknesses of the metal layers and the dielectric layer were varied. Changes in the thickness of the dielectric layer caused greater changes in the absorption spectra than changes in the thicknesses of the metal layers. For the application in thermal emitters, the knowledge of electromigration properties of molybdenum silicide layers is crucial. Investigations via accelerated tests with different acceleration factors are demonstrated for test structures. We investigated structures based on molybdenum silicide and for comparison with a well known system analogous structures made of aluminum. We find that molybdenum silicide shows considerably lower electromigration than aluminium.

Schottky diodes prepared on silicon bonded wafers with dislocation network (DN) lying parallel to the sample surface at the depth of ∼2 μm were investigated by means of capacitance-voltage (CV), current-voltage (IV) measurements at 80 K under optical illumination. A model of the interpretation of CV and IV data is presented and discussed. It is shown that electron-beam induced current (EBIC) mapping under the proper chosen forward bias voltages allows one to trace the inhomogeneities of the potential barrier at DN. The observed non-uniformity of the DN barrier heights was ascribed to inhomogeneous distribution of small oxide precipitates lying at the dislocation network plane (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

We report on electro-luminescence from metal-insulator-semiconductor diodes (MISLED). MISLEDs prepared on silicon with HfO2 layers of different thicknesses were investigated and their properties compared with such prepared by using SiO2 insulator layer. The role of the insulator layer was studied in view of the efficiency of the band-to-band radiation from silicon. We show that the luminescence efficiency depends on the dielectric constant of the insulator as well as on its ability to conduct carriers by tunnelling. Efficiency enhancement of 3.3 times was detected when the SiO2 insulator was substituted by HfO2 in the MIS emitter. Optimal injection current exists, which leads to a maximal efficiency of the luminescence. The optimal current depends strongly on the thickness of the oxide. We relate the existence of an optimal current with the depth at which the injected minority carriers recombine radiatively. Thus the electric field in the semiconductor and the surface recombination are the factors determining the optimal injection (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

Incorporation of optical components into microelectronic devices will significantly improve their performance. Absence of effective Si-based light emitter hampers such integration. In the present work light emitting Si diodes, fabricated by dopant (boron or phosphorous) implantation and annealing are investigated. Different implantation doses and annealing temperatures were employed. The efficiency of the electroluminescence (EL), obtained from such structures was measured and correlated with the fabrication process parameters. As previously reported, the EL of band-to-band radiative transition in Si is strongly influenced, by the dopant implantation dose, i.e. higher doses usually enhance EL. Our results suggest that the effect is mainly related to the increase of minority carrier lifetime in the substrate. Distinct measurements showed that the higher implantation doses lead longer carrier lifetimes in the samples. The correlation between lifetime and the EL efficiency could be satisfactory explained in the frame of a classical model, considering the carrier-injection dependence of the rates of the three main recombination mechanisms in silicon, i.e. multi-phonon, radiative and Auger recombination. We suppose that the increase in the implantation dose improves minority carrier lifetime due to the gettering of impurity atoms from the substrate material to the highly doped emitter region.

Using strained SOI as a strategy to enhance the performance of Si-based electronic devices raises fundamental questions about the stability of the strain during different processing steps. In this work, we elucidate the influence of nanoscale pattering, a crucial step in device fabrication, on the strain states. UV micro-Raman and high resolution transmission electron microscopy were employed to quantify the strain in the strained layers. Post-patterning strain in different nanostructures was evaluated by UV micro-Raman. Our data demonstrate that the formation of free surfaces upon pattering leads to a partial relaxation of the strain. The extent of the relaxation was found to depend on the lateral dimension and the geometry. A detailed mechanistic picture is presented based on 3D finite element simulations

The electrical and optical properties of dislocations in Si are reviewed, namely dislocation-related recombination and luminescence, transport of minority and majority carriers along dislocations or the electric field around dislocations. It is shown that Si wafer direct bonding allows well-controlled formation of dislocation networks, giving rise to adjustable dislocation properties. Ideas for novel Si devices utilizing dislocations as active components are presented. In particular, dislocation-based light emitters at about 1.5 μm wavelength are demonstrated. Concepts for dislocation-based conductive channels and fast FETs, manipulators of biomolecules or thermo-electric generators are sketched.

Dislocation networks (DNs) formed by silicon wafer bonding were studied by means of Electron Beam Induced Current (EBIC) and Photoluminescence (PL). The measurements were performed on p–n junction diode structures prepared by ion implantation. EBIC signal was observed not only inside the diode structure, but also far outside the diode area. This finding demonstrates the ability of the bonding interface to efficiently collect minority carriers and indicates a high electrical conductivity of the dislocation network. In addition, circular inhomogeneities of charge collection were observed. The contrast of those regions was bright at high beam energies and turned dark or vanished at lower energies. The contrast behavior of the circular areas can be explained by local variations of collection efficiency and recombination at the DN, which might be a result of different density of oxide precipitates. PL mappings at 0.794 and 1.081 eV revealed similar circular areas.

A new concept for Si-based light emitting diodes (LED) capable of emitting at 1.5 μm is proposed. It utilizes D-band radiation from dislocations in Si. Whether a dislocation network created in a reproducible manner by Si wafer direct bonding or dislocation loops produced by Si ion implantation are employed. It is also stated that dislocation loops do not lead to the strong band-to-band electroluminescence at 1.1 μm of p-n diodes, as it was predicted in the literature. A MOS-LED (Fig. A) and p-n LEDs emitting at 1.5 μm are demonstrated by the authors. The maximum efficiency that could be achieved at room temperature is close to 1%. Levels in the bandgap which are probably involved in the formation of the D1-line at 1.5 μm are revealed. Moreover, the observation of the Stark effect for the D1-line is reported. Namely, a red/blue-shift of peak position was observed in electro- and photo-luminescence when the electric field in the p-n LED was increased/lowered. This effect may allow realization of a novel Si-based light emitter with electric field modulated emission wavelength. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Semiconductor wafer bonding offers a new degree of freedom in the design of material combinations without the common restrictions of the structure of the materials bonded. It is already an established method for the industrial production of advanced substrates (SOI) applied as basic material in high-performance device fabrication. SOI, i.e. a thin device layer on an insulator, is a promising concept for further device developments. The advantages of SOI can be combined with mobility enhancing materials such as strained silicon (SSOI) or germanium on insulator (GOI). The bonding process is not limited to a certain wafer diameter and is applicable to different material combinations which are important to integrate different functions on a chip (system on a chip, SoC). (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing of thin silicon layers on SiGe buffers and their transfer to oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafers characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance.

Spectroscopic Ellipsometry was employed to study the etching process of uniaxially strained Si (sSi) layers obtained by direct wafer bonding of Si wafers in a mechanically benstate followed by thinning one of the Si wafers, the donor wafer, by the smart-cut process, keeping the other, the handle wafer intact The smart-cut process requires a high dose hydrogen implantation into the donor wafer prior to bonding. As a result of the implantation conditions a ∼600 nm uniaxially sSi layer could be transferred onto the handle wafer. In order to thin down and smooth the surface damage of the transferred layer induced by the implantation and splitting process, the samples were dipped in a solution of tetra-methyl ammonium hydroxide (TMAH). The thicknesses of the transferred sSi layers determined from ellipsometry were in good agreement with those obtained from Transmission Electron Microscopy (TEM), while the roughness values were matching those obtained from Atomic Force Microscopy (AFM). The etching rate has also been determined.

The fabrication of two-dimensionally confining X-ray waveguides enables the generation of nanoscopic X-ray beams. First applications of such waveguides for lens-less holographic imaging have already been demonstrated, but were limited by the fabrication methods and the design. To overcome these limitations, we present here the fabrication process for a second generation of X-ray waveguide with air or vacuum as guiding channel, based on e-beam lithography, ion etching and subsequent wafer bonding. This is a first step towards waveguides fulfilling requirements of high transmission and high confinement, since the process can be scaled down to smaller channel dimensions from the present structures. We address the structuring method used and present results of first X-ray characterization at synchrotron beamlines, under two entirely different beam settings, corresponding to the coupling of a coherent beam and an incoherent beam. peerReviewed

The paper presents a critical analysis of Si light emitters made by ion implantation and describes novel concepts for IR light emitters based on silicon nanostructures that do not need Er doping. It is shown that dislocation networks which can be generated in a well controlled way by wafer direct bonding exhibit promising light emitting properties. The luminescence of the dislocation networks can be tailored by the choice of the misorientation of the bonded wafers. It is demonstrated that efficient D1 emission (1.55 μm) at 300 K or D3 emission (1.3 μm) can be obtained for specific misorientations. An enhancement of the luminescence is observed when applying a bias voltage across the network, caused by a changed occupation of the states at the network. Oxygen in the dislocation network is supposed to increase the intensity of the D1 luminescence. Si nanowires are discussed as another potential candidate for IR emitters. Among other lines, efficient luminescence around 1.55 μm is found at 300 K in nanowires. This emission line is attributed to extended defects within the nanowires.

Si-based light emitters with efficient emission at 1.5 or 1.3 μm are required for on-chip optical interconnection for the ultra large scale integrated circuits in the future. In this paper, we have shown that dislocation networks in Si formed by direct wafer bonding emit a quartet of luminescence D-lines. The D-line spectrum can be tailored by the structure of the dislocation network. The D1 or D3, with a wavelength of 1.5 or 1.3 μm respectively, can be made dominating in the luminescence spectrum. An external bias voltage applied to the bonded interface can significantly enhance the luminescence intensity of D-lines.

In order to investigate the electrical properties at the surface of dislocation rich silicon, we conducted Electrostatic Force Microscopy on cross-sections of samples prepared by Wafer Direct Bonding. The applied methods, namely Scanning Kelvin Probe Microscopy and non-contact Scanning Capacitance Microscopy, yield a distinct contrast at the position of the dislocation area, i.e. the bonding interface, indicating strong electrical activity. For an explanation of the explicit electrostatic potential extracted from the experiment a simple model taking into account only an intrinsic charge distribution at the dislocation area appears to be insufficient. Instead, a more complex approach has to be used considering carrier generation and recombination by additional, dynamic mechanisms. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm2 /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices.

Direct wafer bonding between high-density-plasma chemical vapour deposited (HDP-CVD) oxide and thermal oxide (TO) has been investigated. HDP-CVD oxides, about 230 nm in thickness, were deposited on Si(0 0 1) control wafers and the wafers of interest that contain a thin strained silicon (sSi) layer on a so-called virtual substrate that is composed of relaxed SiGe (∼4 μm thick) on Si(0 0 1) wafers. The surfaces of the as-deposited HDP-CVD oxides on the Si control wafers were smooth with a root-mean-square (RMS) roughness of 2 nm. After HDP-CVD oxide deposition on the sSi/SiGe/Si substrates, the RMS roughness of the oxide surfaces was also found to be the same, i.e., >2 nm. To use these wafers for direct bonding the RMS roughness had to be reduced below 1 nm, which was carried out using a chemo-mechanical polishing (CMP) step. After bonding the HDP-CVD oxides to thermally oxidized handle wafers, the bonded interfaces were mostly bubble- and void-free for the silicon control and the sSi/SiGe/Si(0 0 1) wafers. The bonded wafer pairs were then annealed at higher temperatures up to 800 °C and the bonded interfaces were still found to be almost bubble- and void-free. Thus, HDP-CVD oxide is quite suitable for direct wafer bonding and layer transfer of ultrathin sSi layers on oxidized Si wafers for the fabrication of novel sSOI substrates.

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(0 0 1) by chemical vapor deposition (CVD). The plastic relaxation of the initially pseudomorphic SiGe layer is mediated by helium implantation into the Si wafer below the SiGe/Si(0 0 1) interface and subsequent annealing. A SiO 2 layer is grown by plasma enhanced (PE) CVD on the sSi/virtual substrate prior to wafer bonding. The PECVD oxide layer is used to compensate the thermal stress existing at the bonding interface during annealing. The SiO 2 /sSi/virtual substrate wafers are then implanted with hydrogen at a high dose (3.5 × 10 16 H 2 + cm −2 ) and subsequently bonded to Si(0 0 1) handle wafers. Subsequent annealing of the bonded wafer pair leads to the transfer of the implanted layer (containing the sSi layer) from the virtual substrate to the Si handle wafer. The final sSOI structure is realized by subsequent chemo-mechanical polishing followed by selective wet chemical etching. The sSOI substrate shows good thickness uniformity (∼20 nm) of the sSi layer over the entire 8 in. area and the strain measurements indicate a value of ∼0.66%.

Tensile strained Si (sSi) layers were epitaxially deposited onto fully relaxed Si0.78Ge0.22 (SiGe) epitaxial layers (4 μm) on silicon substrates. Periodic arrays of 150 nm × 150 nm and 150 nm × 750 nm pillars with a height of 100 nm were fabricated into the sSi and SiGe layers by electron-beam lithography and subsequent reactive ion etching. The strain in the patterned and unpatterned samples was analyzed using high-resolution UV micro-Raman spectroscopy. The 325 nm excitation line used probes strain in Si close to the surface (penetration depth of ∼9 nm). The Raman measurements revealed that the nano-patterning yields a relaxation of strain of ∼33% in the large pillars and ∼53% in the small pillars of the ∼0.95% initial strain in the unpatterned sSi layer.

The paper deals with possibilities of utilizing dislocation structures as active components of devices. The suggested means for controlled formation of dislocations is direct wafer bonding, giving rise to well defined dislocation networks with adjustable properties. It is shown that the networks allow building light emitting diodes based on the D line luminescence of the dislocations. A light emitter at about 1.5 mm wavelength is demonstrated, with an efficiency potential estimated at 1%. Immobilization of biomolecules on Si surfaces by Coulomb interaction with the dislocations in the network is another application discussed. Finally, the potential use of dislocation networks as insulating layers permeable to impurities to be gettered and as three-dimensional buried conductive channels in the Si wafer is addressed.

Different methods of preparing sSOI wafers have been analyzed. The initial virtual substrate wafers are characterized by a 17 - 20 nm thick strained silicon layer grown either on a thick relaxed SiGe layer on a graded buffer or on a thin SiGe buffer relaxed by He implantation. Bonding and layer transfer experiments using different oxide layers proved that strained silicon layers are completely transferred if designed PE-CVD oxide layers were used. For both types of virtual substrates the oxide layers are deposited on top of the strained silicon and bonded to non-oxidized (blank) silicon wafers. A perfect layers transfer is obtained for virtual substrates having thick SiGe buffer layers (type A) even at 350ºC, while annealing at 450ºC is required for substrates with thin SiGe buffer layers (type B). The lower annealing temperature for substrates of type A is caused by the lower activation energy for blistering. The hydrogen implantation is here into the SiGe. For type B substrates the hydrogen implantation is into the underlying Si requiring a higher temperature for layer splitting (higher activation energy for Si).

Thin relaxed SiGe buffer layers with Ge contents of 23at% and 26at% and thicknesses between 150 to 180 nm on Si(100) terminated with 6 nm Si were made by He ion implantation and annealing. Subsequent overgrowth of the thin buffers with thin strained Si cap layers with SiGe and strained Si reduced the threading dislocation and pile-up densities significantly. Best results were achieved for high temperature SiGe overgrowth with a thickness of 200nm and Ge contents lower than the effective Ge content of the buffer. Threading dislocation densities as low as 1x105 cm-2 and dislocation pile-up densities of 10 cm-1 were determined. Strained silicon on insulator wafers were produced by wafer bonding. Wafer splitting was done by H ion implantation and annealing. The strain of the layers was measured by Raman spectroscopy revealing a strain of 0.66% in the tensile strained Si on the partially relaxed Si0.77Ge0.23 buffers.

On-chip optical interconnects require a CMOS-compatible electrically pumped Si-based light emitter at about 1.5 μm. Dislocations in silicon offer a recombination centre for light emission at the desired energy. Here we report on the radiative properties of dislocation networks, created in a well controllable manner at a certain depth of silicon wafers. Dislocation networks, created by ion implantation and annealing, misfit dislocation in SiGe buffers and a novel concept of dislocations created by misoriented direct bonded Si wafers are discussed. We demonstrate that under a specific misorientation a dislocation network with efficient room temperature D1 (1.55 μm) emission might be generated.

A new concept for a Si light emitting diode (LED) capable of emitting efficiently at 1.55 μm or at 1.3 pm, respectively, is proposed. It utilizes radiation from a well-defined dislocation network created in a reproducible manner by direct Si wafer bonding. The wavelength of the light emitted from the network can be tailored by adjusting the misorientation between the Si wafers. That way dominance of radiation at 1.55 μm (D1 line) or at 1.3 μm (D3 line) was achieved. There are hints that decoration of the dislocations by oxygen enhances the intensity of the D1 radiation. A critical analysis of the light emitter proposed by W. L. Ng et al. [Nature 410, 192 (2001)] using band-to-band emission is given. Its application at the above wavelengths would require a few microns thick SiGe layer on top of the Si substrate.

Reproducible formation of well-controlled dislocation structures is a prerequisite to use dislocations as an active part of devices. Regular dislocation networks have been formed at the interface by Si wafer direct bonding. The barriers of interface were generally smaller than 100 meV. The temperature dependence of the electron-beam-induced current (EBIC) contrast of the interface indicates a deep state density of a few 10E5 per cm along the dislocation lines in the network. It is also found that the dislocation networks in Si can act as effective channel for carrier transport. Photoluminescence (PL) reveals that the D line spectrum related to the dislocation networks can be tailored by the bonding misorientation. So, the D1 line can be made the dominating feature in the PL spectrum. It is suggested that regular dislocation networks represent an interesting new nanosystem for future applications, such as accommodation biomolecules onto silicon, dislocation-based LED or buried nanowires.

Electroluminescence of B and P implanted samples has been studied. P implantation is found to have a similar effect on light emission as B implant. The band-to-band (BB) luminescence of P implanted diodes is observed to increase by more than one order of magnitude upon rising the temperature and an internal efficiency of 2 % has been reached at 300 K. An efficiency larger than 5% seems to be reachable. The strong BB line emission at 1.1 &m is attributed to high bulk SRH lifetime. The BB line escapes from the substrate below the p-n junction. It is not due to the implantation-related defects/dislocations. The luminescence spectrum can be tailored to achieve dominance of the dislocation-related D1 line at about 1.5 &m. It is observed that a regular periodic dislocation network, formed by Si wafer direct bonding with a specific misorientation, exhibits even at 300 K only D1 photoluminescence. Such a dislocation network is believed to be a serious candidate to gain an efficient Si-based light emitter.

RIE-plasma etching of sub-micron structures in 150-200-nm thick Cr layers deposited on 4-inch SiO"2/Si/SiO"2 wafers was investigated as a function of the gas composition, RF power, and resist type. An optimal recipe is obtained yielding a Cr etching rate of about 7 nm/min and a ratio of the resist to the Cr etching rates of about 2 in case of etching the sub-micron structures in Cr with a ZEP 520 resist mask. SEM investigations show nearly vertical sidewalls of features etched in Cr layers with a lateral size ranging from 0.3 to 0.5 @mm.

Strained silicon devices provide for an enhanced carrier mobility compared to that of unstrained silicon devices of identical dimensions. The device performance gets even better when using strained silicon on insulator material. We report experimental procedures based on wafer bonding, smart cutting and selective chemical etching to obtain thin strained silicon (∼15 nm) on insulator wafers. The starting material is an 8″ wafer with pseudomorphically grown strained silicon on a so-called virtual substrate as realized by epitaxial chemical vapor deposition of relaxed SiGe (grown with a grading rate of 10% Ge in the SiGe-alloy per 1 μm layer deposition) on a Si(0 0 1) substrate. The starting and bonded wafers are characterized: (i) structurally using transmission electron microscopy, (ii) topographically, using atomic force microscopy and (iii) the strain is quantified using UV-Raman spectroscopy.

Electroluminescence (EL) of light-emitting diodes (LED) with different active regions and photoluminescence (PL) of Ge layers embedded in Si barriers on Si substrates has been studied. Increasing the tensile strain in the active region of Ge LEDs by using GeSn virtual substrate technology leads to an enhancement of the direct band luminescence. An intensity increase by a factor of four is achieved due to n-type doping with an antimony concentration of 3 × 1019 cm−3. The EL of LEDs with a GeSn/Ge multi quantum well structure as active region show an increased direct band luminescence of GeSn by a factor of 16 compared to an intrinsic Ge LED, revealing the advantage of carrier confinement. A high density of threading dislocations, due to the lattice mismatch of Ge and Si, causes a huge drop of PL intensity in the range of one to two orders of magnitude in the temperature range from 80 to 350 K. Thin and pseudomorphically grown Ge layers between Si barrier layers exhibit a huge PL intensity due to the absence of threading dislocations. Taking into account the thickness of the active region the direct band luminescence intensity is increased by two orders of magnitude.

Strain engineering is ubiquitous in the design and fabrication of innovative, high-performance electronic, optoelectronic, and photovoltaic devices. The increasing importance of strain-engineered nanoscale materials has raised significant challenges at both fabrication and characterization levels. Raman scattering spectroscopy (RSS) is one of the most straightforward techniques that have been broadly utilized to estimate the strain in semiconductors. However, this technique is incapable of measuring the individual components of stress, thus only providing the average values of the in-plane strain. This inherit limitation severely diminishes the importance of RSS analysis and makes it ineffective in the predominant case of nanostructures and devices with a nonuniform distribution of strain. Herein, we circumvent this major limitation and demonstrate for the first time the application of RSS to simultaneously probe the two local stress in-plane components in individual ultrathin silicon nanowires based on the imaging of the splitting of the two forbidden transverse optical phonons.

A new concept for light emitting diodes in silicon capable of emitting 1.55 µm is reported. It utilizes D1-band luminescence from a dislocation network in silicon.

Studies dealing with the bonding behavior of silicon wafers coated with thermal oxide, plasma-enhanced chemical vapor deposition (PE-CVD) oxide, PE-CVD oxynitride, PE-CVD nitride and low-pressure (LP) CVD nitride are presented. The PE-CVD layers require a chemo-mechanical polishing (CMP) before bonding to reduce the surface roughness. The bonding energies of the wafer pairs with different interface layers are similar to those of bonded hydrophilic silicon wafers. Infrared microscopy of patterned wafer pairs reveals interfaces which are almost free of bubbles. Presumably, the gas, which usually generates such interface bubbles, diffuses into the interface cavities. The tensile strengths of patterned wafer pairs including a PE-CVD oxide or a PE-CVD oxynitride interface layer are about twice as high as for patterned hydrophilic silicon wafer pairs.

Metallic impurities are detrimental to many silicon devices and limit the efficiency of multicrystalline silicon solar cells. Therefore they are a major subject of ongoing research. Photoluminescence spectroscopy is a promising technique for detecting precipitated metals in silicon because of its sensitivity to the minority carrier density and to specific types of defects; however the impact of impurities on the defect luminescence could not be clarified yet. In this letter we examine the role of micron-sized iron and copper precipitates in direct bonded wafers by micro-photoluminescence spectroscopy. Both kinds of precipitates are detectable by means of the reduced band-to-band luminescence. An element-specific effect on the defect luminescence is observed. The results are confirmed by X-ray fluorescence spectroscopy. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Two-dimensional arrangements of well-controlled numbers and types of dislocations were realized in thin SOI device layers by semiconductor wafer bonding. Remarkable improvements of nMOSFET performance are obtained if the defects are positioned on well-defined locations in the channel. An increase of the drain current (ID) was proved by one order of magnitude at room temperature. The increase of ID depends on the dislocation type. Mixed dislocations result in the highest increase of the drain current. Such MOSFETs operate also at cryogenic temperatures with excellent parameters (subthreshold swing of 21 mV/dec, etc.). Coulomb blockades related to dislocations are observed making it possible to realize single electron transistors for future cryogenic applications.

A new concept for light emitting diodes in silicon capable of emitting 1.55 μm is reported. It utilizes D1-band luminescence from a dislocation network in silicon. The dislocation network is created in a reproducible manner by silicon wafer direct bonding. A MOS-LED on silicon substrate and a novel two-electrode device in a thin SOI layer using p-n junctions are demonstrated. The maximum efficiency is expected to exceed 1% at room temperature.

Presently the most prominent silicon materials considered for silicon-on-insulator (SOI) technologies are SIMOX (separation by implanted oxygen) and bonded SOI. The present paper will review recent developments for these two types of approaches for SOI materials with special emphasis on the progress in obtaining ultra thin bonded SOI layers by local plasma etching or an etch-back procedure involving stress compensated boron-germanium doped etch-stop layers.

The accurate manipulation of strain in silicon nanowires can unveil new fundamental properties and enable novel or enhanced functionalities. To exploit these potentialities, it is essential to overcome major challenges at the fabrication and characterization levels. With this perspective, we have investigated the strain behavior in nanowires fabricated by patterning and etching of 15 nm thick tensile strained silicon (100) membranes. To this end, we have developed a method to excite the "forbidden" transverse-optical (TO) phonons in single tensile strained silicon nanowires using high-resolution polarized Raman spectroscopy. Detecting this phonon is critical for precise analysis of strain in nanoscale systems. The intensity of the measured Raman spectra is analyzed based on three-dimensional field distribution of radial, azimuthal, and linear polarizations focused by a high numerical aperture lens. The effects of sample geometry on the sensitivity of TO measurement are addressed. A significantly higher sensitivity is demonstrated for nanowires as compared to thin layers. In-plane and out-of-plane strain profiles in single nanowires are obtained through the simultaneous probe of local TO and longitudinal-optical (LO) phonons. New insights into strained nanowires mechanical properties are inferred from the measured strain profiles.

We provide evidence of nanopatterning-induced bending of an ultrathin tensile strained silicon layer directly on oxide. This strained layer is achieved through the epitaxial growth of silicon on a Si0.84Ge0.16 virtual substrate and subsequent transfer onto a SiO2-capped silicon substrate by combining hydrophilic wafer bonding and the ion-cut process. Using high resolution transmission electron microscopy, we found that the upper face of the strained silicon nanostructures fabricated from the obtained heterostructure using electron beam lithography and dry reactive ion etching displays a concave shape. This bending results from the free-surface-induced strain relaxation, which implies lattice out-of-plane expansion near the edges and concomitant contraction at the center. For a ∼110 nm × 400 nm × 20 nm nanostructure, the bending is associated with an angle of 1.5 ◦ between the (2¯ 20) vertical atomic planes at the edges of the ∼110 nm side. No bending is, however, observed at the strained Si/SiO2 interface. This phenomenon cannot be explained by the classical Stoney’s formula or related formulations developed for nanoscale thin films. Here we employed a continuum mechanical approach to describe these observations using three-dimensional numerical calculations of relaxation-induced lattice displacements. (Some figures in this article are in colour only in the electronic version)

The physical properties of materials can be manipulated by applying stress or strain. For instance, the controlled introduction of strain in silicon (Si) devices was found to increase the charge careers mobility and modify the Si optical properties. The exploitation of this potential technology raises fundamental questions on strain and stress stability and behavior during the fabrication and processing of strained Si devices. In this paper, we address this issue and provide detailed three-dimensional finite element simulations of strain redistribution upon nanoscale patterning that is a crucial step in the fabrication of devices. The shown calculated results give valuable insights into the relaxation phenomenon of nano-scale strained silicon mesa-structures and point out ways to modify the strain field in one-dimensional optical micro-cavity waveguides based on photonic crystal designs. Our calculations are augmented by experimental data obtained by UV μ-Raman spectroscopy analysis.

The strain behavior in nanoscale patterned biaxial tensile strained Si layer on insulator is investigated in 60-nm-thick nanostructures with dimensions in the 80-400 nm range. The in-plane strain is evaluated by using UV micro-Raman. We found that less than 30% of the biaxial strain is maintained in the 200x200 nm(2) nanostructures. This relaxation, due to the formation of free surfaces, becomes more important in smaller nanostructures. The strain is completely relieved at 80 nm. This phenomenon is described based on detailed three-dimensional finite element simulations. The anisotropic relaxation in rectangular nanostructures is also discussed.

This article addresses the behavior of strain in ultrathin SSOI during the nanopatterning process.