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Selective-area growth is a promising technique for enabling of the fabrication of the scalable III–V nanowire networks required to test proposals for Majorana-based quantum computing devices. However, the contours of the growth parameter window resulting in selective growth remain undefined. Herein, we present a set of experimental techniques that unambiguously establish the parameter space window resulting in selective III–V nanowire networks growth by molecular beam epitaxy. Selectivity maps are constructed for both GaAs and InAs compounds based on in situ characterization of growth kinetics on GaAs(001) substrates, where the difference in group III adatom desorption rates between the III–V surface and the amorphous mask area is identified as the primary mechanism governing selectivity. The broad applicability of this method is demonstrated by the successful realization of high-quality InAs and GaAs nanowire networks on GaAs, InP, and InAs substrates of both (001) and (111)B orientations as well as homoepitaxial InSb nanowire networks. Finally, phase coherence in Aharonov–Bohm ring experiments validates the potential of these crystals for nanoelectronics and quantum transport applications. This work should enable faster and better nanoscale crystal engineering over a range of compound semiconductors for improved device performance., The project was supported by Microsoft Station Q (Delft). S. Martí-Sanchez acknowledges funding from “Programa Internacional de Becas “la Caixa″-Severo Ochoa”. ICN2 members acknowledge funding from Generalitat de Catalunya 2017 SGR 327. ICN2 acknowledges support from the Severo Ochoa Programme (MINECO, grant no. SEV-2013-0295) and is funded by the CERCA Programme/Generalitat de Catalunya. Part of the present work has been performed in the framework of Universitat Autonoma de Barcelona Materials Science PhD program.

We present a tri-gate In0.53Ga0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n-In0.53Ga0.47As channel doped to 1018/cm3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2O3 presents a bandgap of 7.0 eV, a k-value of 8.1 and a breakdown field of 8–10.5 MV/cm. A post-fabrication H2/Ar anneal applied to the PE-ALD Al2O3/In0.53Ga0.47As-OI gate stack yielded a low density of interface traps (Dit) of 7 × 1011/cm2 eV at Ec − E = −0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2O3/HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53Ga0.47As. The H2/Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2/Ar anneal, the long-channel (10 μm) device featured a threshold voltage (VT) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III–V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2/Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.

Display Omitted Highly crystalline BaTiO3 was integrated on Si using molecular beam epitaxy.Electro-optic response was evaluated for a-axis, c-axis, and mixed films.Increased a-axis fraction correlated with increased electro-optic response.Post-deposition oxygen anneal improved crystallinity and reduced leakage current. High-quality epitaxial BaTiO3 (BTO) on Si has emerged as a highly promising material for future electro-optic (EO) devices based on BTO's large effective Pockels coefficient. We report on the EO response of BTO films deposited on Si by molecular beam epitaxy (MBE), and characterize the structure of these films by reflection high-energy electron diffraction and X-ray diffraction. O2 rapid thermal anneal at 600?C for 30min ensures full oxidation of BTO for minimal leakage current with minimal change in crystalline structure.

arXiv:1802.07808v2, III-V semiconductor nanowires have shown great potential in various quantum transport experiments. However, realizing a scalable high-quality nanowire-based platform that could lead to quantum information applications has been challenging. Here, we study the potential of selective area growth by molecular beam epitaxy of InAs nanowire networks grown on GaAs-based buffer layers, where Sb is used as a surfactant. The buffered geometry allows for substantial elastic strain relaxation and a strong enhancement of field effect mobility. We show that the networks possess strong spin-orbit interaction and long phase-coherence lengths with a temperature dependence indicating ballistic transport. With these findings, and the compatibility of the growth method with hybrid epitaxy, we conclude that the material platform fulfills the requirements for a wide range of quantum experiments and applications., The project was supported by Microsoft Station Q, the European Research Council (ERC) under the grant agreement No.716655 (HEMs-DAM), the European Union Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement No 722176, the Danish National Science Research Foundation and the Villum Foundation. SMS acknowledges funding from >Programa Internacional de Becas >la Caixa>-Severo Ochoa>. JA and SMS also acknowledge funding from Generalitat de Catalunya 2017 SGR 327. ICN2 acknowledges support from the Severo Ochoa Programme (MINECO, Grant no. SEV-2013-0295) and is funded by the CERCA Programme / Generalitat de Catalunya.

In this paper, we introduce ${p}$ -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III–V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, ${I} _{\rm on}$ of 6 $\mu $ A/ $\mu $ m ( $|V_{GS}| = |V_{DS}| = 1$ V) and a room-temperature subthreshold swing ( SS ) of $\sim 160$ mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET ${I} _{\rm on}$ performance by 1–2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

1. Introduction As Si-CMOS scaling is becoming increasingly challenging, III-V compound semiconductors such as InxGa1-xAs (x≥0.53) (InGaAs) are receiving an increasing interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers. III-V integration on Si by direct wafer bonding is considered as one of the possible paths towards this objective [3]. Our rationale is that (1) InGaAs-on-insulator can be fabricated with the appropriate critical dimensions and thermal stability, (2) source wafers can be fabricated on large diameter wafers with acceptable defect densities and (3) hybrid substrates can be used to fabricate simple CMOS circuits. 2. InGaAs-on-Insulator A possible fabrication path for InGaAs-On-Insulator substrate is summarized. For demonstration purposes, the source substrate can simply be etched. A manufacturable process will however rely on the H-induced thermal splitting, as demonstrated in [3]. For thin layers as required for advanced CMOS, the thickness of InGaAs-o-I is below the critical value determined by the thermal strain up to 600°C. In addition, the interface energy at the Al2O3-Si bonding interface is almost 1 J/m2, larger than the one determined for SiO2-Si bonding in SOI wafers [4]. Such structures can therefore undergo high temperature processes such as the regrowth of highly doped InGaAs source and drain. The thermal stability is illustrated by showing that the regrowth of InGaAs do not degrade the structural quality of the underlying ultra-thin InGaAs-o-I. Functional self-aligned devices have been processed down to short gate length Lg=24nm, demonstrating the stability of such structures [5]. 2. Large diameter source wafer For VLSI integration, the bonding flow must be available for large diameters. As no InP substrate is available above 4”, the only possibility is to grow a virtual donor wafer onto a large diameter silicon substrate. Low defect density as well as very low roughness is required. In our internal work, GaAs deposition is performed by MBE on 200mm Ge/Si (001) substrate 6° off-cut, and subsequent pseudomorphic InxAl1-xAs grading buffer (x~ 0-0.65) allows reaching InP lattice-matching conditions. The formation of a thin InGaAs active layer completes the heterostructure that is compatible with the direct wafer bonding process. The best rms/TDD values reported so far are for GaAs 1nm/low-107cm-2 , and for InGaAs 2nm/mid-108cm-2. , close to the best value reported so far for Aspect Ratio Trapping methods. Excellent device metrics have been obtained on such heterostructures, supporting the idea that they can be used as donor wafers. 3. Hybrid circuits Based on the previous results, the co-integration of fully depleted InGaAs and SiGe MOSFETs can be envisioned. Starting from an 8 nm thick ETSGOI wafer, a 6 nm thick InGaAs layer can be transferred as in [6]. Because of the low temperature used during wafer bonding, and due to the presence of the BOX, cross-diffusion between InGaAs and SiGe is inhibited. The n- and p- active regions are defined based on mesa definition in the InGaAs and SiGe layer. The rest of the process follows an ETSOI-like front-end where n- and p-FETs are processed simultaneously. Such an hybrid structure is shown, for which a simplified process has been utilized, including a common gate stack and metal source drain instead of raised source/drain. The device characteristics have been extensively reported in [6], and a typical inverter transfer characteristic has been obtained, leading to the first demonstration of hybrid CMOS circuits based on high mobility channels. [1] J. Lin, D. A. Antoniadis and J. A. Del Alamo, IEDM Tech. Dig. (2012) [2] M. Radosavljevic, G. Dewey, D. Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, S. Kabehie, J. Kavalieros, V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, H. W. Then and Robert Chau, IEDM Tech. Dig. (2011) [3] L. Czornomaz, N. Daix, D. Caimi, M, Sousa, R. Erni, M. D. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart and J. Fompeyrine, IEDM Tech. Dig. (2012) [4] N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa and J. Fompeyrine, S3S conference 2013 [5] L. Czornomaz, et al., Proc. ESSDERC 2013 [6] L. Czornomaz, et al., IEDM Tech Digest (2013)

In0.53Ga0.47As based capacitors and self-aligned transistors fabricated with HfO2/Al2O3/Si gate stacks in a gate-first process flow show promising electrical properties. With in-situ and ex-situ characterization methods, we review systematically the physical and chemical properties of the whole multilayered stack. Especially, critical instabilities which may potentially limit the achievement of sub-nanometer capacitance equivalent thickness and a low interface state density are described in detail. Finally we propose some alternative solutions to avoid the observed instability paths.

We report on the maskless integration of micron-sized GaAs crystals on patterned Si substrates by metal organic vapor phase epitaxy. In order to adapt the mismatch between the lattice parameter and thermal expansion coefficient of GaAs and Si, 2 μm tall Ge crystals were first grown as virtual substrate by low energy plasma enhanced chemical vapor deposition. We investigate the morphological evolution of the GaAs structures grown on top of the Ge crystals at the transition towards full pyramids with energetically stable {111} facets. A substantial release of strain is shown in GaAs crystals with a height of 2 μm and lateral sizes up to 15×15 μm2 by both X-ray diffraction and photoluminescence.

The tuning of the optical and electronic properties of semiconductor nanowires can be achieved by crystal phase engineering. Zinc-blende and diamond semiconductors exhibit pressure-induced structural transitions as well as a strong pressure dependence of the band gaps. When reduced to nanoscale dimensions, new phenomena may appear. We demonstrate the tuning of the optical properties of GaAs nanowires and the induction of a phase transition by applying an external pressure. The dependence of the E-0 gap on the applied pressure was measured, and a direct-to-indirect transition was found. Resonant Raman scattering was obtained by pressure tuning of the E-0 and the E-0 + Delta(so) gaps with respect to the excitation energy. The resonances of the longitudinal optical modes L0 and 2L0 indicate the presence of electron-phonon Frohlich interactions. These measurements show for the first time a variation of ionicity in GaAs when in nanowire form. Furthermore, the dependence of the lattice constant on applied pressure was estimated. Finally, we found a clear indication of a structural transition above 16 GPa.

InAs quantum dot arrays are obtained on GaAs nanowire facets by molecular beam epitaxy. The GaAs nanowires are first grown by the gallium-assisted catalyst-free method. Decoration of the nanowire facets with InAs quantum dots is achieved only when the facets are capped with an ultrathin AlAs layer, as demonstrated by atomic force, high-resolution electron microscopy, and energy-dispersive X-ray spectroscopy line scans. The excitation of single and double excitons in the quantum dots are demonstrated by low-temperature photoluminescence spectroscopy realized on the single nanowires. This new type of heterostructures opens a new avenue to the fabrication of highly efficient single-photon sources, novel quantum optics experiments, as well as the realization of intermediate-band nanowire solar cells for third-generation photovoltaics.

Doped catalyst-free GaAs nanowires have been grown by molecular beam epitaxy with the gallium-assisted method. The spatial dependence of the dopant concentration and resistivity have been measured by Raman spectroscopy and four point electrical measurements. Along with theoretical considerations, the doping mechanisms have been revealed. Two competing mechanisms have been revealed: dopant incorporation from the side facets and from the gallium droplet. In the latter incorporation path, doping compensation seems to play an important role in the effective dopant concentration. Hole concentrations of at least 2.4 x 10(18) cm(-3) have been achieved, which to our knowledge is the largest p doping range obtained up to date. This work opens the avenue for the use of doped GaAs nanowires in advanced applications and in mesoscopic physics experiments.

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record I ON (118 µA/µm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better I on and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-I ON .

Display Omitted 50nm InGaAs on insulator layers successfully transferred using wafer bonding.We fabricated semiconductor/insulator/semiconductor capacitor structures.CV characteristics were measured and compared to simulated small ac signal CVs.This approach is suitable for the study of the insulator/InGaAs bottom interface. The electrical properties of Au/Ni/In0.53Ga0.47As/Al2O3/SiO2/Si structures were investigated using capacitance voltage (C-V) analysis. The properties of the InGaAs on insulator structures were analysed by comparing the measured and the theoretical C-Vs obtained using a physics based simulation of this structure. The results show that the measured data obtained on both n-type and p-type silicon match very well the simulated data. This work also shows that this approach allows the characterisation of charges in the buried oxide as well as interface states at the bottom InGaAs/Al2O3 interface.

A tri-gate In 0.53 Ga 0.47 As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In 0.53 Ga 0.47 As channel doped to 1018 /cm3 obtained by direct wafer bonding and a 3.5-nm-thick A1 2 O 3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W fin ) and gate length (L g ) scaling at fixed channel doping (N d ) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kane's tunneling model for direct bandgap (E g ) materials and compare it with experimental results. Moreover, studying the activation energy (E A ) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.

As Si-CMOS scaling has become increasingly challenging, III-V compound semiconductors such as In x Ga 1-x As (x≥0.53) (InGaAs) are receiving much interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers.

Direct wafer bonding can be a vehicle for the dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. Like for SiGe, direct wafer bonding enable the fabrication of fully depleted transistors having superior electrostatic control over the channel. Hybrid substrates can be also fabricated by direct wafer bonding with stacked ultra-thin high-mobility layers. A process flow allows fabricating n- and p-channel field effect transistors with ultra-thin body and BOX on the same wafer. Working CMOS inverters are obtained using a common front-end.

In this work, we show for the first time that VLSI-like gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (SID) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short L G .

In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In 0.53 Ga 0.47 As MOSFETs with silicon. We first demonstrate that the transfer of high-quality InGaAs / InAlAs heterostructures (t ch < 10 nm) can be achieved by direct wafer bonding and hydrogen-induced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600oC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL) against state-of-the-art III-V-o-I or Tri-Gate FET data.

We have demonstrated the first InGaAs MOSFETs with sub-nm EOT featuring a gate-first implant-free process compatible with VLSI. At L G = 65 nm, these devices are among the best reported ones in terms of electrostatic integrity but they suffer from a large access resistance related to a large gate-to-source/drain spacing. Future work will focus on scaling this spacing in the 5 nm range in order to achieve the desired on-performance.

Multiple seed formation by three-dimensional twinning at the initial stages of growth explains the manifold of orientations found when self-catalyzed GaAs nanowires grow on silicon. This mechanism can be tuned as a function of the growth conditions by changing the relative size between the GaAs seed and the Ga droplet. We demonstrate how growing under high V/III ratio results in a 100% yield of vertical nanowires on silicon(111). These results open up the avenue towards the efficient integration of III–V nanowire arrays on the silicon platform.

In this paper we introduce a new paradigm for nanowire growth that explains the unwanted appearance of parasitic nonvertical nanowires. With a crystal structure polarization analysis of the initial stages of GaAs nanowire growth on Si substrates, we demonstrate that secondary seeds form due to a three-dimensional twinning phenomenon. We derive the geometrical rules that underlie the multiple growth directions observed experimentally. These rules help optimizing nanowire array devices such as solar or water splitting cells or of more complex hierarchical branched nanowire devices.

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Taboada, A. G. et al., We report on the mask-less integration of GaAs crystals several microns in size on patterned Si substrates by metal organic vapor phase epitaxy. The lattice parameter mismatch is bridged by first growing 2-μm-tall intermediate Ge mesas on 8-μm-tall Si pillars by low-energy plasma enhanced chemical vapor deposition. We investigate the morphological evolution of the GaAs crystals towards full pyramids exhibiting energetically stable {111} facets with decreasing Si pillar size. The release of the strain induced by the mismatch of thermal expansion coefficients in the GaAs crystals has been studied by X-ray diffraction and photoluminescence measurements. The strain release mechanism is discussed within the framework of linear elasticity theory by Finite Element Method simulations, based on realistic geometries extracted from scanning electron microscopy images. © 2014 AIP Publishing LLC., Financial support by the Swiss Federal Program Nano-Tera through projects NEXRAY and COSMICMOS and Spanish MINECO and CAM through projects EPIC-NANOTICS and Q&C Light are gratefully acknowledged.

The unambiguous measurement of carrier concentration and mobility in semiconductor nanowires remains a challenging task. This is a consequence of their one-dimensional nature and the incompatibility with Hall or van der Pauw measurements. We propose a method that allows the direct determination of mobility and carrier concentration in nanowires in a contact-less manner. We demonstrate how forward Raman scattering enables the measurement of phonon-plasmon interactions. By applying this method to p-type GaAs nanowires, we were able to directly obtain values of the carrier concentration between 3.0 × 10(17) and 7.4 × 10(18) cm(-3) and a mobility of 31 cm(2) (V s)(-1) at room temperature. This study opens the path towards the study of plasmon-phonon interactions in semiconductor nanowires.

The thermal properties of freely suspended GaAs nanowires are investigated by applying a method which relies on laser heating and the determination of the local temperature by Raman spectroscopy. In order to determine the values for the thermal conductivity kappa, the fraction of the laser power absorbed inside the GaAs nanowire is estimated by numerical simulations. The thermal conductivity of nanowires with homogeneous diameter is found to lie in the range of 8-36 W m(-1) K-1. The change of the temperature profile in the presence of a tapering was investigated. Furthermore, we discuss the influence of laser heating in ambient conditions on the value of kappa. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3532848]

P-type gallium arsenide nanowires were grown with different silicon doping concentrations. The incorporation is monitored by Raman spectroscopy of the local vibrational modes. For Si-concentrations up to 1.4×1018 cm−3, silicon incorporates mainly in arsenic sites. For higher concentrations, we observe the formation of silicon pairs. This is related to the Coulomb interaction between charged defects during growth. An electrical deactivation of more than 85% of the silicon acceptors is deduced for nominal silicon concentration of 4×1019 cm−3. This work is important to understand the limiting mechanisms of doping in compound semiconductor nanowires.

Cleaved edge overgrowth and selective area epitaxy were combined for the synthesis of InAs quantum dot (QD) arrays with lateral sizes from 20 to 40 nm. The optical properties were locally assessed by confocal photoluminescence spectroscopy experiments at liquid helium temperature. The emission lines redshift as the lateral size of the QDs is increased. In agreement with a narrow size distribution, significantly narrow emission lines are observed for measurements in QD ensembles. Excitation power dependent luminescence measurements were realized on QD ensembles. A shell filling behavior was observed. The same measurements realized on single QDs led to the observation of multiple excitonic effects. Polarization dependent luminescence measurements indicate the existence of in-plane optical anisotropy, which strictly follows in-plane morphological anisotropy of the QDs. These results are encouraging for the use of quantum dot arrays in quantum information science and technology, as well as for new device concepts.