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Silicon carbide (SiC) vertical-diffused metal oxide field transistor (VDMOSFET) is an important power device for aerospace application. However, it is sensitive to heavy particles radiation in space which can cause catastrophic single-event effects (SEEs). In this article, a method of SEE hardening at a high linear energy transfer (LET) value range is studied to the 1.2 kV-rated SiC VDMOSFET by the 2-D numerical simulator SILVACO TCAD. Simulation results illustrate that, compared with the VDMOSFET which only has four buffer (FB-VDMOSFET) layers, the improved MOSFET could increase the abilities of single-event burnout (SEB) and the single-event gate rupture (SEGR) of the device effectively. At the same time, the proposed MOSFET has the lower specific ON-resistance (${R}_{\text {on, sp}}$) at room temperature. As a result, the gate oxide of the FB-VDMOSFET has reached 7.5 MV/cm and the maximum temperature reached 2480 K at a voltage of 600 V and an LET value of 0.5 pC/ $\mu \text{m}$. However, the maximum temperature of the improved VDMOSFET is 2150 K when ${V}_{\mathrm {DS}}$ = 950 V. [ABSTRACT FROM AUTHOR]

In this work, the single-event burnout (SEB) and degradation behaviors induced by heavy-ion irradiation were investigated in an 80-V-rated SEB-hardened split-gate trench (SGT) power U-shaped metal-oxide-semiconductor field-effect transistor (UMOSFET). After SEB hardening, the SEB failure threshold voltage of the sample device was measured to be 90 V; furthermore, a permanent degradation of the drain leakage or gate leakage was found after irradiation when the reverse voltage exceeded 60 V. The simulation results demonstrate that the heavy-ion-induced transient high temperature is a common mechanism responsible for the severe degradation and the catastrophic SEB. In addition, an effective method to improve the degradation and SEB tolerances, which enhances the rated breakdown voltage of a device, was proven through simulations. [ABSTRACT FROM AUTHOR]

This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power metal–oxide–semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion’s strike position to SEB is proved to be the edge of the P+/P− JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure’s 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one. [ABSTRACT FROM AUTHOR]

In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/μm and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters. [ABSTRACT FROM AUTHOR]

This paper proposes a new breakdown-enhanced gallium nitride (GaN) metal–insulator–semiconductor field-effect transistor (MISFET) with the architecture of a double channel and a P-buried layer, i.e. DCP-MISFET. The lower barrier and lower channel are connected to the drain, and the lower two-dimensional electron gas can improve the device electric field distribution between the gate and drain, achieving an enhanced breakdown voltage. At the same time, the P-buried layer below the gate field plate can reduce the peak electric field around the gate field plate. The proposed simulated device with LGD = 15 μm presents an excellent breakdown voltage of 2373 V. In addition, the ON-resistance of 15.07 s Ω mm and Baliga's figure of merit of 3.736 GW cm−2 are achieved in the optimized DCP-MISFET. Compared with the breakdown voltage of 1547 V of the optimized field plate conventional GaN MISFET, the proposed device increases the breakdown voltage by 53.39% and the Baliga's figure of merit is enhanced by 133.89%. [ABSTRACT FROM AUTHOR]

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure. [ABSTRACT FROM AUTHOR]

A silicon-on-insulator (SOI) lateral double-diffused MOSFET (LDMOSFET) with a buried field plate (BFP-LDMOS) is proposed. Its characteristics are studied using 2-D simulations. The proposed structure features double buried field plates which are surrounded by buried oxide (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents a premature breakdown at the interface of the silicon/BOX and enhances the dielectric field. The source buried field plate (SBFP) introduces a new electric-field peak and modulates the distribution of the horizontal electric field. In addition, the BFPs replace part of the BOX, which is useful to minimize self-heating effects (SHE). According to the simulation results, compared to a conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V. The specific on-state resistance ( R on,sp ), however, decreases from 20.46 mΩ cm 2 to 18.50 mΩ cm 2 . Moreover, the maximum lattice temperature at 1 mW/μm and V gs = 10 V is reduced by 33.8 K compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

In this paper, a SiC LDMOS with double L-shaped buried oxide layers (DL-SiC LDMOS) is investigated and simulated. The DL-SiC LDMOS consists of two L-shaped buried oxide layers and two SiC windows. Using 2-D numerical simulation software, Atlas, Silvaco TCAD, the breakdown voltage, and the self-heating effect are discussed. The double-L shaped buried oxide layers and SiC windows in the active area can introduce an additional electric field peak and make the electric field distribution more uniform in the drift region. In addition, the SiC windows, which connect the active area to the substrate, can facilitate heat dissipation and reduce the maximum lattice temperature of the device. Compared with the BODS structure, the DL-SiC LDMOS and BODS structures have the same device parameters, except of the buried oxide layers. The simulation results of DL-SiC LDMOS exhibits outstanding characteristics including an increase of the breakdown voltage by 32.6% to 1220 V, and a low maximum lattice temperature (535 K) at room temperature. [ABSTRACT FROM AUTHOR]

In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain ( A V ), cutoff frequency ( f T ), and maximum oscillation frequency ( f \mathrm{MAX} ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed. [ABSTRACT FROM AUTHOR]

The performance for P + Sidewall Trigate Junctionless nanowire MOSFET is investigated. The new device has a P + sidewall near the source. A comprehensive device comparison includes the subthreshold slope (SS), Drain-induced barrier lowering (DIBL) and the stability for threshold voltage (V TH ). High performance for SS and low leakage currents can be achieved by P + sidewall JL. As a result, SS nearly at 70 mV/dec, I ON /I OFF > 10 6 , and DIBL nearly at 60 mV are achieved at L G = 10 nm for P + sidewall JL NMOSFET, which is the highlighting excellent electrostatic performance for trigate JL NW MOSFEETs. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a new silicon-on-insulator superjunction lateral double-diffused MOSFET (SOI SJLDMOS) with a p-trench layer and stepped buried oxide, is investigated using 3D numerical simulation. The p-trench layer and stepped buried oxide distinguish it from a conventional SOI SJLDMOS. The etched buried oxide layer, with its stepped buried -oxide structure, which facilitates a more even electric field distribution via the electric field modulation effect, increases the breakdown-voltage (BV). Furthermore, the p-trench layer improves the doping concentration through compensation depletion, which further decreases the specific on-resistance (R on,sp). The simulation indicates that the new device has a higher BV (increased by 29%) than the conventional SOI SJLDMOS. At the same time, R on,sp decreases by 20% for the on-state for a given drift-region length. Highlights • A new SOI SJ LDMOS with p-trench and stepped buried oxide is proposed. • The p-trench layer for a higher doping concentration and lower on-resistance of the device. • The stepped buried oxide layer modulates the electric field distribution more uniform. • A 29% increase in the breakdown voltage for the SOI BSJ-PT LDMOS device. • A 20% decrease in the specific on-resistance for the SOI BSJ-PT LDMOS device. [ABSTRACT FROM AUTHOR]