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Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) responses are investigated for 3-D-sequentially integrated fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Strong layer-to-layer coupling of TID response is observed. The simultaneous application of positive bias to the gate of the bottom-layer device and negative bias to the top-layer device leads to the maximum enhancement of positive charge trapping in the top-layer device and the intermediate dielectric layer. This enhancement is due to the upward-directed electric field in the intermediate dielectric layer under these bias conditions. In contrast, electrostatic shielding prevents the gate bias of the top-layer device from affecting the response of the bottom-layer device, as confirmed by experiments and technology computer-aided design (TCAD) simulations. Effects of layer-to-layer coupling are less significant for postirradiation-biased annealing. [ABSTRACT FROM AUTHOR]

Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-around (GAA) nanowire (NW) devices are characterized for different biasing conditions. Negative-bias-stress-induced degradation in Ge GAA device originates primarily from the interface- and border-trap generation. Devices stressed at high gate voltage show rapid initial degradation and quick saturation dominated by interface-trap generation. Radiation-induced OFF-state leakage current in Ge GAA NWs increases with dose due to enhanced band-to-band tunneling (BTBT) caused by charge trapping in the shallow trench isolation (STI). [ABSTRACT FROM AUTHOR]

Peak transient currents due to pulsed-laser or heavy-ion irradiation of Ge $p$ MOS FinFETs are nearly independent of gate bias. This is because the prompt photocurrent is due primarily to a transient source–drain shunt. In contrast, long-term diffusion charge collection is strongly gate-bias dependent. This bias dependence results from hole injection from the source in response to the transient increase in electron concentration in the channel. The transients measured at the source terminal change polarity when the strike location moves from the source to the drain, but this effect does not occur for the transients measured at the drain terminal. Charge collection mechanisms are studied using TCAD simulations. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state for both silicon on insulator (SOI) and bulk devices. To first order, ionizing radiation does not interact strongly with programing-induced charges in the gate dielectric for either device type. Hole trapping in the buried oxide dominates the TID response of the 22-nm FDSOI devices. The 14-nm bulk devices with two fins and total effective fin widths of 150 nm are minimally affected by TID, but the subthreshold leakage of devices with 40 fins and total effective fin widths of $3~\mu \text{m}$ increases with increasing TID. When devices are programmed or reprogrammed after irradiation, significant increases in subthreshold slope are observed due to the generation of interface traps, border traps, and/or charge lateral nonuniformities. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in advanced bulk nMOS and pMOS FinFETs with SiO2/HfO2 gate dielectrics. Otherwise identical devices built with and without through-silicon via (TSV) integration exhibit threshold voltage shifts of less than 25 mV and changes in maximum transconductance of less than 1% up to 2 Mrad(SiO2). TSV integration negligibly impacts threshold shifts and degradation of subthreshold swing and $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratios. Similar low-frequency noise magnitudes and frequency dependencies are observed before and after TID irradiation for each device type. Effective densities of the near-interfacial electron traps responsible for the noise in the nMOS devices increase as the surface potential moves toward midgap, while effective densities of the hole traps that cause the noise in the pMOS devices increase as the surface potential moves toward the valence band edge. [ABSTRACT FROM AUTHOR]

The energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations. Excellent agreement is obtained with experimental current–voltage characteristics. For these 24-nm gate length devices, the electron distribution features a smeared energy peak with an extended tail. This extension of the tail results primarily from the Coulomb scattering within the channel. A fraction of electrons that enter the drain retains their energy, resulting in an out-of-equilibrium distribution in the drain region. The simulated density and average energy of the hot electrons correlate well with experimentally observed device degradation. We propose that the interaction of high-energy electrons with hydrogen-passivated phosphorus dopant complexes within the drain may provide an additional pathway for interface-trap formation in these devices. [ABSTRACT FROM AUTHOR]

Semiconductor–insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical mechanisms related to single-event effects has not been previously reported. We present experimental data that demonstrate that single-event charge collection can be impacted by changes in interface quality. The experimental data, combined with simulations, show that single-event response may depend on surface recombination at interface defects. The effect depends on strike location and increases with increasing linear energy transfer (LET). Surface recombination can affect single-event charge collection for interfaces with a surface recombination velocity (SRV) of 1000 cm/s and is a dominant charge collection mechanism with SRV $> 10^{5}$ cm/s. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage Vth shifts and subthreshold stretchout (SS), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and Id – Vgs measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of Vth and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO2/Al2O3 gate-stack. Transistors are irradiated up to 500 krad(SiO2) and annealed at high temperatures. Irradiated devices show negative threshold-voltage Vth shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor Vth shifts are due primarily to hole trapping at oxygen vacancies in HfO2, and the increased noise is due primarily to O vacancies in Al2O3. Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures. [ABSTRACT FROM AUTHOR]

A two-photon absorption technique is used to understand the mechanisms of single-event effects (SEEs) in silicon carbide power metal–oxide–field-effect transistors (MOSFETs) and power junction barrier Schottky diodes. The MOSFETs and diodes have similar structures enabling the identification of effects associated specifically with the parasitic bipolar structure that is present in the MOSFETs, but not the diodes. The collected charge in the diodes varies only with laser depth, whereas it varies with depth and lateral position in the MOSFETs. Optical simulations demonstrate that the variations in collected charge observed are from the semiconductor device structure and not from metal/passivation-induced reflection. The difference in the spatial dependence of collected charge between the MOSFET and diode is explained by bipolar amplification of the charge carriers in the MOSFETs. Technology computer-aided design (TCAD) device simulations extend this analysis to heavy-ion-induced charge collection. In addition, there is discussion comparing this analysis with experimental results from prior works that show enhanced charge collection resulting from heavy-ion irradiation. [ABSTRACT FROM AUTHOR]

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at $V_{\mathrm {G}} = -1$ V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. The 1/ $f$ noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose response of few layer MoS2 transistors with ZrO2 or h-BN gate dielectrics is investigated under various bias conditions. Defects in MoS2 and surrounding dielectric layers significantly affect radiation-induced trapping. For devices with ZrO2 dielectrics, much larger negative Vth shifts and peak transconductance degradation are observed for irradiation under negative and ground bias than under positive bias. The h-BN devices exhibit positive threshold voltage shifts under negative-bias irradiation. For both ZrO2 and h-BN passivated devices, the peak transconductance degradation results from charge trapping at the surface of the MoS2 or in nearby oxides. Changes in defect energy distributions of MoS2 FETs during X-ray irradiation are characterized via temperature-dependent low-frequency noise measurements. Density functional theory calculations are performed to provide insight into the pertinent defects. [ABSTRACT FROM AUTHOR]

The pulsed-laser single-event transient response of InGaAs FinFETs on bulk silicon substrates is investigated. Charge collection due to a source–drain shunt effect and drain-to-substrate junction charge collection contribute to the observed transients. The transient response of these silicon substrate devices is compared to that of InGaAs FinFETs on semi-insulating substrates. Faster transients with reduced peak currents and peak widths are observed on the silicon substrate devices. Simulations show hole collection by the silicon substrate. This reduces the amount of source-barrier lowering and bipolar-amplification relative to other III–V devices. Moreover, the reduced hole lifetime in the GaAs buffer layer also contributes to the relative reduction of the bipolar amplification in these devices. [ABSTRACT FROM AUTHOR]

Significant threshold voltage $V_{\mathrm {th}}$ shifts are observed during 10-keV X-ray irradiation of AlGaN/GaN high-electron mobility transistors (HEMTs). Shifts are much smaller for lower dose-rate Cs-137 irradiation than that for higher dose-rate X-ray irradiation. This occurs because hydrogen transport and interactions with defects and impurities in these crystalline wide bandgap semiconductor materials differ fundamentally from those in amorphous SiO2. The electric field is also higher in GaN-based HEMTs than in bipolar base oxides. The absence of enhanced low-dose-rate sensitivity in these devices simplifies testing of GaN-based HEMTs for space applications. No significant X-ray-induced $V_{\mathrm {th}}$ shifts are observed in development stage InAlN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

Gate and drain bias dependences of hot carrier degradation are evaluated for AlGaN/GaN HEMTs fabricated via two different process methods. Both positive and negative threshold voltage $V_{\mathbf{th}}$ shifts are observed for each device type, depending on the mode and duration of the stress, indicating the presence of significant densities of donor-like and acceptor-like traps. Worst-case stress bias for transconductance degradation is the “ON” state for both device types. We find that transconductance degradation provides a more effective parameter to monitor defect buildup than $V_{\mathbf{th}}$ shifts, and that a single worst-case stressing bias condition cannot be defined for all varieties of AlGaN/GaN HEMTs. Low-frequency noise measurements versus temperature assist the identification of defects responsible for the observed degradation. Defect dehydrogenation and oxygen impurity centers are found to be particularly significant to the response of these devices. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal–dielectric interfaces, and enhanced electron–hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions. [ABSTRACT FROM PUBLISHER]

We use capacitance–frequency ( $C$ – $f$ ) measurements to provide lower bound estimates of border-trap densities in multifin MOS capacitors with high-K dielectrics built in Ge and InGaAs fin field effect transistor (FinFET) technologies before and after X-ray irradiation. The $C$ – $f$ method is illustrated for SiO2-based planar MOS capacitors and compared with high-frequency capacitance–voltage measurements. Lower effective border-trap densities are found before and after irradiation for multifin capacitors built in a strained Ge $p$ MOS FinFET technology than for similar devices built using an early-developmental stage InGaAs MOS technology. These results show the utility of $C$ – $f$ measurements in characterizing defect densities in MOS capacitors, particularly when large border-trap densities exist. [ABSTRACT FROM PUBLISHER]

The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. Ionization in the spacer oxide and overlying silicon nitride layers above the lightly doped drain extensions leads to charge buildup as well as the ionization and/or release of hydrogen. Charge trapped in the spacer oxide or at its interface modifies the parasitic series resistance, reducing the drive current. The released hydrogen transports as H+ with an activation energy of ~0.92 eV. If the direction of the electric field is suitable, the H+ can reach the gate oxide interface and depassivate Si-H bonds, leading to threshold voltage shifts. Newly created interface traps are most prominent near the source or drain. The resulting transistor responses and defect-energy distributions often vary strongly in space and energy as a result, as demonstrated through current–voltage, charge-pumping, and low-frequency noise measurements. [ABSTRACT FROM PUBLISHER]

The influence of surface carrier concentration on the ideality factor of excess base current ( \Delta IB ) in gated lateral PNP (GLPNP) bipolar junction transistors (BJTs) induced by 1-MeV electrons is investigated. \Delta IB in LPNP BJTs is impacted by the surface carrier density and radiation-induced interface traps. In GLPNP BJTs, the surface carrier concentration can be controlled by the voltage applied to a gate over the base region. The ideality factor changes after irradiation, and its dependence on emitter-base voltage ( V\mathrm {EB} ) is a function of gate voltage. For the irradiated devices, as the gate voltage decreases from +20 to −5 V, the ideality factor for excess base current changes from a single slope to two-slope behavior. The majority carrier concentration at the surface of the base, controlled by the gate voltage, impacts the excess base current and its ideality factor. [ABSTRACT FROM AUTHOR]

We have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO2) show minimal transconductance degradation (less than 5%), very small \text {V}_{th} shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p$ MOS FinFETs is far superior to that of past generations of planar Ge $p$ MOS devices. These improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology. [ABSTRACT FROM PUBLISHER]

We find that the low-frequency 1/ f noise of AlGaN/GaN HEMTs before and after 1.8-MeV proton irradiation is more consistent with a carrier-number fluctuation model that includes a non-constant defect-energy distribution {D}_{t} ( {E}_{f} ) than with the Hooge mobility fluctuation model. A strongly varying Dt ( {E}f ) in these devices is confirmed by measurements of the voltage and temperature dependence of the noise. First-order estimates of effective border-trap density before and after 1.8-MeV proton irradiation are obtained for commercial and research-grade devices using a simple number-fluctuation model. The input-referred noise magnitude of GaN/AlGaN HEMTs decreases at biases that are much more positive than threshold because the gated region of the HEMT comprises a relatively small portion of the channel, and the noise is attenuated by the voltage divider formed by the gated and ungated regions of the channel. [ABSTRACT FROM PUBLISHER]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]

We have measured the low-frequency 1/ f noise of Si0.55Ge0.45 p MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( \textitS {vd} ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device. [ABSTRACT FROM PUBLISHER]

We report the experimental data, quantum-mechanical calculations, and engineering-level modeling that provide insight into the atomic-scale processes that underlie the hot-electron degradation of AlGaN/GaN high-electron-mobility transistors during electrical stress at moderate drain bias. There is relatively large degradation (up to 20%) of the peak transconductance ( gm ) in the semi-ON state, along with a small shift of the threshold voltage ( VT ). The VT shift and gm degradation increase with temperature. A model of the degradation is presented, based on the hot-carrier-induced defect generation. The model considers carrier energy distributions for different temperatures obtained using an ensemble Monte Carlo (EMC) approach. The Ensemble Monte-Carlo results show that the concentration of energetic carriers is maximum at the end of the gate on the gate–drain access side in the semi-ON state of operation. The degradation is directly related to the number of carriers with sufficient energy to generate defects, and the carrier energy distribution depends strongly on the device temperature. The first-principles density functional theory calculations and the analysis suggest that the dehydrogenation of substitutional iron and its complexes is the dominant cause of the observed degradation in these devices. [ABSTRACT FROM AUTHOR]

We investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics. The measured activation energies for interface-trap charge buildup during negative-bias temperature stress are lower for SiGe channel pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO 2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO 2/HfO 2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si–H bonds and that Ge–H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO 2/HfO 2 gate dielectrics and Si pMOSFETs with SiO 2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO 2. [ABSTRACT FROM PUBLISHER]

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms. [ABSTRACT FROM PUBLISHER]

The total-dose radiation tolerance of 32-nm nFETs is investigated. nFETs built in 32-nm RF-CMOS-on-SOI technology with high-k dielectrics show increased off-state leakage current and electron trapping in the gate oxide. The impact of CMOS-on-SOI technology scaling (from 65-nm to 32-nm) on the total-dose radiation tolerance and hot-carrier reliability (HCR) is investigated through both experiments and supporting TCAD simulations. The 32-nm nFETs exhibit less total-dose degradation compared to 45-nm nFETs. However, the hot-carrier degradation increases as the technology scales. An interplay of electric-field in the gate oxide and impact ionization in the channel region is responsible for the observed differences in the degradation mechanisms for the three technologies. [ABSTRACT FROM AUTHOR]

Monte Carlo analysis of hot-electron degradation in AlGaN/GaN high-electron mobility transistors shows that, for gate voltages corresponding to semi-ON bias conditions, the average electron energy has a spatial peak with \langleEAVE\rangle\sim1.5~\rm eV . The peak is located at the edge of the gate. At this location, the carrier versus energy distribution has a large tail extending over 3 eV. When transferred to the lattice, this energy can cause defect dehydrogenation and device degradation. These results are consistent with the experimental data indicating maximum degradation in the semi-ON bias condition. [ABSTRACT FROM AUTHOR]

Bias-temperature instabilities (BTIs) are investigated for n- and p-substrate 4H-SiC metal–oxide–semiconductor (MOS) capacitors. The midgap voltage (V \rm mg) shifts positively under positive bias stress at high temperatures for n-substrate capacitors with 67.5-nm nitrided oxides and shifts negatively under negative bias for p-substrate capacitors with 55-nm nitrided oxides. The magnitudes of the Vmg shifts are less than 0.5 V for electric fields of magnitudes of approximately \pm3.1 MV/cm for up to one day of stress at 150 ^\circ\C or 20 min of stress at 300 ^\circ\C. Switched-bias stressing at 150 ^\circ\C causes partially reversible shifts for the n-substrate capacitors, while the p-substrate capacitors show monotonically increasing negative shifts. Based on the measured temperature dependence of the Vmg shifts, the effective activation energy for BTI that is measured between room temperature and 250 ^\circ\C is 0.12 \pm 0.02 eV for the n-substrate capacitors (positive shifts) and 0.23 \pm 0.02 eV for the p-substrate capacitors (negative shifts). The midgap voltage shifts in these wide-bandgap devices are caused by charge capture at deep interface traps and N-related defects at or near the \SiC-\SiO2 interface, which can be enhanced at elevated temperatures by the generation of additional carriers due to the ionization of deep dopants in the SiC during bias-temperature stress. [ABSTRACT FROM PUBLISHER]

Irradiated Ge pMOSFETs have been characterized via charge pumping (ICP) and 1/f noise. The noise increases much more with irradiation than does ICP for devices with eight Si monolayers at the interface, while devices with five Si monolayers and lower halo implantation dose exhibit comparable increases in noise and ICP with irradiation. These results suggest that border traps in the HfO2 affect the noise more than interface traps, and that devices with eight Si monolayers have a higher border-trap density than devices with five Si monolayers. Noise measurements as a function of gate voltage show that the border trap density increases significantly toward the Ge valence band edge, while three-level charge pumping reveals an interface trap density that increases slightly toward midgap. [ABSTRACT FROM AUTHOR]

The total ionizing dose response of triple-gate MOSFETs is investigated for various fin widths and bias conditions. Experiments and simulations are used to analyze the buildup of trapped charge in the buried oxide and its impact on the threshold-voltage shift and subthreshold-slope degradation. The higher total-dose tolerance of multiple-gate FinFETs with narrow fins is attributed to lateral gate control over the electrostatic potential in the body and especially at the Si fin/BOX interface. It is demonstrated that ON-state irradiation is the worst-case bias configuration for triple-gate MOSFETs through extensive experimental analysis. [ABSTRACT FROM PUBLISHER]

The switched dose rate technique has been proposed as an accelerated test technique for enhanced low-dose-rate sensitivity. The physical mechanisms at play when this technique is applied are investigated in this paper. The variation of Not and Nit is characterized using gated lateral pnp transistors to understand the kinetics of device degradation related to differences in mechanisms between high dose rate and low dose rate irradiations. [ABSTRACT FROM PUBLISHER]

A physics-based TCAD model for enhanced low-dose-rate sensitivity in linear bipolar devices is developed. Quantitative agreement is found with measured data over a wide range of dose rates and H2 concentrations. Analysis of the degradation effects of individual defect types, the implementation of which has been informed by first principles calculations, provides insights into the mechanisms behind enhanced low-dose-rate effects in different hydrogen environments. The effects of initial defect concentration and location and the energetics of the defect-related reactions are explored. Conclusions are drawn about the roles of molecular hydrogen and hydrogenated defects in the radiation response of these devices. [ABSTRACT FROM PUBLISHER]

We have evaluated the responses of graphene materials and devices to 10-keV X-ray irradiation and ozone exposure. Large positive shifts are observed in the current-voltage characteristics of graphene-on-\SiO2 transistors irradiated under negative gate bias. Moreover, significant radiation-induced increases are found in the resistance of suspended graphene layers; the charge neutral point (CNP) of the graphene layer also shifts positively with increasing total dose. Raman spectroscopy shows that similar defects are generated in graphene-on-\SiO2 sheets by 10-keV X-ray irradiation and ozone exposure. First principles calculations of the relevant binding energies, and reaction and diffusion barriers for oxygen on graphene, strongly suggest that oxygen adsorption and reactions, along with the resulting p-type doping, can lead to the observed degradation of irradiated or ozone-exposed graphene materials and devices. [ABSTRACT FROM PUBLISHER]

The irradiation and annealing responses of 4H-SiC MOS devices with nitrided oxides are investigated at varying biases. Radiation-induced hole trapping dominates the radiation response of these devices. Switching the bias between irradiation and annealing can lead to significant enhancement of the degradation in some cases. Positive irradiation bias followed by negative annealing bias is found to be the worst-case for the combined degradation. After irradiation, significant reversibility of charge trapping is observed in switched-bias annealing of n-substrate capacitors, while enhanced charge trapping is found in p-substrate capacitors. These results show the potential importance of evaluating the combined radiation and reliability responses of SiC MOS devices for long-term use in high total-ionizing-dose space applications. [ABSTRACT FROM PUBLISHER]

The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping. [ABSTRACT FROM PUBLISHER]

The irradiation and annealing responses of Ge pMOSFETs have been investigated under transmission gate bias. Both the radiation-induced charge trapping and the low frequency (1/ f ) noise increase with total ionizing dose and decrease with annealing time. The smallest increases in noise after irradiation are observed for Ge pMOSFETs with the lowest halo implantation doses. The smallest increases in oxide and interface trap charge densities are obtained for devices with eight monolayers of Si at the interface, as compared to devices with five Si monolayers. [ABSTRACT FROM AUTHOR]

InAs–AlSb high-electron mobility transistors stressed with hot carriers may exhibit shifts in the peak transconductance toward more negative gate-voltages. The devices are most degradation prone in operating conditions with high longitudinal (in the direction of IDS) electric fields in the channel. Room-temperature annealing, gate current, and channel-mobility measurements suggest the presence of a metastable defect in the top AlSb layer. Device simulations and first-principles quantum–mechanical calculations are used to investigate the physical nature of the defects responsible for degradation. Metastable configurations of substitutional and interstitial oxygen have charge states and transition energies consistent with the degradation trends. [ABSTRACT FROM PUBLISHER]

The radiation response of advanced non-planar multiple gate field effect transistors (MuGFETs) has been shown to have a strong dependence on fin width (W). The incorporation of total ionizing dose (TID) effects into a physics-based surface-potential compact model allows for the effects of radiation-induced degradation in MuGFET devices to be modeled in circuit simulators, e.g., SPICE. A set of extracted parameters are used in conjunction with closed-form expressions for the surface potential, thereby enabling accurate modeling of the radiation-response and its dependence on W. Total ionizing dose (TID) experiments and two-dimensional (2D) TCAD simulations are used to validate the compact modeling approach presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, heavy-ion-induced single-event transient (SET) pulsewidths measured in a 65-nm bulk CMOS technology at temperatures ranging from 25 ^\circ\C to 100 ^\circ\C with an autonomous SET capture circuit are presented. The experimental results for the SETs induced in two different inverter chain circuits indicate an increase in the average SET pulsewidth as a function of the operating temperature. Unique SET test structures were also designed to differentiate between SETs induced in an nMOS transistor and those induced in a pMOS transistor. The SET widths induced in a pMOS transistor increase more with temperature than the SETs induced in an nMOS transistor. [ABSTRACT FROM PUBLISHER]

The impact of total ionizing dose (TID) is reported on irradiated capacitorless metastable dip RAM (MSDRAM) cells, built in a planar SOI technology. The memory window shifts toward more negative voltages at higher doses. The unconventional gate current peak measured in MSDRAM cells decreases with dose and disappears at 500~\ krad(\ SiO2) for these devices. The retention time of the 0-state decreases with dose, with the greatest decrease for memory cells programmed with high back-gate voltages. The trapped charge in the 400-nm buried oxide changes the potential in the body and interferes with the ability to store a 0-state. The irradiated cells exhibit higher drain currents while reading the 1-state. This increase of the drain current is enhanced for longer programming times. [ABSTRACT FROM AUTHOR]

The 1.8-MeV proton radiation responses are compared for AlGaN/GaN HEMTs grown under Ga-rich, N-rich, and NH3-rich conditions. The NH3-rich devices are more susceptible to proton irradiation than the Ga-rich and N-rich devices. The 1/ f noise of the devices increases with increasing fluence. Density functional theory calculations show that N vacancies and Ga-N divacancies lead to enhanced noise in these devices. [ABSTRACT FROM AUTHOR]

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications. [ABSTRACT FROM AUTHOR]

Detailed studies of the temperature and voltage dependences of the low-frequency noise of 4H-SiC MOSFETs and TCAD simulations show that the noise is caused primarily by interface traps. First-principle calculations identify these traps as carbon vacancy clusters and nitrogen dopant atoms at or near the \SiC/SiO2 interface. [ABSTRACT FROM AUTHOR]