Search

In this paper, we achieved excellent variation control, endurance enhancement, and leakage reduction in zirconium (Zr)-doped hafnium oxide (Hf1–xZrxO2) based ferroelectric films by the germination ...

The lack of effective synthesis techniques for achieving wafer-scale uniformity and high crystallinity remains one of the major obstacles for two-dimensional (2D) layered materials in practical applications. 2D solid-phase crystallization (2DSPC) is proposed based on the area-scalable and semiconductor-process-compatible sputtering and thermal annealing techniques. It successfully synthesizes few-layer 2H-MoTe2 with a monocrystalline grain size exceeding half a centimeter on an amorphous substrate of silicon dioxide. The extremely large grain size is made possible through a two-step annealing process in an inert atmosphere. The initial rapid thermal annealing at high temperatures produces hexagonal monocrystalline 2H-MoTe2 seeds with low density and the subsequent long-duration furnace annealing at low temperatures enlarges the monocrystalline domains only from the pre-existing seeds. The 2DSPC mechanism and its morphological evolution agree with the classical nucleation theory and kinetic Wulff construction theory, respectively. Our result suggests the promising potential of 2DSPC as a simple yet effective route for synthesizing future wafer-scale, high-quality 2D materials.

The phonon transport in the lateral direction for gap-controlled Si nanopillar/SiGe interlayer composite materials was investigated to eliminate heat generation in the channel area for advanced MOS transistors. The gap-controlled Si NP/SiGe composite layer showed 1/100 times lower thermal conductivity than Si bulk. Then, the phonon transport behavior in lateral direction could be predicted by the combination between 3-omega measurement method for thermal conductivity and Landauer approach for phonon transport in Si NP/Si0.7Ge0.3 interlayer composite structure. We found that the NP structure could regulate the phonon transport in the lateral direction by changing the NP gaps. As such, this structure achieves the first step toward phonon transport management in the same electron transportation direction of planar-type MOSFETs and represents a promising solution to heat generation for advanced CMOS devices.

Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) technology, including future Ge-based technology. In this paper, we demonstrate Ge twin-transistor NVM with a fin field-effect transistor (FinFET) structure. This Ge twin-transistor NVM exhibits high programming and erasing speeds and satisfactory reliability. Moreover, the masks and fabrication process of this Ge twin-transistor NVM are identical to those of Ge-channel FinFETs. Thus, Ge twin-transistor NVM is a promising candidate for embedded NVM applications in future high-performance Ge complementary metal-oxide-semiconductor technology (CMOS).

The rapid reduction of feature size in CMOS devices causes their variability to increase, thus reducing the circuit yield [1]-[3]. In particular, the static random access memory (SRAM) cell uses the smallest transistor to achieve high-density integration, the effect of which is a lower yield [4]. The reduction of variability is, therefore, becoming the most important concern for CMOS devices. In this article, we review the effectiveness of introducing multigate devices and microwave annealing (MWA) for performance enhancement.

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

In this work, we studied the effects of microwave annealing process on amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and demonstrated a high performance and reliable device characteristics. The characteristic trapping time ( τ ) derived from stretched-exponential model was extracted to exhibit the quality improvement of a-IGZO thin film. The microwave annealing features a selective heating and potentially avoids the damage to materials neighboring the a-IGZO channel layer in TFT device structure during thermal processes, resulting in lower parasitic source to drain resistance.

Two-dimensional (2D) molybdenum ditelluride (MoTe2) exhibits an intriguing polymorphic nature, showing stable semiconducting 2H and metallic 1T′ phases at room temperature. Polymorphism in MoTe2 presents new opportunities in developing phase-change memory, high- performance transistors, and spintronic devices. However, it also poses challenges in synthesizing homogeneous MoTe2 with a precisely controlled phase. Recently, a new yet simple method using sputtering and 2D solid-phase crystallization (SPC) is proposed for synthesizing high-quality and large-area MoTe2. This study investigates the polymorphism control of MoTe2 synthesis using 2D SPC. The Te/Mo ratio and oxygen content in the as-sputtered films correlate strongly with the final phase and electrical properties of SPC MoTe2. Furthermore, the SPC thermal budget may be exploited for stabilizing a deterministic phase. The comprehensive experiments presented in this work demonstrate the versatile and precise controllability on the MoTe2 phase by using the simple 2D SPC technique.

For undoped

A twin FinFET structure non-volatile memory with high mobility germanium channel (Twin Ge FinFET structure NVM) is demonstrated. An extrapolation of the memory window can achieve 10V of V TH at 21V for 10−3s which is large enough for NVM application. And the memory window can be maintained at 1.5V after 103 P/E cycles. In the future, this novel twin Ge FinFET NVM give a new solution of embedded NVM for next-generation Ge-based FinFET MOSFET integrated circuit.

Highly reliable and low-cost long-period corrugation and phase gratings based on a cascade of phase-shifted lithium niobate waveguides are theoretically analyzed, experimentally realized and characterized in a logical sequence. The realization of these phase-shifted waveguide gratings (LPWG) is subsequently achieved via a two-step proton exchange method. The measurement results have demonstrated that the maximum dip contrast is up to 19.73 dB and the narrowest full-width-at-half-maximum (FWHM) is close to 2.34 nm. Furthermore, for the cascaded pi-phase-shifted long-period waveguide gratings (LPWG), the two resonance wavelengths are symmetrically shifted away from the center wavelength in response to an increase in the number of LPWG sections incorporated.

Among extensively researched 2D-TMDs, MoTe 2 is an emerging but understudied material because of the lack of reliable and reproducible synthesis methods. The difficulties of its synthesis originate from the weak Mo-Te bonding energy, which results in the low chemical reactivity of MoTe 2 . Additionally, compared with other TMDs, MoTe 2 is relatively unstable. It easily oxidizes and decomposes at high temperatures, which complicate the synthesis using conventional CVD. We have previously developed a PVD method capable of depositing large-area, high-crystallinity, few-layer 2D MoTe 2 without complex designs of gas-phase transport or Mo-Te chemical reaction. MoTe 2 is directly sputtered and post-annealed in a 2D encapsulation structure to improve its crystallinity. MoTe 2 can be synthesized in either homogeneous semiconducting 2H or metallic 1T’ phase by controlling the adequate thermal budget during annealing. This talk will mainly discuss the process optimization and electrical properties of 1T'-MoTe 2 , which is potentially important in several emerging research fields, including 2D interconnect, topological superconductor, and 2H-lT’ in-plane homojunction transistor.

Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 $\mu \text{A}/\mu \text{m}$ , a large current ON/OFF ratio of $> 5\times 10^{7}$ , and minimal short-channel effect using $V_{G}=2$ V and $V_{D}=1$ V.

We present a high-performance Si/Ge/Si p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) with a NiSiGe Schottky junction source/drain (S/D) formed through microwave-activated annealing. A Schottky contact S/D is preferable, because the lower process temperature is beneficial for eliminating Ge diffusion. The fabricated NiSiGe Schottky junction exhibited a high effective barrier height ( $\Phi _{\textrm {Bn}}$ ) of 0.69 eV for electrons, resulting in a high junction current ratio of more than $10^{5}$ at the applied voltage of $|V_{a}|=1$ V. Our quantum-well pMOSFET exhibited a high $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 10^{7}$ ( $I_{S}$ ) and a moderate subthreshold swing of 166 mV/decade.

This work investigates the characteristics of ohmic contacts on an n-type Ge by combining TiO2 with different metals. Metal-insulator-semiconductor (MIS) structures easily crystallize after post-metal annealing (PMA), with the subsequent characteristics dependent on the insulator thickness and process temperature. If 2 nm thick TiO2 is doped with nitrogen, there is no obvious difference in the current-voltage characteristics before/after PMA. The transmission electron microscope (TEM) analysis also verified that a lightly nitrogen-doped process is useful in suppressing the crystalline transition. In this study, the tungsten (W) contact showed the best thermal stability. Therefore, this technique could be effective in suppressing TiO2 crystallization with improved thermal stability.

In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 °C, steeper S.S. and Ion/Ioff>107 could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 °C possessed lower Ioff and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length ( $\lambda $ ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage ( $\mathrm{V}_{\mathrm {\mathbf {BTBT}}}$ ) indicates clearly that TFET annealed by MWA had a lower $\lambda $ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of $10^{\mathrm {\mathbf {8}}}$ , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.

In this study we use chemical and physical vapor depositions to fabricate amorphous silicon (a-Si) films. We also use traditional rapid thermal annealing (RTA) and advanced microwave annealing (MWA) to activate or crystallize a-Si films and then observe their sheet resistances and crystallization. We discovered, although the cost of films fabricated by electron beam (e-beam) evaporation is relatively lower than by chemical vapor deposition (CVD), the effects of the former method are poorer whether in sheet resistance or film crystallization. In addition, only at the doping layer prepared by CVD can film crystallization degree produced by MWA match RTA.

In this paper, we used the electron beam (e-beam) evaporation to deposit Ge thin film on glass, and used microwave annealing (MWA) system of 5.8 GHz frequency for thin film crystallization. Then, we compared the MWA experiment results of sample sheet resistance (Rs), crystallization strength and cross section with those using traditional rapid thermal annealing (RTA) equipment. We found that MWA can get poly-Ge thin film with (111), (220) and (311) crystallization directions and optimal Rs at a temperature of about 450 ° C without affecting the film thickness. By comparison, RTA equipment can only reduce the sample Rs at least temperature of 550oC.

P-i-n single-junction hydrogenated amorphous silicon (a-Si:H) thin film solar cells were successfully fabricated in this study on a glass substrate by high density plasma chemical vapor deposition (HDP-CVD) at low power of 50 W, low temperature of 200°C and various hydrogen dilution ratios (R). The open circuit voltage (Voc ), short circuit current density (Jsc ), fill factor (FF) and conversion efficiency (η) of the solar cell as well as the refractive index (n) and absorption coefficient (α) of the i-layer at 600 nm wavelength rise with increasing R until an abrupt drop at high hydrogen dilution, i.e. R > 0.95. However, the optical energy bandgap (Eg ) of the i-layer decreases with the R increase. Voc and α are inversely correlated with Eg . The hydrogen content affects the i-layer and p/i interface quality of the a-Si:H thin film solar cell with an optimal value of R = 0.95, which corresponds to solar cell conversion efficiency of 3.85%. The proposed a-Si:H thin film solar cell is expected to be improv...

Ge-epi on Si wafers contain >1E7/cm2 TDD which degrades junction leakage and potentially also degrade mobility. Therefore we investigated using Ge-Cz wafers as an alternative free of Ge-epi TDD and observed that surface Sn implantation up to 16% can induce surface tensile strain-Ge measured by XRD enhancing top 30nm n-well surface layer mobility (µe) by 2.5x from 500cm2/Vs up to 1250cm2/Vs but the surface tensile strain-Ge degraded top 30nm p-well surface layer mobility (µh) by 73% from 3000cm2/Vs to 800cm2/Vs and surface bulk mobility by 74% from 1850cm2/Vs to 480cm2/Vs.

In this paper, microwave assisted annealing (MWAA) technique on atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) fabricated indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) is investigated for the first time. MWAA with 300W for 100sec treatment on AP-IGZO TFTs have been fabricated successfully and show excellent electrical characteristics including a VTH of −1.23 V, SS of 0.18 V/dec, µFE of 17.4 cm2/V-s, and Ion/Ioff ratio of 8.14 106. Stretched exponential time dependence model is used to analyze the mechanism of AP-IGZO TFTs under PBTI stress. Accordingly, chemisorption model for oxygen adsorption at AP-IGZO backchannel with and without MWAA is proposed to explain the mechanism under PBTI stress.

A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth ( 107) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.

Local and selective far-infrared ray laser annealing (FIR-LA) process with very short heating duration ( 5×104) and small DIBL. Furthermore, the thus fabricated low driving voltage 6T SRAM shows a static noise margin (SNM) of 130 mV at Vd=0.4V enabling the low power and low cost 3D+IC for internet of things (IoTs).

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550nm. The three different modulation lengths (ML) of 500, 1000, and 2000µm while keeping the overall MZI length constant at 1.5cm were set as a general design rule for these 10µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50mA current (Is) to achieve a π phase shift, the modulation efficiency of the device was measured to be η =π/(Is·L) $\\simeq$ 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5µsec and the 3dB roll-off frequency (f3dB) measured was in the excess of ∼400kHz.

This study examines the effects of plasma-induced damage (PID) both on advanced SiO 2 /poly-gate and Hf-based high- k /dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high- k /metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high- k /metal-gate CMOS technology.

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventionalSiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Metal-oxide-semiconductor capacitors with HfAlO high-k gate dielectric deposited by Atomic Layer Deposition (ALD) and SiGe channel were studied in this work. A thin Si layer was also grown upon SiGe channel layer as a capping layer to form a Si/SiGe/Si structure on substrate. Different Ge contents from 7% to 32% in SiGe channel on electrical characteristics of MOS device were investigated. Based on gate leakage and reliability properties of MOS devices, the optimal Ge content in SiGe channel to achieve enough mobility enhancement is around 20%. The improvement of electrical characteristics includes low leakage current, small EOT value and good reliability.

We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO"2) dielectric stack (equivalent oxide thickness=2.63nm) in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model.

A flow formed C-250 maraging steel tubing was welded by electron beam welded (EBW) process and subsequently age hardened. Conventional EB welding with high energy input had resulted in seriously inadequate percentage elongation of the weldment. With an additional prewelding stress relief treatment and EBW with a lower energy input, the elongation of the weldment showed significant improvement after being treated with age hardening. It was found that the tensile strength was increased by 12% and the percentage elongation was remarkably increased by 92%.

In this work, high-performance low-temperature poly-silicon (LTPS) thin film transistors (TFTs) with double-gate (DG) structure and lateral grain growth have been demonstrated by excimer laser crystallization (ELC). Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current–voltage characteristics as compared with the conventional solid-phase crystallized (SPC) poly-Si double-gate TFTs or conventional ELC top-gate (TG) TFTs. The proposed ELC DG TFTs ( W / L = 1.5/1.5 μm) had the field-effect-mobility exceeding 400 cm 2 /V s, on/off current ratio higher than 10 8 , superior short-channel characteristics and higher current drivability.

In this letter, high-performance low-temperature polysilicon thin-film transistors (TFTs) with double-gate (DG) structure and controlled lateral grain growth have been demonstrated by excimer laser crystallization. Via a proper excimer laser condition, along with the a-Si step height beside the bottom gate, a superlateral growth of Si was formed in the channel length plateau. Therefore, the DG TFTs with lateral silicon grains in the channel regions exhibited better current-voltage characteristics, as compared with the conventional top-gate ones. The proposed DG TFTs (W/L = 1/1 mum) had the field-effect mobility exceeding 550 cm2/Vmiddots, an on/off current ratio that is higher than 108, superior short-channel characteristics, and higher current drivability. In addition, the device-to-device uniformity could be improved since grain growth could be artificially controlled by the spatial plateau structure.

In this study, an n-channel metal–oxide–semiconductor field-effect transistor (nMOSFET) fabricated with local strained channel techniques on a (111) Si substrate using a SiN capping layer with high mechanical stress and the stack gate of amorphous silicon (α-Si) and polycrystalline silicon (poly-Si) was investigated. By using these techniques, the performance improvement of the nMOSFETs in the channel direction on the (111) substrate was achieved. The on-current and transconductance (Gm) increased with increasing SiN capping layer or α-Si layer thickness. Our experimental results show that devices with a 700 A α-Si layer show a 6.7% on-current improvement percentage relative to those with a 200 A α-Si layer, and a corresponding Gm improvement percentage of 10.2%. In addition, charge pumping current/interface state density decreased for the samples with a thicker SiN layer.

The characteristics of n-channel metal–oxide–semiconductor field-effect transistors (NMOSFETs) with a SiN capping layer were investigated in this study. Although the incorporation of the SiN capping layer markedly enhanced the carrier mobility and thus the drive current of the fabricated devices, the resistance to hot-carrier degradation was sacrificed, owing to the high content of hydrogen in the SiN layer that might diffuse to the channel region during the process. Even if the SiN layer was removed and the channel strain was released later, the hot-carrier degradation was severer than that in devices without SiN capping. Finally, the lateral distribution of generated interface states due to hot-carrier stress was also investigated in this study.

Microwave annealing were able for the applications of dopant activation[1,2] and silicidation[3] of the nano-scaled transistors, However, during conventional fixed-frequency microwave heating, standing wave patterns are formed in the microwave processing chamber resulting in nodes and antinodes over the processing area. This non-uniform energy distribution in turn results in non-uniform heating, commonly observed in the kitchen microwave oven. Coupling effects to improve the uniformity and dopant activation efficiency by fixed-frequency microwave annealing process was investigated[4]. Through the aid of susceptors, the uniformity of Rs and dopant activation efficiency could be improved.

In this letter, microwave annealing technology is proposed to reduce thermal budget for the manufacture of transparent conductive oxide thin-film transistor (TFT). With microwave annealing, a nitrogenated amorphous In-Ga-Zn-O (a-IGZO:N) TFT fabricated on glass panel behaves as a carrier mobility of 4.21 cm2/V s and threshold voltage of 2.91 V. The performance of microwave-treated a-IGZO:N TFT with annealing process duration of 300 s is well competitive with its counterpart treated by thermal furnace annealing at 350 C for 1 h. Owing to its low thermal budget and selective heating to materials of interest, the microwave annealing has great potential for flexible oxide TFT applications.

In this paper, we discuss dynamic threshold MOS (DTMOS) operations for nMOSFETs of different dielectric types and thicknesses. We found that, under the DT mode of operation, all devices exhibit a threshold voltage close to 0.7 V, independent of the thickness and gate dielectric type of the device. This is due to the diminished influence of the body effect factor. Formulations of threshold voltage and subthreshold swing of DTMOS are developed to gain insights into this unique phenomenon, and simulation of the subthreshold swing is also provided.

Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, during conventional fixed-frequency microwave heating, standing wave patterns can be established in the microwave processing chamber, resulting in nodes and antinodes over the processing area, resulting in thermal variations over the process wafer. In this letter, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency microwave anneal are studied. The composition, number, and spacing of susceptor wafers were varied in a systematic fashion in these experiments.

In this study, activation and crystallization in short channel amorphous Si TFTs were demonstrated using a novel microwave annealing (MWA) technique. Both low-temperature MWA and rapid thermal annealing (RTA) were compared to study the dopant activation level. We successfully activated the source/drain region, improved the electronic mobility and suppressed the short-channel effects using low temperature MWA. This can reduce the annealing temperature and processing time below that of solid phase crystallization (SPC). This technique is promising for realizing a high utility rate of AM-LCDs with low cost. © 2012 The Electrochemical Society. [DOI: 10.1149/2.003201ssl] All rights reserved.

Molybdenum ditelluride (MoTe$_2$) has attracted considerable interest for nanoelectronic, optoelectronic, spintronic, and valleytronic applications because of its modest band gap, high field-effect mobility, large spin-orbit-coupling splitting, and tunable 1T'/2H phases. However, synthesizing large-area, high-quality MoTe$_2$ remains challenging. The complicated design of gas-phase reactant transport and reaction for chemical vapor deposition or tellurization is nontrivial because of the weak bonding energy between Mo and Te. Here, we report a new method for depositing MoTe$_2$ that entails using physical vapor deposition followed by a post-annealing process in a Te-free atmosphere. Both Mo and Te were physically deposited onto the substrate by sputtering a MoTe$_2$ target. A composite SiO$_2$ capping layer was designed to prevent Te sublimation during the post-annealing process. The post-annealing process facilitated 1T'-to-2H phase transition and solid-phase crystallization, leading to the formation of high-crystallinity few-layer 2H-MoTe$_2$ with a field-effect mobility of ~10 cm$^2$/(V-s), the highest among all nonexfoliated 2H-MoTe$_2$ currently reported. Furthermore, 2H-MoS$_2$ and Td-WTe$_2$ can be deposited using similar methods. Requiring no transfer or chemical reaction of metal and chalcogen reactants in the gas phase, the proposed method is potentially a general yet simple approach for depositing a wide variety of large-area, high-quality, two-dimensional layered structures.

Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120°C to 140°C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150°C reduction in maximum temperature at the same activation concentration (about 2 × 1019 cm-3) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.

This is the first study to successfully achieve record DNA sensitivity (sub-ƒM) by self-aligned, maskless, dual-channel, and metal-gate-based thin-film transistor nano-wire FET. Both novel device architecture (dual-channel) and optimization of integration processes (microcrystalline silicon and self-aligned sidewall sub-50 nm critical dimension) of nano-wire FET enhance the sensitivity to biological entities substantially. Meanwhile, the proposed device is accomplished with an embedded VLSI CMOS circuit. It can thus offer high application potential to pH, protein, and DNA probing in SoC-based portable bioelectronics.