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This brief presents a nano-ampere CMOS current reference (CCR) for low power application with a wide temperature range from −40°C to 120°C. The current reference is generated by the division of a temperature-independent voltage and resistance in a simple way. The low temperature-independent voltage is generated based on the threshold voltage difference between two same-type NMOS transistors with different channel lengths working in the subthreshold region, while the temperature-independent resistance is made up by two poly resistors, whose temperature coefficients are opposite. By designing a low voltage to allow for a small resistance, the CCR circuit takes a small chip area while generating nano-ampere current. The proposed CCR circuit was implemented in a standard 0.18- ${\mu }\text{m}$ CMOS process and its active area is 0.054 mm2. Among the measured 10 samples, the average output current is 11.6 nA and the average temperature coefficient is 169 ppm/°C.

This paper presents a three-core LC-based digitally controlled oscillator (DCO) in 55 nm CMOS technology for wideband all-digital phased-locked loop (ADPLL) system. Various techniques are employed to ease the trade-off between tuning range, frequency resolution and linearity. Multi cores and multi-stage improved capacitor arrays are implemented to achieve an ultra-wideband tuning range of 91%. Capacitor division technology is employed for high frequency resolution and carefully symmetrical layout arrangement is applied for linear frequency tuning. This DCO oscillates over a 2.7-7.2 GHz frequency range with a fine frequency resolution of 3.2-14.2 kHz. The DCO exhibits a phase noise of -128.7 dBc/Hz at 1 MHz frequency offset from 4.95 GHz carrier. The total area of the DCO is 1.35×1.08 mm2, with a total current consumption of 25 mA from a 2.5 V supply voltage. The simulation results show that the proposed DCO exhibits comparable good tuning range, resolution and phase noise performances, and is suitable for wideband ADPLL application.

In this paper, a newly analytical method is proposed for the design of programmable frequency dividers. The more accurate transfer function of the current mode logic (CML) stage is used to analyze the injection-locking behavior models of the dual-modulus prescaler, and the general analytical expressions of the locking range of the prescaler are derived. Based on the analytical expressions that can be calculated using device-level circuit parameters obtained through DC and AC simulations, the dual-modulus prescaler design can be optimized quickly and accurately, thereby extending the frequency-division range of the programmable frequency divider. The proposed analytical method is verified by the measured results of the 2–22 GHz programmable divider, fabricated in 0.13-μm SiGe BiCMOS technology. By using heterojunction bipolar transistors (HBTs) in the dual-modulus prescaler and metal–oxidesemiconductor field-effect transistors (MOSFETs) in the pulse and swallow counters, the proposed programmable divider achieves the lowest power consumption of 63.3 mW and the best FOMT compared with previously works.

This Letter presents a 60 GHz low power low noise amplifier (LNA) with high g m × R out transconductor stages in a 65-nm complementary metal oxide semiconductor (CMOS) technology. Different from the cascode and current-reused common source-common source (CS-CS) structure, the new transconductor proposed in this Letter comprises a CS transistor whose DC current is shared by other two transistors. With this configuration, the equivalent transconductance, g m and output resistance, R out of the transconductor are both high while its noise figure is deteriorated slightly comparing with CS structure, making it suitable for low-power LNA circuits. From the measurement results, the LNA gets a gain of 13.4 ± 1.5 dB and 3-dB bandwidth of 16.7 GHz (48-64.7 GHz). The average noise figure of the LNA is 6.1 dB with a power dissipation of 9.6 mW under 1 V power supply.

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

A fully-integrated differential transceiver for C-band, based on polyphase filters (PPFs) to achieve a high image rejection ratio (IRR), is proposed in the paper. The transceiver meets the requirements for the 5GHz band radar application, which is implemented in 1P6M 0.18μm CMOS technology. The receiver achieves 7.2dB NF, 29.3dB gain and 50.7dB IRR with 3-level digital gain controllability, while draws 93.1mA from 3.3V power supply. The transmitter achieves 16.4dBm output peak power, 29.5dB gain and 65.6dB IRR, which dissipates 138.4mA from 3.3V power supply. The die area is 2.7mm×2.9mm.

We present a 31-45.5 GHz injection-locked frequency divider (ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power con- sumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm0.42 mm.

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

A 26–47.9 GHz ultrawideband CMOS dual injection-locked frequency divider (dual-ILFD) with high input impedance is demonstrated. As the differential input signal is injected into the gate of the PMOS tail transistor and NMOS switch transistor, the proposed divider has high input impedance and can be driven easily by the preceding driving circuits. Meanwhile, the locking range of the proposed divider is extended significantly by fully utilizing the dual-injection technique. The proposed dual-ILFD is fabricated in a standard 90-nm CMOS process and on-wafer measurements are performed. The measurements show that the free-running frequency of the divider is 19.11 GHz. At an incident power of 0 dBm, a total locking range from 26 to 47.9 GHz is achieved. The power consumption is 2.88 mW at a supply voltage of 1.2 V. The total chip size is 0.62 × 0.42 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2126–2129, 2014

An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time T ERC , the channel resistor R on and the capacitance of C L . The range of T ERC is restricted in actual PDP system. C L is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller R on .

This paper presents a 24–48-GHz low power high gain low noise amplifier (LNA) in a 90-nm LP CMOS process. The asymmetrical T-coils, together with gate-inductive peaking, not only enhance the wideband gain, but also facilitate the layout design and reduce the chip area. The fabricated LNA circuit exhibits a broadband of 24–48-GHz and an average gain of 20 dB, while consuming a dc current of 17.6 mA from a 1.2 V supply. The minimum noise figure is only 3.1dB. This monolithic integrated circuit achieves excellent relative bandwidth of 67% compared with the previous published millimeter-wave (MMW) CMOS amplifiers.

This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 µm CMOS technology. Each channel incorporated a transimpedance amplifier and a limiting amplifier. To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s, an optimized circuit topology was proposed and some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, and active negative feedback. Against the power consumption, crosstalk and noise, some corresponding solutions were presented such as applying isolation structure for parallel amplifier array, and optimization of noise and circuit parameters for 10 Gb/s applications. The on-wafer measurements revealed that this chip’s operation speed reached up to 10 Gb/s per channel, and 120 Gb/s with 12-channel in parallel operation. Consuming a DC power of 853 mW from a 1.8 V supply voltage, the chip exhibits a conversion gain of up to 92.6 dBΩ, and a −3 dB bandwidth of 8 GHz, the output swing and input sensitivity for a bit-error rate of 10−12 at 10 Gb/s are 310 mV and 10 mVpp, respectively. The chip size is 1142 µm×3816 µm including on-wafer testing pads.

This letter presents a wideband transformer balun with a center open stub. Since the interconnected line between two coupled-lines greatly deteriorates the performance of balun in millimeter-wave designs, the proposed center open stub provides a good solution to further optimize the balance of balun. The proposed transformer balun with center open stub has been fabricated in 90 nm CMOS technology, with a compact chip area of 0.012 mm 2 . The balun achieves an amplitude imbalance of less than 1 dB for a frequency band ranging from 1 to 48 GHz along with a phase imbalance of less than 5 degrees for the frequency band ranging from 2 to 47 GHz.

A 1.8 mW wideband common-gate (CG) low-noise amplifier (LNA) with double capacitor-cross-coupled (CCC) feedback is presented for multiband wireless communication standards. To achieve a low-noise figure (NF) and high-voltage gain under low power consumption, the CG LNA is based on the double CCC feedback and current-reuse techniques. Post-layout simulated results for 0.18 μm CMOS implementations show that the voltage gain is 18.1 dB with a 3 dB bandwidth from 100 MHz to 1.7 GHz and the IIP3 is -4.9 dBm at 1 GHz. The average NF is 2.4 dB within the entire 3 dB bandwidth. The LNA consumes 1.8 mW from a 1.8 V DC supply and the active size is 0.15 × 0.14 mm 2 .

Human enterovirus 71 (EV71) and coxsackievirus A16 (CA16) are the major etiological agents of hand, foot and mouth disease (HFMD) and are often associated with neurological complications. Currently, several vaccine types are being developed for EV71 and CA16. In this study, we constructed a bivalent chimeric virus-like particle (VLP) presenting the VP1 (aa208-222) and VP2 (aa141-155) epitopes of EV71 using hepatitis B virus core protein (HBc) as a carrier, designated HBc-E1/2. Immunization with the chimeric VLPs HBc-E1/2 induced higher IgG titers and neutralization titers against EV71 and CA16 in vitro than immunization with only one epitope incorporated into HBc. Importantly, passive immunization with the recombinant HBc-E2 particles protected neonatal mice against lethal EV71 and CA16 infections. We demonstrate that anti-VP2 (aa141-155) sera bound authentic CA16 viral particles, whereas anti-VP1 (aa208-222) sera could not. Moreover, the anti-VP2 (aa141-155) antibodies inhibited the binding of human serum to virions, which demonstrated that the VP2 epitope is immunodominant between EV71 and CA16. These results illustrated that the chimeric VLP HBc-E1/2 is a promising candidate for a broad-spectrum HFMD vaccine and also reveals mechanisms of protection by the neighboring linear epitopes of the VP1 GH and VP2 EF loops.

This paper presents the design of a low power and a highly linear folded down-conversion mixer, for wideband applications, implemented in a 65nm CMOS process. Post-layout simulation results are presented. The proposed multiple-gated transistor (MGTR) based mixer achieves a linearity enhancement of 12.68 dB when compared to a conventional folded single balanced mixer operating at an input radio frequency (RF) range of 10.25∼13.75 GHz (direct conversion), with a fixed local oscillator (LO) frequency of 12 GHz and a corresponding intermediate frequency (IF) ranging from dc∼1.75 GHz. The proposed mixer combines the advantages of both gm3 cancellation and low output impedance in order to maximize linearity without employing a tuned load, hence not limiting the performance of the mixer to narrowband applications.

This paper presents a 1-V class-E power amplifier for Wireless Sensor Network in a 0.18-μm CMOS process. The design exploits a cross-coupled structure to achieve high operating frequency and reduce the size of the transistors. Pairs of digital MOS switches manipulate the cross-coupled structure to work or not. To control the output power, a topology of three parallel units with different output power is adopted. An off-chip balun is also proposed for output differential-to-single ended conversion and impedance matching. At 800 MHz, the power amplifier can deliver a range of output power from -5.5 to 6.6 dBm and achieve maximal power-added efficiency (PAE) of 52.7% at 6.6 dBm.

The effect of the middle hepatitis B virus surface protein (MHBs) remains to be elucidated. To investigate the biological function of the MHBs protein, the present study performed yeast two-hybrid screening to search for proteins that interact with the MHBs protein in hepatocytes. The bait plasmid expressing the MHBs protein was constructed by cloning the gene of the MHBs protein into pGBKT7, then the recombinant plasmid DNA was transformed into AH109 yeast (a type). The transformed yeast AH109 was mated with yeast Y187 (α type) containing the liver cDNA library plasmid in 2X yeast peptone dextrose adenine (YPDA) medium. The mated diploid yeast was plated on quadruple dropout medium (SD/-Trp-Leu-His-Ade) containing X-α-gal for selection and screening. Following extracting and sequencing of the plasmids from positive (blue) colonies, the sequence analysis was conducted and analyzed by bioinformatics methods. Two colonies were selected and sequenced. Among them, one was the human DNA sequence from the clone RP11-490D19 on chromosome 9 and the other was homo sapiens 12 BAC RP11-180M15 (Roswell Park Cancer Institute Human BAC Library). The yeast two-hybrid system is an effective method for identifying hepatocyte proteins that interact with MHBs. The MHBs protein binds with different proteins suggesting that it has multiple functions in vivo.

As the CMOS technology scaling into nanometer and the power supply voltage decrease, low-voltage circuit design becomes a challenge. A divider-by-2 with 0.5 V power supply implemented in TSMC 0.13 μm 1P8M CMOS process is designed to produce 2.4 ~ 2.5 GHz quad-signals for Wireless Sensor Networks (WSN). To reduce the threshold voltage of transistors, low-threshold (LT) NMOS transistor in Deep-N-Well (DNW) with Forward-Body Bias technique is used in the circuits. The design of layout with DNW and isolation of the bulk of the LT NMOS with the substrate are explained in this chapter. The post-simulated operating frequency range is 2.5 ~ 7 GHz and the power consumption is 0.9 mW at 5 GHz.

A 3-bit microelectromechanical system (MEMS) digital attenuator is designed with 0–20 GHz bandwidth. The attenuation ranges from 0 to 35 dB with 5 dB step. The attenuator, with the coplanar waveguide (CPW), is implemented by surface sacrificial layer technology. The DC-contact MEMS switches with three contact dimples are symmetrically placed around the T type resistor network, making the switches minimum in number and the structure compact. Through the lumped parameter method, the attenuator has good terminal matches in different attenuation states. The test results show that eight different attenuation states are realized within 0–20 GHz. The attenuation deviation is less than ±5%, the insertion loss is less than 1.7 dB and the voltage standing wave rations is less than 1.4 under most of the attenuation states. With the MEMS switches and CPW being adopted, the attenuator has the advantages of higher linearity, lower insertion loss and power consumption. The chip size is about 3.2 mm2 including the pad.

A 7-bit 26MS/s SAR (successive approximation register) ADC is presented in this paper for the application of ZigBee receiver. Compared to the conventional method, the set-and-down method reduces the average switching energy by around 80%. Dynamic comparator is chosen to diminish the signal-dependent offset caused by the non-fixed input common-mode voltage. A prototype ADC was implemented in a CMOS 0.18-μm technology. The ADC consumes 1.66 mW at 26MS/s under a 1.8-V supply. The post-simulation shows that SNDR and SFDR are 43.11dB and 57.49dB, when sampling 3.19921875 MHz sinusoid input signal at 26MHz sampling clock.

A 1.8 GHz LC VCO in 1.8-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for digital switched tuning. Designed in 0.18μm RF CMOS technology, the proposed VCO achieves a phase noise of −126.2dBc/Hz at 1MHz offset and consumes 1.38mA core current at 1.8-V voltage supply.

In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18μm CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than ±0.005%. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V.

A novel Charge Pump (CP) circuit with high performance is introduced in this paper. A rail-to-rail operational amplifier is used to enable the CP charge and discharge currents to be match well in a wide output voltage range. A unity-gain amplifier is adopted to eliminate the current sharing problem. Besides, the high initial charge current shortens the settling time of charge pump phase-locked-loops (CPPLLs). The proposed CP designed and realized in 0.18µm CMOS process. The test results show that the current mismatch rate can be less than 0.5% in the output voltage range of 0.23V to 1.72V, with the charge pump current of 100µA and the precharging current of 109µA. The average power consumption of the charge pump in the locked condition is around 0.57mW under 1.8V supply voltage.

This paper presents a 6-bit 1.8V 16MS/s, low-power digital to analog converter (DAC) using TSMC 0.18µm CMOS technology for WSN applications. It is based on a current steering binary weighted architecture. It has differential current outputs. The output voltage is externally generated by the current that the DAC injects into high precision resistor. The DAC occupies 0.7mm×0.5mm. A spurious-free dynamic range (SFDR) of more than 50dB has been simulated over the complete Nyquist interval at sampling frequencies up to 16MS/s. The power consumption at a 16MHz clock frequency for a near-Nyquist sinusoidal output signal approximately equals 1.5mW.

A 4.8GHz LC voltage controlled oscillator (VCO) for WSN Applications is designed based on TSMC 0.18 µm RF CMOS process. The VCO adopts complementary differential negative resistance structure with switch resistor biasing which achieves good phase noise performance and realizing low power consumption. The 3-bit switch capacitor array provides wide tuning range and the 6-bit switch resistors array provides varied biasing current by auto current calibration (ACC) circuit. With a 1.8V supply voltage, the post-simulated result achieves 27.7% tuning range that can compensate the frequency deviation due to process corners. The post simulated phase noise is −119dBc/Hz@1MHz at frequency of 2.44GHz. The operating current of the VCO core is from 0.4mA to 3.3mA. Finally, the chip size of the VCO core is 0.3mm2 and the whole chip size is 0.8×1.2mm2 with testing buffer and pads.

A 4.8GHz CMOS LC VCO with 37.5% tuning range in 0.5-V supply is presented. The VCO achieves low power consumption by optimum selection of inductance in the L-C tank. To increase the tuning range, a three-bit switching capacitor array is used for the digital switched tuning. A voltage-boosted technique is used to generate a high voltage for the switches in the digital tuning scheme. Designed in 0.13μm CMOS technology, the proposed VCO achieves a phase noise of −113.8dBc/Hz at 1MHz offset and consumes 2.4mA core current at 0.5 voltage supply.

A 10-Gb/s transimpedance amplifier (TIA) for the parallel optical receiver module is realized in 0.18-μm CMOS technology. The proposed TIA employs a regulated cascode (RGC) input structure and adopts active inductor peaking and feedback techniques to enhance the bandwidth. Besides, a noise optimization is processed. The TIA provides a conversion gain of 50 dBΩ and 3-dB bandwith of 7 GHz. The measured sensitivity is about 35 μA at a bit error rate of 10−12 with a 231−1 pseudorandom test pattern for 10 Gb/s operation. Under a 1.8-V supply voltage, the differential TIA consumes 29.2 mW, counting an output buffer. The core chip area is 144×160 μm2 excluding the output buffer and testing pads.

In this paper, a new model for interleaved planar symmetric balun in CMOS radio frequency integrated circuits (RFICs) is developed. The model uses a “2-Π” sub-circuit to represent each inductor coil in the balun, and a novel substrate inductance is introduced to describe the substrate eddy-current effect. Verification with the measured data from a CMOS process demonstrates the model's accurate performance prediction up to self-resonant frequency (SRF).

A 10-Gb/s integrated optical receiver front-end amplifier (FEA) that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) has been designed based on a 0.18-μm CMOS technology. A regulated-cascode (RGC) structure was used in the design of transimpedance amplifier (TIA), which overcomes the inadequate bandwidth problem caused by the large parasitic capacitance effect of the photodiode and CMOS transistors. By employing the interleaving active feedback, the bandwidth of the limiting amplifier (LA) was enhanced. And the noise analysis and optimization was especially performed to drive the FEA to obtain good noise performance. The schematic simulation results indicate that, with a photodiode parasitic capacitance of 500fF and the bonding pad parasitic capacitance of 200fF between which a 2-mm bond wire is inserted at the input node, the FEA provides a conversion gain of up to 90.3 dBΩ and −3-dB bandwidth of 10.38 GHz. By properly adopting the proposed noise optimization methods, the optimized average equivalent input noise current is about 2.8 μA rms . Operating under a 1.8-V supply, the power dissipation is about 94mW.

Conventional charge pumps (CPs) all share a problem of current mismatching, which dominates the phase noise of phase-locked loop (PLL). A high performance charge pump circuit in 0.18μm CMOS process is presented. A rail-to-rail error operational amplifier with reference circuit and self-biasing cascode current mirror enables the charge pump current to be well matched in a wide output voltage range. Simulation results show that the current mismatching can be less than 0.01% within output voltage range of 0.01V to 1.6V, with the charge pump current of 100μA. The circuit dissipates 3mW from a single 1.8-V supply.

A Ku-band MMIC of power amplifier has been designed in the standard 0.2 μm AlGaAs/InGaAs/GaAs PHEMT process of OMMIC. The monolithically integrated single-ended 3-stage power amplifier is biased at class A state. The resistors have been added in series or in parallel with the gate of the PHEMT for each stage to improve the stability. Under a single supply voltage of +3.5V, simulations prove that the circuit exhibits a linear output power of more than 28 dBm (P1dB); small signal gain of 21 dB, input return loss of less than -15 dB, output return loss of less than -5 dB and power additional efficiency of 23.5%.

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order (LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band (VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher quality-factor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18-μm CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 mA. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are −122.5, −113.3, −110.1, and −116.8 dBc/Hz, respectively. The chip area, including the pads, is 1.2 × 0.62 mm2 and the supply voltage is 1.8 V.