A 0.5 V Divider-by-2 with Forward-Body Bias Technique for Wireless Sensor Networks

As the CMOS technology scaling into nanometer and the power supply voltage decrease, low-voltage circuit design becomes a challenge. A divider-by-2 with 0.5 V power supply implemented in TSMC 0.13 μm 1P8M CMOS process is designed to produce 2.4 ~ 2.5 GHz quad-signals for Wireless Sensor Networks (WSN). To reduce the threshold voltage of transistors, low-threshold (LT) NMOS transistor in Deep-N-Well (DNW) with Forward-Body Bias technique is used in the circuits. The design of layout with DNW and isolation of the bulk of the LT NMOS with the substrate are explained in this chapter. The post-simulated operating frequency range is 2.5 ~ 7 GHz and the power consumption is 0.9 mW at 5 GHz.