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In this study, the recent advances and trends of chiplet design and heterogeneous integration packaging will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, lateral interconnects, and examples of chiplet design and heterogeneous integration packaging. Also, emphasis is placed on the fundamental and examples of hybrid bonding. [ABSTRACT FROM AUTHOR]

In this paper, the warpages of a chip-first and die face-up fan-out wafer-level packaging (FOWLP) with a very large silicon chip (10 mm $\times \,\, 10$ mm $\times \,\, 0.15$ mm) and three redistributed layers are measured and characterized. Emphasis is placed on the measurement and 3-D finite-element simulation of the warpages during the FOWLP fabrication processes, especially for: 1) right after postmold cure; 2) right after backgrinding of the epoxy molding compound to expose the Cu-contact pads; and 3) the individual package (right after the solder ball mounting and dicing) versus surface mount technology reflow temperatures. The simulation results are compared to the measurement results. Some recommendations on controlling the warpages are provided. [ABSTRACT FROM AUTHOR]

Recent advances in flip chip technology such as wafer humping, package substrate, flip chip assembly, and underfill will be presented in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. [ABSTRACT FROM AUTHOR]

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure. [ABSTRACT FROM AUTHOR]

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration. [ABSTRACT FROM PUBLISHER]

In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollow TSV for fluidic circulation. Heat transfer enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated liquid cooling solution for 100 W from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed. [ABSTRACT FROM AUTHOR]

Abstract: Thermal performances of 3D IC integration system-in-package (SiP) with TSV (through silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational fluid dynamic) analyses. Emphases are placed on the determination of (1) the equivalent thermal conductivity of interposers/chips with various copper-filled, aluminum-filled, and polymer w/o filler filled TSV diameters, pitches, and aspect ratios, (2) the junction temperature and thermal resistance of 3D IC SiP with various TSV interposers, (3) the junction temperature and thermal resistance of 3D stacking of up to 8 TSV memory chips, and (4) the effect of thickness of the TSV chip on its hot spot temperature. Useful design charts and guidelines are provided for engineering practice convenient. [Copyright &y& Elsevier]

The development of ultrafine-pitch microbumps and the thermal compression bonding (TCB) process for advanced 3-D stacking technology are discussed in this paper. Microbumps, consisting of Cu pillars and thin Sn caps with a pitch of 25 \mum, are fabricated on an Si chip by the electroplating method. Total thickness of the Cu pillar and the Sn cap is 10 \mum. Electroless nickel and immersion gold pads with a total thickness of 4 \mum are fabricated on an Si carrier. TCB of the Si chip and the Si carrier is conducted on an FC150 flip-chip bonder, and a good joining with higher than 10-MPa die shear strength is achieved. After bonding, the bond line thickness between the Si chip and the Si carrier is filled with the selected capillary underfill material. Void-free underfilling is achieved with underfill materials which have a fine filler size. Ninety percent of the bonded samples can pass the thermal cycling test (-40/+125^\circC) with 1000 cycles and the highly accelerated temperature/humidity stress test (130^\circC, 85% RH) for 96 h. [ABSTRACT FROM PUBLISHER]

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 \mum in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 \mum in diameter and 25 \mum in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs. [ABSTRACT FROM PUBLISHER]

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21\,\times\,21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-\mum SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25\,\times\,25\,\times\,0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45\,\times\,45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements. [ABSTRACT FROM PUBLISHER]

Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack fine pitch ball grid array package is reported. A 65 nm Cu/low-k die is used as the bottom die in the package to increase the speed of the chip with multilayer interconnect structures. Compared to the conventional dielectrics, low-k materials are softer and less resistant to thermal-mechanical stress induced by packaging processes. In this paper, finite element analysis is performed to minimize the stress in low-k layers and to address the low-k delamination issue. In the dicing evaluation, comparison among straight cut, bevel cut and two-step cut was performed in terms of die strength and chipping results. It is found that the bevel cut dicing method is the best dicing method. The die attach process (especially wire embedded film process) is optimized to ensure that no voids are present in the die attach materials after the bonding process. The ultralow loop wire bonding process (50 \mum) is also well established. The maximum wire sweep for all test vehicles is less than 10% in the molding process. Finally, all samples for test vehicle 1 were shown to have successfully passed JEDEC component level tests such as thermal cycling for 1000 cycles (-40^\circC to 125^\circC) and high temperature storage (HTS at 150^\circC) for 1000 h. [ABSTRACT FROM PUBLISHER]

With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP (EMWLP) is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present low loss passives on EMWLP platform demonstrated in a 5.5-GHz band pass filter targeted for wireless local area network (WLAN) applications. To ascertain the feasibility of designing for low loss millimeter wave passives on EMWLP, transmission lines were designed and their loss characteristics investigated up to 110 GHz, which are reported here. Subsequently we demonstrate for the first time a narrowband low loss 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results. In addition, a temperature dependence characterization was performed on the 77-GHz filter, with little variation in the measured filter characteristics observed. [ABSTRACT FROM AUTHOR]

Copper(Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm x 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-µm pitch in two depopulated rows using redistribution layers (RDL).Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 µm height with SnAg solder cap and SnAg solder bump of 150 µm height with 5-µm-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow under fills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-kWLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL. [ABSTRACT FROM AUTHOR]

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law is grounded in lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. However, there are many critical issues for 3D IC integration. In this study, some of the critical issues will be discussed and some potential solutions or research problems will be proposed. [ABSTRACT FROM AUTHOR]

The design and assembly process of 10 different 3D MEMS packages will be presented and discussed in this study. These 3D MEMS packages integrate the MEMS devices from the MEMS wafer (with either wirebonding pads, or solder-bumped TSV, through silicon via, substrate, or solder-bumped flip chip without TSV), the ASIC chips from the ASIC wafer (either with or without TSV), and the cavity package cap from the cap wafer (either with or without TSV). The assembly process consists of release (etching), singulation, wire bonding, flip chip, TSV, cavity etching, chip-to-wafer (C2W) bonding, and wafer-to-wafer (W2W) bonding. It can be shown that these packages lead to a small packaging footprint, high electrical performance, and potentially low cost. [ABSTRACT FROM AUTHOR]

Low-temperature solders have wide applications in integrated circuits and micro-electromechanical systems packaging. In this article, a study on Ag-In solder for chip-to-chip thermocompression bonding was carried out. The resulting joint consists of AgIn2 and Ag9In4 phases, with the latter phase having a melting temperature higher than 400°C. Complete consumption of In solder into a Ag-rich intermetallic compound is achieved by applying a bond pressure of 1.4 MPa at 180°C for 40 min. We also observe that the bonding pressure effect enables a Ag-rich phase to be formed within a shorter bonding duration (10 min) at a higher pressure of 1.6 MPa. Finally, prolonged aging leads to the formation of the final phase of Ag9In4 in the bonded joints. [ABSTRACT FROM AUTHOR]