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Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6x logic density, 1.5x energy efficiency, and 1.4x operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

Memory arrays such as SRAM cells are responsible to the high-power consumption of modern digital systems. This investigation proposed an SRAM utilizing an ultra-low power cell, implemented using the 16-nm FinFET CMOS technology. Voltage supply selection of the static RAM cells is done by gating the wordline (WL) enable. In standby mode, the cell wordline is not activated, where the cell operates on a lower voltage level so that the stored bit status is still retained. On the other hand, the normal mode is activated when the wordline of the cell is enabled. Theoretical derivations, all-PVT-corner post-layout simulations, and measurement results were provided for verification of the functionality and performance. An SRAM of 1-kb capacity is designed based on the propose cell. The on-silicon measurement demonstrates 0.006832 fJ (energy/bit) at 500 MHz clock rate and 0.8 V supply.

Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 $$\upmu $$ m $$^{2}$$ (12 $$\upmu $$ m $$\times $$ 17 $$\upmu $$ m).

Rotational speed detection is important for alternator-voltage-regulator (AVR) to starts-up and generates regulated electric power for vehicles. However, the rotational speed detection in standby mode for self-start is challenging with low loss rectifier, such as the Schottky diode. In this paper, a novel rotational speed detection method by sensing phase voltage or field voltage at specific modes is proposed to solve the issue without extra wiring or external components. The analysis of phase voltage in standby mode considering rectifier leakage current explains the challenges of conventional detection. The derivation of field voltage in standby mode with ANSYS Maxwell simulation verifies the proposed method. The experimental platform with a three-phase six-pole pairs alternator verified that the proposed method can detect rotational speed even in self-start and low speed of 200 rpm.

In this article, the effect of large double frequency capacitor voltage ripple (CVR) on harmonic performance, efficiency, and capacitor lifetime in the cascaded H-bridge low capacitance static reactive power compensator (StatCom) (LC-StatCom) is analytically determined. With insight provided by the analysis, an LC-StatCom with modular switched capacitors is proposed that provides a degree of freedom to control the CVR magnitude. The premise of the operation is to keep redundant capacitor modules in standby mode when operating with lower currents. In addition, it is shown that by distributing losses between additional dc-side switches and the main H-bridge switches, the proposed concept provides opportunities for choosing an optimal hybrid combination of semiconductor technologies. The proposed concept is evaluated using a simulated 8.5 MVA StatCom and feasibility of the proposed system is confirmed by experiments on a seven-level 0.8 kVA single-phase LC-StatCom prototype.

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time in standby mode drained out as soon. To mitigate this problem Static Random-Access Memory (SRAM) is designed with dual control stacked inverter which exploits dual control signals. The proposed dual control stacked inverter reduces the power consumption by 43.42%, 71.71% 63.83% and reduces the delay by 77.05%, 77.06%, 77.16% when compared to sleepy stack approach, sleepy keeper approach and dual stack power gating. Similarly, the proposed dual controlled stacking SRAM with low Vth reduces the power consumption by 96.7%, 95.36%, 96.69% and 33.54% when compared to the sleepy stacky approach, sleepy keeper approach, dual stack approach and dual controlled stacking. The proposed SRAM cell increases the reliability of overall System on Chip.

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

This article presents Switched-Capacitor assisted Power Gating (SwCap PG) for reducing the leakage currents of large digital circuits. For the first time, PG switch is biased in the super turn-off and the super turn-on mode during the off-state and the on-state, respectively. A simple switched-capacitor network reconfigures and biases the PG switch in four different possible states with low area and power overhead. During the super turn-off, voltage stress is avoided in the PG switch when the circuit load uses supply voltage equal to the nominal $\text{V}_{\mathbf {DD}}$ in a given technology, and maximum possible leakage current reduction is achieved by the optimal biasing of the gate voltage. The proposed SwCap PG is experimentally validated in the 180nm CMOS technology. Measurement results of CMOS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by 186- $226\times $ and 18% respectively, as compared to the conventional PG. An alternate solution for SwCap network using MEMS devices as the switching elements is implemented for additional benefits. Measurement results of MEMS SwCap PG show that leakage current and $\text{R}_{\mathbf {ON}}$ reduce by $172\times $ and 26% respectively, compared to the conventional PG. Finally, the applicability of the SwCap PG in the nano-scale CMOS technologies is addressed.

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

This letter describes a miniature, ultra low power, all-dynamic temperature sensor based on a duty-cycled resistive transducer bridge and a 9-bit asynchronous SAR ADC in 65-nm CMOS. It features a novel floating bridge technique and automatic power gating to achieve the lowest reported power consumption. It consumes 2.18 pJ per conversion and has an RMS resolution of 0.53 K, leading to an FoM of 0.61 pJ $\cdot \text{K}^{2}$ . A standby power of 52 pW allows a high power-efficiency, even at low sample rates. It occupies $36\times 46\,\,\mu \text{m}$ of chip area and has a sensing range from −20 °C to 120 °C.

This article presents a highly stable SRAM-based physically unclonable function (PUF) using enhancement–enhancement (EE)-structure bit cells for native stability improvement. The PUF bit cells are power-gated 2-D and are normally in the OFF state, which largely reduces power and is beneficial to attack tolerance. In addition, a dark-bit detection technique based on a lightweight integrated ${V}_{\text {SS}}$ -bias generator is implemented in order to screen out potentially unstable bit cells (dark bits) induced by supply voltage/temperature (VT) variations and other factors. Measured native bit error rate (BER) of prototype chips fabricated in 130-nm standard CMOS is 0.21% at 0.8 V and 23 °C, which is 14 $\times $ better compared with the conventional SRAM-based PUF. After masking the detected dark bits, no bit error (3339 bits $\times $ 500 evaluations) appeared at the worst VT corner across 0.8 to 1.4 V and −40 °C to 120 °C. This technique also eliminated all unstable bits in the accelerated aging test. Both the data before and after dark-bit masking have passed all applicable NIST SP 800–22 randomness tests. The measured operational energy at 0.8 V is 128 fJ/bit and the standby power is 0.44 pW/bit, thanks to the 2-D power-gating scheme. The nMOS-only bit cell is highly compact, with a normalized bit cell area of 373 F 2.

As today's CMOS technology is gradually scaling down to its physical limits, emerging technologies are under research as alternatives in the future, such as carbon nanotube, magnetic tunneling junction, memristor. Among them, memristor is a promising candidate to implement the futuristic VLSI circuits. It provides a great scalability, near-zero standby power consumption, etc. In order to design memristor based VLSI circuits and explore their potential, it is crucial to develop an automated design flow. However, such a design flow is still missing so far. This paper proposes an automated design flow, Mosys by reusing parts of existing CMOS VLSI circuit design tools. Mosys provides a circuit design flow from a Verilog programming interface to performance estimation models. In addition, it employs a probabilistic power estimation model instead of one based on exhaustive-searching method. In our experiments, it significantly reduces the running time up to over 3000 times with a marginal error (

Quaternary memory and logic circuits have been studied by researchers, as they can provide denser integrated circuits and subsequently lower area and power consumption via succinct interconnects. Using multithreshold gate-all-around carbon nanotube field-effect transistors and the nonvolatile feature of magnetic tunnel junctions (MTJs), this letter proposes a bio-inspired variation-aware nonvolatile quaternary latch (Qlatch). Nonvolatility allows the system to be completely powered off during the idle state to reduce standby power significantly without the need for extra component and data loss. Moreover, thanks to the bio-inspired structure of the Qlatch, and the fact that no sense amplifier is used in this circuit to read the MTJs, the Qlatch is more robust to process variations. Simulation results show that the nonvolatile Qlatch consumes 7% less dynamic power and 12% less static power than the conventional Qlatch, has a 61% lower delay, and has 68% lower power delay product.

The proposed threshold detection based ADC targets continuous monitoring systems, where full reconstruction of the input signal isn’t required. The ADC observes whether the input signal stays within safety margins keeping the microcontroller in the standby mode until alarm occurs. This approach generates significantly less output data that needs to be wirelessly transmitted, thereby resulting in significant power savings in the system. This proposed ADC takes full advantage of a ∆Σ DAC allowing for high flexibility and requiring only one decision clock cycle independent of the target resolution. This compact design occupies only 0.012 mm2 in 65 nm CMOS with 10 bits resolution.

This letter presents a microcontroller unit (MCU) that employs a $c$ -axis aligned crystalline indium–gallium–zinc oxide semiconductor FET (CAAC-IGZO FET) with an extremely low off-state current below the zepto-ampere (10−21 A) level. This MCU based on IGZO-FETs has logic circuits and memory macros that can retain data even when the power supply is turned off, and internal voltage regulators that store the reference voltage. A prototype chip has been fabricated with a monolithic process that combines an IGZO process (embedded in BEOL) and an Si CMOS process; the chip has a standby power of 880 nW, a system backup time of 21 ns with 44 fJ/bit, and a wakeup time of $4.69~\mu \text{s}$ . The fabricated chip has demonstrated that the highly energy-efficient normally off computing that establishes low-power operations in Internet of Things and edge AI computing can be achieved with IGZO technology.

A hybrid device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. A hierarchical top-down design approach is used to develop a hybrid spin/charge based FPGA (HSC-FPGA) starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication challenges. Circuit-level simulations indicate at least 40% and 83% read and standby power reduction, respectively, for MRAM-LUTs compared to SRAM-LUTs. However, MRAM-LUTs using spin transfer torque (STT) switching approach suffers from significant write energy consumption. Therefore, we have designed spin Hall effect (SHE)-assisted MRAM-LUTs realizing more than 67% and 61% reduction in reconfiguration energy and area consumption, respectively. Fabric-level simulations exhibit that HSC-FPGA achieves 70% and 30% reductions in standby and read power, respectively, compared to SRAM-based FPGAs for various ISCAS-89 and ITC-99 benchmark circuits. Finally, a multi-level method spanning device-sizing, circuit modular-redundancy, and component-level reconfiguration is developed to increase the process variation resiliency of the MRAM-LUTs. The power consumption and area utilization are analyzed to formulate tradeoffs resulting in recommendations toward future multi-device-based reconfigurable fabrics.

Maximizing the performance during peak workload hours and minimizing the power consumption during off-peak time plays a significant role in the energy-efficient systems. Our previous work has proposed an efficient architecture of a bitmap index creator (BIC) that produced higher indexing throughput than the central processing units and graphics processing units. This paper extends the previous study by focusing on the ASIC implementation of BIC in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process. The fabricated chip could operate at different supply voltages, from 0.4 V to 1.2 V. In the active mode with the supply voltage of 1.2 V, it was fully operational at 41 MHz and consumed 6.68 mW, or 162.9 pJ/cycle. In the standby mode with the supply voltage of 0.4 V and clock gated, the power consumption lowered to 10.6 μW. More significantly, when the reverse back-gate bias voltages are supplied, the standby power deeply reduced to 2.64 nW. This achievement is of considerable importance to the energy-efficient systems.

A dual-gate configuration has been introduced to organic thin-film transistors (TFTs) for full-depletion behavior to enhance the transconductance, subthreshold slope, and drain current on–off ratio. In this letter, we show how those dual-gate effects influence the static and dynamic responses of three-dimensional (3-D) complementary organic logic gates in comparison to their single-gate counterpart. For the comparative study, 3-D inverters and ring oscillators were fabricated by printing directly on plastic foil in both single- and dual-gate configurations. In the static inverter operation, the fully depleted characteristics of the dual-gate TFTs lead to an increase in voltage gain and a dramatic decrease in standby power consumption. In the dynamic ring oscillator operation, the two configurations have comparable gate delays because the use of an additional gate increases not only the drain current but also the load input gate capacitance. Our findings demonstrate the performance of an inverter that can represent the overall operation of complementary logic gates consisting of pull-up and pull-down networks, thereby providing significant insight into the printed organic TFT circuit design using dual gating effects.

This work investigates the performance of strained Si on insulator as potential material for forced stacked multi-threshold FinFET based inverter considering its ultra low-power applications. Using the calibrated exhaustive 3D-TCAD mixed-mode simulation a comparative analysis of conventional and forced stack FinFET based inverters has been performed. The static and dynamic characteristics have been compared with conventional and forced stacked FinFET based inverter. The leakage in standby mode can be reduced through well-defined stack and multi-threshold (VTH) transistors. Channel doping is optimized to get higher VTH devices. To improve the speed of circuits FinFETs are designed on strained Silicon on Insulator (sSOI) wafer. Uniform uniaxial tensile stress in sSOI gives the advantage of high ON current in n-FinFETs. It is observed that using strained FinFETs the maximum delay is reduced below 10 ps and using multi VTH forced stack technique the leakage power is reduced. Hence, forced stack technique based FinFET can evolve as a potential candidate for the future ultra-low power device applications.

Leakage power consumption of clock distribution networks (CDNs) is an important challenge in modern synchronous integrated circuits with billions of deeply scaled transistors. Multithreshold CMOS technology is commonly used to provide power reduction in standby mode while maintaining high performance in active mode. In this paper, a novel dual-threshold-voltage repeater circuit with split inputs–outputs (SPLIT-IOs) is employed for suppressing leakage currents in gated CDNs. Three floor planning strategies are considered for clock distribution across the chip with signal transition times of less than or equal to 50 ps at the leaves. Depending on the power supply voltage and floor plan, the standby leakage power consumption is reduced by 50.36%–78.43% with the proposed clock tree with SPLIT-IO repeaters as compared to the conventional three-level H-tree in a 45-nm CMOS technology. The spread of standby leakage power due to process variations is compressed by 36.72%–73.77% with the proposed clock tree as compared to the standard network. The proposed circuit technique significantly lowers the total energy consumption of partially active networks with local clock gating as well. The energy savings provided by the SPLIT-IO buffers are enhanced with the scaling of power supply voltage and frequency in synchronous systems-on-chip.

A bidirectional link geared toward mobile I/O applications is presented that leverages the technological advantages of CMOS scaling to improve energy efficiency. Active power consumption is minimized by operating the link at low power-supply voltage (VDD), using a digital intensive design that avoids the use of bias voltage or current DACs, a low swing transmitter with a source-series terminated (SST) driver, and circuit and system co-design. To enable fast transitions between different active and standby power modes, a feedforward clock-and-data recovery (CDR) topology based on blind-oversampling is employed. A direct data-sequencing technique for blind oversampling is proposed that significantly reduces the area and power consumption of conventional techniques, while improving the low-frequency jitter tolerance as well. A prototype serial link comprising of the transmitter, receiver, and an all-digital phase-locked loop (ADPLL) achieves a data-rate of 1.2–5 Gb/s with total energy/bit of 1–1.31 pJ/b. The transceiver (TX and RX) itself has an energy/bit of 0.6 pJ/b. The link occupies an area of 0.041 mm2 in 22-nm CMOS technology and operates at VDD of 0.55–0.7 V.

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits.

Gate dielectric scaling is a vital key to improve the steep switching characteristics of TFETs. However, scaling down the oxide thickness causes high gate leakage current that cannot be neglected. The impact of the leakage current on the device operation can cause a serious reliability problem. In this paper, we have investigated the effect of nonuniform gate oxide thickness on the current as well as the high-frequency performance of TFETs. The focus of this paper is to demonstrate how to reduce effects of gate leakage current by using a taper shape gate oxide. The IV and CV characteristics are investigated regarding different nonuniform gate oxide graded shapes. Further, the ON and OFF currents and SS, as figures of merit for low standby power application, have been analyzed. Apart from this, the RF figure of merit in terms of unit-gain cutoff frequency (fT) is investigated.

Many emerging devices are currently being explored as potential alternatives to complementary metal-oxide-semiconductor technologies for overcoming power density and energy efficiency limitations. It is now generally accepted that these emerging devices need to be evaluated at the circuit level. In this paper, we investigate the speed and power performance of hyper-field-effect transistor (Hyper-FET) circuits, comparing them with both high-performance and low standby power fin-shaped FET designs on the same technology node. The evaluation, which was carried out at the gate level and circuit level, includes a characterization of 8-bit ripple carry adders. Our experiments showed around 80% speed degradation and 30% power savings for a given range of operating frequencies. These power savings were much smaller than those predicted from the transistor- and gate-level estimations. Deviations from the ideal expected behavior of the Hyper-FET circuitry are illustrated, which support the obtained results.

This paper implements a low-power PFM boost power converter that can be applied to low-voltage energy harvesting systems, such as in the IoT intelligent micro-sensing power module or energy harvesting interface circuit. The interface circuit can provide power management functions between the energy harvesting device and the electric load. The power converter uses the PFM feedback control mechanism to implement a boost converter which can stabilize the output voltage when the input voltage and load change. And when the input voltage of the PFM boost power converter circuit is less than the transition voltage of the Schmitt triggered inverter circuit, the PFM control circuit of the power converter will stop operating the feedback control regulation process, and the boost power converter will enter the standby mode. Therefore, the static power consumption of the boost power converter is minimized. The overall circuit is simulated and designed using TSMC 0.35um 2P4M CMOS process technology. The converter having 0.324x0.43015 mm2 chip size and power dissipation about 2.287mW. This chip can operate with input supply voltage from 2.0V to 2.5V, and its output voltage can stable at 3.0V and less than 20mV ripple voltage at maximum output current 10mA. The converter with a load regulation is less than 0.944mV/mA and the line voltage regulation is less than 34.6mV/V.

This paper presents cascade amplifier with parametric variation using CMOS technology which can be stimulated at lower technology node. Amplifiers used for high frequency operations and higher bandwidth designed by BJT technology undergoes various limitations like small scale integration, power consumption and high frequency operation. CMOS Technology has an edge over BJT in various terms like low power dissipation, large-scale integration and high speed. This paper reflects the advantages of using MOSFET Technology for direct coupled common emitter followed by common base amplifier where we try to apply parametric variations in the proposed work which directly reduces the leakage current and hence power consumption in CMOS Technology. This research depicts trusted changes in power consumption for CMOS based cascade amplifier as compared to conventional cascade amplifier. The research paper also shows high performance by changing “w/l” ratio as a process parameter for a particular Technology node. In this paper, chip variations and environmental variation including FinFET Technology are taken into account with material properties to reduce the power consumption of cascade amplifier in the standby mode. The proposed work has several applications in high frequency amplifier design where parameters associated with amplifier can be improved by parametric variation and proposed FinFET based amplifier design.

Scaling down of CMOS technology requires vital reduction of leakage power in low-power applications. Power gating technique is generally employed in the standby mode to reduce static power consumption but it increases delay of the logic cells badly and the ultimate result of the circuit is besmirched to a great extent in deep submicron circuits. This paper utilizes feedback mechanism for reducing dynamic and static power during active and standby mode, respectively, and power gating technique is also engaged for further minimizing static power during standby mode. Novel optimal power gates such as NOT, NAND, NOR, and EX-OR are developed and simulations are done with 45 nm CMOS technology and 0.6 V supply voltage for the 32-bit ripple carry adder. Proposed adder using optimal power NAND gate accomplishes 46 percent reduction in dynamic power consumption and 84.3 percent reduction in static power consumption and 28.98 percent reduction in power delay product.

This work presents the design of a sensor– actuator interface system developed for implantable applications. The analog front-end incorporates a high performance, low power and low noise, chopper stabilized current mode instrumentation amplifier for interfacing with MEMS-based micro-pressure sensors. This work also demonstrates a method for drug delivery actuation based on programmable pressure thresholding and mixed signal approach. The system further features a method for reducing standby power dissipation where the core circuits are disabled pending pre-set sufficient analyte volume and bandgap reference output. The overall system finds application in implantable systems based on micro-pressure sensing and actuation such as a closed loop automatic micturition (urinator) chip. The system consists of a high performance and ultra-low noise chopper stabilized instrumentation amplifier, a digitally programmable threshold generator and comparator circuit for setting up the pressure thresholds for urination, and an actuator model that simulates drug delivery for micturition, overactive bladder control, and bladder closure. The corresponding sub-circuits have been designed to operate in low power that is suitable for implantable applications and be powered by energy harvesters. SPICE simulations confirm the performance of the different system blocks under the physiological temperature range.

In this paper, a 20T high-speed wide voltage range level shifter using thin gate oxide devices is presented. The proposed circuit is realized to shift OV to 1.2V input signal to an output swing of OV to 6V. It ensures the safe operating area limit of thin gate devices in STMicroelectronics 65nm Low Standby Power (LSTP) triple well technology. The proposed design operates at 800MHz and has a low static power consumption of 112.91nW at 1.2V input. The proposed level shifter is variation tolerant and also works at input signals down to 0.5V. This enables wide voltage range operation in dynamic voltage and frequency scaling (DVFS). The total energy dissipation per transition is measured as 0.21pJ at a capacitive load of 35fF.

A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Reliability of power supply is an important component of enterprise efficiency and trouble - free operation of electrical equipment. In this paper, we propose a method for monitoring the phase difference and instantaneous voltage values between the residual load voltage and the standby power source in emergency mode to ensure the minimum starting current when the electric power reserve is automatically entered. The proposed method is based on the annealing method, which makes it possible to compare the accuracy of matching the residual voltage waveforms on the bus voltage and the standby power source, and is implemented in the MathLab environment. The simulation of the emergency process on the 10 kV bus section was carried out with the determination of the development time of the phase difference between the residual voltage on the load and the standby power source.

In this paper, we propose a power gating scheme for SRAM in latest bulk technology node for IoT applications. The scheme targets reduction of leakage of both the SRAM cell and the periphery logic. The deep sleep mode memory instance leakage power at TT/0.8V/25°C improves by 100× with respect to standby mode and 25× with respect to the conventional power gating schemes. We are able to achieve 0.25pA/bit of leakage in deep sleep mode. We also propose a leakage sensor-based scheme to reduce the retention mode leakage by 36% at high temperatures.

In this work, a smart temperature sensing chip is proposed for the applications of internet-of-things and wearable devices. A resistor-based temperature sensing bridge is integrated with a fully differential difference amplifier, a 10-bit successive approximation analog-to-digital converter, and timing circuits into a single chip. This chip is designed to sense temperature once per second, and is activated only 64 $\mu$ S per second and stays in the standby mode in the rest of time for reducing power consumption. The proposed chip is designed and fabricated by a 0.18m 1P6M mixed-signal process, and the total area is $953 \times 708$ $\mu m^{2}$. According to the measured results, the linearity between the measured temperature and the digital output is excellent, and it can work with a supply voltage ranging from 1.4 V to 2.0V.

There is a growing concern regarding the increased standby power and reduced stability of SRAM due to continued scaling in technology node. So, there is a necessity to design a new SRAM cell which addresses the concerns related to SRAM cell. So, 10T SRAM cell is proposed with reduced standby power and enhanced stability in read, write and hold modes of operation. There is a reduction in standby power because of the usage of stacked transistors. P10T SRAM cell has decreased the standby power while holding 1 by 4.9%, 15.99% and 1.68% compared to 8T, 8TG and 9T respectively at the worst process corner FF at 0.9 V VDD. There is an increase of 262.89, 47.566, 261.75% write margin compared to 6T, 8TG, 9T SRAM cells at 0.9 V supply voltage for TT corner. The influence of process and voltage variations on write margin was studied on available and proposed SRAM cells. All designs are designed using in cadence virtuoso in 45 nm CMOS technology node.

This paper presents an authentication IC in 65nm CMOS. The IC is interrogated using optical power transfer via off-chip photodiodes and visible light based data transfer via on-chip CMOS diodes. Authentication is performed with a lightweight encryption engine PRINCE. The IC consumes 2.29μW standby power and achieves 53.8kbps data rate. Side channel analysis is performed with results showing that 820K encryptions are necessary to reveal the secret key of the tag.

As the silicon industries miniaturizing the device size and increasing the performance day by day to implement more functionality in digital ICs. We will elaborate different techniques to put in to domino logic circuits. Power consumption can be minimize without deteriorating the performance circuit and efficiency of the circuit can be increases with proposed technique. Here we have use eight and sixteen input OR gates to calculate the UNG of the circuit with present and discussed design in Fin-FET and CMOS technology. With low power characteristics and great performance improvement in FinFET devices changes are obtained in higher I ON /I oFF ratio and the leakage current is reduced and it fastens the switching speed. Simulation is done on PTM 32nm process using H-spice C-2009.09-SP1 simulation tool by a 0.9 V dc supply. at 100MHz frequency. This work introduced a Low Power Stacked (LPS) FinFET based Domino logic 61.46% CKD, 49.08%, 29.18% DFD, 42.11% HSD, 29.36% SFD, saving of standby power of 18.79%, 46.15%,63.3%, in LP and SG mode of Fin-FET, for the 8 input OR gates.

It is essential to retain power and energy efficiency in low-power integrated circuits (ICs) over a wide load current/voltage range to reduce the consumption from the battery in portable/non-portable devices. The power/energy efficiency highly depends on voltage and frequency scaling when all the parts of the devices are in operation. There are also power and clock gating when all the parts of the devices are not in operation. The dynamic and static voltage scaling are main part for power gating. The power saving can be done by varying the supply voltage to ICs. The pulse width, pulse skip, depth and frequency modulation are common techniques for clock gating/frequency generation. The pulse width modulation (PWM) is generally used for fixed frequency operation. The pulse frequency modulation (PFM) is generally used for variable frequency operation depending on load voltage and current demands. The pulse skip modulation (PSM) is special technique to skip the pulses for frequency operation depending on IC operation mode (sleep mode and standby mode). In this chapter, all the existing techniques available for power reduction are discussed with the suitable diagram and examples.

Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON-to- OFF current ratio. In this article, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ON-OFF current tradeoffs are evaluated at the circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, based on this analysis, this article proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained, which were lower than those achieved with low standby power (LSTP) FinFETs and high-performance (HP) FinFETs. This article also evaluates the impact of PTM transition time on the power performance of HyperFET circuits. Ministerio de Economía y Competitividad, FEDER TEC2017-87052-P

This paper reports the first demonstration of Ultra-Low-Power (ULP) operation below 1 µW and noise reduction realized by a monolithic 3-axis accelerometer using a SiGe-MEMS-on-CMOS technique. In this work, the ULP operation is attributed to incorporating high-sensitivity SiGe-MEMS and low-power CMOS circuit with a monolithic configuration. The power consumption is confirmed to be 273 nW in an active mode and 160 nW in a standby mode. Furthermore, this work first evaluates the quantitative benefit of the monolithic configuration in view of noise reduction, and the result is a 30% lower noise density compared to a two-chip configuration using wire bonding, stemming from a 53% reduction of the parasitic capacitance. This work's approach enabling ULP operation and the noise reduction will contribute to the long battery life of sensors desired for IoT applications.

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.

In this paper, an ultra-low power and configurable IR-UWB transmitter is presented. The center frequency can be tuned from 500 MHz to 4.1 GHz. The configurability is achieved by the digitally programmable shunt capacitor delay elements. Shift registers are used to configure the delay lines and to minimize the number of pins used. The transmitter is capable of achieving 600 MHz pulse repetition frequency (PRF) with a 9.6 pJ/pulse performance at 4 GHz center frequency in the 3.1–5 GHz band. The standby power consumption is $$1.8\,\upmu \hbox {W}$$ .

Power gating circuits are utilized to manage power consumption and thermal stress in microprocessors and other high-performance integrated circuits. Most of the power gating techniques utilize sleep transistors in different configurations to reduce the subthreshold leakage current, which is the primary source of the standby power. These sleep transistors, which are added between the supply lines and the circuits as header and footer switches, impose additional area, delay, power, and other overheads and complexities. This brief introduces the concept of combining the functionality of the sleep transistors with the logic devices by utilizing fully depleted silicon-on-insulator (FDSOI) device. This FDSOI transistor-based power gating circuit design approach will eliminate the requirement of employing a separate set of sleep transistors to place the circuit in the sleep or idle mode. This will reduce the overall complexity and overheads of integrated circuits and simplify power gating techniques. In addition, it improves the overall power efficiency and lower thermal effects. SOI devices are becoming critically important for various very-large-scale integration applications, because SOI devices provide higher performance and reliability, and options to design circuits with multiple-threshold voltages to ensure faster switching and lower power consumption. In the proposed circuit design approach, the flexibility to control the threshold voltage of a double-gate FDSOI device via back gate has been exploited to eliminate the need for using a separate set of sleep transistors. The presented sleep transistor design is verified via HSPICE simulation using the Leti-UTSOI model from CEA-Leti .

This paper proposes a new 10-transistor (10T) bitcell for robust operations at subthreshold voltages without any boost circuitry. Features of the proposed bitcell include: 1) differential pre-discharged bit-lines and a pair of decoupled access ports to resist disturbance; 2) footed latch for write assist; 3) spare latch-foot to fight against half-select disturbances; and 4) highly stacked pull-down structure to reduce both leakage and power. A bit-interleaved SRAM macro, constructed with the proposed 10T bitcell, is fabricated in 28 nm CMOS. The power consumption has been measured as 90 nW for 30 kHz access at 0.25 V, and 41 nW for retention at 0.20 V, of which the leakage is 31% better than the state-of-the-art design.

TCAM (ternary content addressable memory) is a special memory type that can compare input search data with stored data, and return location (sometime, the associated content) of matched data. TCAM is widely used in microprocessor designs as well as communication chip, e.g., IP-routing. Following technology advances of emerging nonvolatile memories (eNVM), applying eNVM to TCAM designs becomes attractive to achieve high density and low standby power. In this paper, we examined the applications of three promising eNVM technologies, i.e., magnetic tunneling junction (MTJ), memristor, and ferroelectric memory field effect transistor (FeFET), in the design of nonvolatile TCAM cells. All these technologies can achieve close-to-zero standby power though each of them has very different pros and cons.

Emerging memories have been developed to achieve energy efficiency target in the Internet of Things era. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile (NV) memory has demonstrated attractive performance because of zero standby power, reduced switching power, infinite endurance, and high density. Meanwhile, hybrid STT-MTJ/CMOS integration is a promising solution to overcome the bottleneck of dynamic and leakage power dissipation. In this paper, ultralow power methodologies are developed at device and circuit level in 28 nm fully depleted silicon on insulator CMOS technology. Supply voltage scaling, near-/sub-threshold (V t ) operation, and back-bias adjustment are demonstrated, showing 81% dynamic power reduction under 0.6 V near-V t sensing operation, with the tradeoff of 6.2% increased sensing error rate. Through the case study on STT-MTJ-based NV flip-flops (NV-FFs), up to 76% dynamic and 79% leakage power saving can be realized in ultra-low power NV-FF implementation.

Zigbee SoC plays an important role in transferring and receiving the data in wireless sensor networks for its data security and high speed grade. The active mode of Zigbee SoC consumes power from power supply directly and standby mode of Zigbee SoC consumes no power from the power supply unit. There may be a leakage current in standby mode of the circuit which further linearly degrades the performance of the Zigbee SoC. This paper proposes a low power and high efficient active mode logic of the power gating methodology in Zigbee SoC to reduce the leakage current. The circuit in proposed Zigbee SoC has less number of transistors than the conventional methodology and hence the proposed system has low delay as 2.29 * 10–8 ms.

Supply voltage assignment (SVA) can alleviate the performance aging induced by the negative bias temperature instability (NBTI) effect. However, due to the random characteristic of an actual system workload, it is difficult to estimate the aging rate and control the supply voltage reasonably. To solve this problem, we present a workload-aware SVA method (WSVA) that encapsulates the workload change into the aging estimation using an LUT-based approach. Moreover, an NBTI and leakage co-optimization strategy based on an integer linear programming (ILP) approach is proposed to obtain the optimal input vector in standby mode. Simulation experiments on multiple benchmark circuits demonstrate that the LUT-based approach can track the dynamic change of the workload online and provide an accurate aging estimate for SVA with little computation cost. Compared with the SVA method without considering the workload, the proposed aging estimation approach and the optimal input vector selection strategy in the WSVA framework can enable the CMOS circuit conserve additional power dissipation while guaranteeing the performance requirements.