A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB

Maximizing the performance during peak workload hours and minimizing the power consumption during off-peak time plays a significant role in the energy-efficient systems. Our previous work has proposed an efficient architecture of a bitmap index creator (BIC) that produced higher indexing throughput than the central processing units and graphics processing units. This paper extends the previous study by focusing on the ASIC implementation of BIC in a 65-nm silicon-on-thin-buried-oxide (SOTB) CMOS process. The fabricated chip could operate at different supply voltages, from 0.4 V to 1.2 V. In the active mode with the supply voltage of 1.2 V, it was fully operational at 41 MHz and consumed 6.68 mW, or 162.9 pJ/cycle. In the standby mode with the supply voltage of 0.4 V and clock gated, the power consumption lowered to 10.6 μW. More significantly, when the reverse back-gate bias voltages are supplied, the standby power deeply reduced to 2.64 nW. This achievement is of considerable importance to the energy-efficient systems.