Search

In the realm of VLSI circuits, addition and multiplication are the most pivotal operators in arithmetic units. In this regard, this work aims to propose an energy efficient 4:2 precise compressor utilizing 10 nm wrap gate CNTFET technology. The proposed compressor is constructed from 2 hybrids 14-transistors full adders. The proposed Gate All Around (GAA) CNTFET based full adder employs a hybrid XOR/XNOR logic structure to lower the transistor count and power consumption. After performing rigorous simulations, we have demonstrated that the proposed GAA CNTFET based full adder and 4:2 compressor depict 175.3 nW and 308.5 nW power consumption respectively along with superior propagation delay response (4.4 ps and 10.57 ps respectively) at a 0.5 V nominal supply voltage. Moreover, the proposed designs occupy a lower layout area (0.195 μm2 and 0.43 μm2 for the proposed full adder and 4:2 compressor respectively) compared to the other counterparts. Our results accentuate the application of the proposed GAA CNTFET based 4:2 precise compressor for ultra miniature microprocessing systems.

Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are designed in 90-nm CMOS technology. According to simulation results, the proposed circuits have rail to rail output signals. Also, an improvement of 12%–52%, 7%–48% and 28%–68% has been achieved in delay, power consumption and power-delay product (PDP), respectively.

Carbon nanotubes are known as an interesting material to be used in the next generations of electronic technology, especially at nano regime. Nowadays, carbon nanotube field effect transistor or CNTFET is one of the promising devices for future electronic applications. A CNTFET which uses carbon nanotube as channel or source/drain region is the most promising candidate for replacing the current silicon transistor technology. The study of modern manufacturing approach and impact of device parameters on its performance is one of the important research fields in nanoelectronics. In this paper we study some aspects of changes in gate parameters at different channel diameters. This paper shows that for small values of diameter, increasing the dielectric constant of gate insulator doesn't help to improve the performance as value of dielectric constant of gate insulator reaches a certain amount. Also, increasing the oxide thickness of gate insulator doesn't always decrease transistor performance. For high diameter values, increasing the thickness up to a certain value improves the transistor performance.

This paper presents the design and simulation of improved circuits of Fuzzifier and capacitance to voltage (C2V) converter. The Fuzzifier circuit is designed based on analog advantages such as low die area, high accuracy, and simplicity which are added to the fuzzy system advantages. For implementing this idea, a programmable Membership Function Generator (MFG) including differential pair circuit as a Fuzzifier is proposed. The MFG generates arbitrary forms of Gaussian, Trapezoidal, and Triangular shapes. The shape types are achieved using control switches and different reference voltages. This structure is also general purpose in tuning the slope of Membership Functions (MFs) using scaled transistors with different W/L ratios. With a specific purpose in mind, we used it here to generate fuzzy language terms from sensed classic data of a blood glucose microsensor. Thus we proposed a C2V circuit to convert capacitance variations (from MEMS glucose microsensor) to voltage values as classic data. The proposed mentioned circuits can be applicable in design of Fuzzy Logic Controller (FLC) chips to detect blood glucose, process its data in Fuzzy environment, and control insulin injection of diabetic patients by MEMS micropumps. The simulation results are achieved by MATLAB and Hspice software in 0.35 μm CMOS standard technology.

Quantum cellular automata (QCA) represents an emerging technology at the nanotechnology level. There are various faults that may occur in QCA cells. One of these faults is the single electron fault that can happen during manufacturing or the operation of QCA circuits. The behaviour of the single electron fault in QCA devices is not similar to either previously investigated faults or conventional CMOS logic. A detailed simulation-based logic level modelling of the single electron fault for QCA binary wire is represented in this study. Results show that if a single electron fault occurs in a binary wire, then the logic value of that wire will be inverted.

Choosing a suitable doping level of channel relevant to channel diameter is considered for determining the carbon nanotube field effect transistors' performance which seem to be the best substitute of current transistor technology. For low diameter values of channel the ratio of on/off current declines by increasing the doping level. But for higher diameter values there is an optimum point of doping level in obtaining the highest on/off current ratio. For further verification, the variations of performance are justified by electron distribution function's changes on energy band diagram of these devices. The results are compared at two different gate fields., Comment: 9 double spaced pages, 4 figures, published in applied physics letters, along with the terms of the American Institute of Physics Transfer of Copyright Agreement at first page

Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency CMOS PLLs in 0.13/μm technology. The advantage of a single-ended control line is the reduction of area and power. It is, on the other hand, very critical to examine the performance of a differential control in high performance PLLs.

Many disturbances in the electronic systems of satellites are caused by the space radiations. Like other electronic systems, the electronic systems of satellites are subject to improve to nanoelectronic systems. Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. The effects of space radiations in QCA binary wire are investigated in this paper. Single Electron Fault (SEF) is a fault which may happen during operation of QCA circuits. A detailed simulation based logic level modeling of Single Electron Fault for QCA binary wire is represented in this paper.

In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are based upon UMC 0.13µm CMOS process at 1.2 V power supply. The simulation results show that the DLL can operate from 416MHz to 766MHz and the frequency multiplier synthesize frequency from 416MHz to 4.6 GHz. The proposed frequency multiplier possess the programmable function, and the output clock frequency are × 1, × 3 and × 6 of an input reference clock.

Nowadays carbon nanotube field effect transistor or CNTFET is one of the promising devices for future electronic applications. These transistors are frequently simulated using Non-Equilibrium Green's Function (NEGF) formalism. In this paper we study aspects of changes in gate parameters at different channel diameter which have not been known before. We find that in small values of diameter, increasing the dielectric constant of gate insulator doesn't help to improve the performance as value of dielectric constant reaches a certain amount. We also find that increasing the oxide thickness doesn't always decrease transistor performance. For high diameter values, increasing the thickness upto a certain value, improves the transistor performance.

Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. Nowadays, many applications of QCA technology are introduced and cryptography can be an interesting application of QCA technology. The original encryption algorithm for GSM was A5/1. Here, we have implemented the A5/1 stream cipher using QCA technology. Simulation results are obtained from QCADesigner software.

Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. Because of high speed, nanoscale size and ultra low power nature of QCA, cryptography can be an interesting application of QCA technology. QCA implementation of the Serpent block cipher is discussed in this paper. The basic modules of Serpent are implemented using QCA cells. It can be obviously seen that the implementation of cryptographic algorithms in this technology has considerable advantages compared to conventional CMOS approach.

Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. There are various faults which may occur in QCA cells. One of these faults is the Single Electron Fault (SEF) that can happen during manufacturing or operation of QCA circuits. A detailed simulation based logic level modeling of Single Electron Fault for QCA binary wire is represented in this paper.

Quantum cellular automata (QCA) represents an emerging technology at the nano technology level. Nowadays, many applications and design methods of QCA technology are introduced. Defect tolerant design of QCA circuits is a challenging case. Here, we will investigate the effects of single event upsets (SEU) on QCA circuits and the defects which may occur.

Quantum Cellular Automata (QCA) represents an emerging technology at the nano technology level. Nowadays, many applications of QCA technology are introduced and cryptography can be an interesting application of QCA technology. Substitution boxes are important components in many modern day block and stream ciphers. Here, we have implemented a specific 4×4 S-Box using QCA technology. Simulation results are obtained from QCADesigner software.

Quantum Cellular Automata (QCA) represents an emerging technology at the nanotechnology level. There are various faults which may occur in QCA cells. One of these faults is the Single Electron Fault (SEF) that can happen during manufacturing or operation of QCA circuits. A detailed simulation based logic level modeling of Single Electron Fault for QCA Inverter gate is represented in this paper.

Analog integrated filters are mainly used in a stage prior to A/D convertors in analog-digital systems as anti-aliasing filters. This paper presents a 3rd order transconductance-C (Gm-C) anti aliasing filter (AAF) as part of the front-end analog circuits of DRB receivers. In the present work we have minimized the power consumption and the number of transistors in such circuits. The anti-aliasing filter is designed and simulated using 0.18 um CMOS technology. The circuit consumed 233.25 micro Watts through a 1.8 V power supply with a cut-off frequency of 22.5 MHz.

Quantum cellular automata (QCA) represents an emerging technology at the nano technology level. Nowadays, many applications of QCA technology are introduced while programmability can increase the flexibility of QCA implementations. Using the structure of FPGAs can lead to flexible QCA implementations. So, we have implemented a MUX-Based FPGA CLB. This CLB has 3 multiplexers and each multiplexer is composed of 34 QCA cells.

During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need of modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using ordinary differential algebraic equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design community, efficient semiconductor device models must be available. In this paper potential merits of the new IEEE VHDL-AMS standard in the field of modeling of semiconductor devices are discussed. The device models for diodes and the principles, techniques and methodology used to achieve the design of an analytical third generation Spice transistor MOS model named EKV are presented. This is done by taking into account the thermoelectrical effect with VHDL-AMS, and with relevant parameters set to match a deep submicron technology developed in VHDL-AMS. The models were validated using system vision from mentor graphics.

Substrate noise is a key problem in the design of large mixed-signal circuits. Estimating the interaction from large digital blocks and its effect on on-chip performance degradation is extremely important in mixed-signal IC design and is a major challenge in system-on-chip (SOC) design. In this paper, we address efficient methods and models to simulate substrate noise coupling at high level design with the real-time capability. An efficient, fast and real time macromodel is presented. Extracted macromodel captures a variety of noise interference mechanisms, including power/ground bounce, IR drop, switching coupling noise and interconnect noise sources. Techniques to directly or indirectly compute the values of the elements in the cell macromodel are described. This approach makes it possible to predict substrate noise generation of large digital blocks in a very efficient and fast way and makes it compatible with the design flow of mixed-signal circuits. For verification, the macromodel accuracy is demonstrated in some example circuits.

The current-mode instrumentation amplifier based on second-generation current conveyors (CCII) offers many benefits over conventional instrumentation amplifier architectures. It does not need any matched components to achieve high CMRR and its bandwidth is not gain-bandwidth product limited. Therefore, the wideband CMOS current conveyor has been used in this structure. HSPICE simulations have shown that its performance is quite satisfactory for wideband current-mode signal processing. Furthermore, different CMRR enhancement techniques of current-mode instrumentation amplifiers are discussed. The new simulated instrumentation amplifier provides approximately 40 dB of improvement on the high-frequency CMRR up to the 3-dB corner frequency and even higher. In addition, composite conveyor techniques improving the instrumentation amplifier performance are presented.

Quantum cellular automata represents an emerging technology at the nanotechnology level. There are various faults which may occur in quantum cellular automata cells. One of these faults is the single electron fault that can happen during manufacturing or operation of quantum cellular automata circuits. The behavior of single electron fault in quantum cellular automata devices is not similar to either previously investigated faults or conventional complementary metal oxide semiconductor (CMOS) logic. A detailed simulation based logic level modeling of single electron fault for quantum cellular automata binary wire and majority gate is represented in this paper. Results show that if a single electron fault occurs in a binary wire, the logic value of that wire will be inverted and if a single electron fault occurs in a majority gate, the logic value of that gate will be changed.