Two new energy-efficient full adder designs

Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are designed in 90-nm CMOS technology. According to simulation results, the proposed circuits have rail to rail output signals. Also, an improvement of 12%–52%, 7%–48% and 28%–68% has been achieved in delay, power consumption and power-delay product (PDP), respectively.