Design and simulation of a CMOS DLL-based frequency multiplier

In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are based upon UMC 0.13µm CMOS process at 1.2 V power supply. The simulation results show that the DLL can operate from 416MHz to 766MHz and the frequency multiplier synthesize frequency from 416MHz to 4.6 GHz. The proposed frequency multiplier possess the programmable function, and the output clock frequency are × 1, × 3 and × 6 of an input reference clock.