4,359 results on '"Integrated circuits -- Intellectual property"'
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2. Researchers Submit Patent Application, 'Semiconductor Integrated Circuit Device', for Approval (USPTO 20240421089)
3. Researchers Submit Patent Application, 'Integrated Circuit Workload, Temperature, And/Or Sub-Threshold Leakage Sensor', for Approval (USPTO 20240418770)
4. Researchers Submit Patent Application, 'Semiconductor Device And Method Of Forming The Same', for Approval (USPTO 20240422958)
5. Researchers Submit Patent Application, 'Inverted Gate Cut Region', for Approval (USPTO 20240420959)
6. Researchers Submit Patent Application, 'Integrated Thermal Bridges On Wirebond Assembled Integrated Circuits For Heat Spreading', for Approval (USPTO 20240421092)
7. Researchers Submit Patent Application, 'Fpga Wide Barrel-Shifters Implementation Using Packed Dsp Multipliers', for Approval (USPTO 20240419446)
8. Patent Issued for Surge protection in semiconductor integrated circuit and semiconductor memory device (USPTO 12170440)
9. Patent Issued for Microprocessor with a time counter for statically dispatching extended instructions (USPTO 12169716)
10. Patent Issued for High voltage MOSFET device with improved breakdown voltage (USPTO 12170329)
11. Patent Application Titled 'Semiconductor Devices With Different Gate Dielectric Thicknesses' Published Online (USPTO 20240421209)
12. Patent Application Titled 'Semiconductor Device And Method Of Forming The Same' Published Online (USPTO 20240421184)
13. Patent Application Titled 'Reduction of Air Gaps in FinFET Structures' Published Online (USPTO 20240420998)
14. 'Semiconductor Package' in Patent Application Approval Process (USPTO 20240421143)
15. 'Recess Poly Esd Diode For Power Mosfet' in Patent Application Approval Process (USPTO 20240421147)
16. 'Electro-Photonic Transmitter And Receiver Integrated Circuits (Chiplets) For Co-Packaged Optics And Methods Of Operation' in Patent Application Approval Process (USPTO 20240421909)
17. Researchers Submit Patent Application, 'Multilayer Moisture Repelling Films For Front End Fet Applications', for Approval (USPTO 20240413098)
18. Researchers Submit Patent Application, 'Heat Radiation Devices', for Approval (USPTO 20240413053)
19. Researchers Submit Patent Application, 'Memory Structure', for Approval (USPTO 20240412772)
20. Patent Application Titled 'Semiconductor Memory Devices Having Enhanced Sub-Word Line Drivers Therein' Published Online (USPTO 20240412773)
21. 'Contact Assembly For Power Semiconductor Chips And Power Electronics Module' in Patent Application Approval Process (USPTO 20240413119)
22. Researchers Submit Patent Application, 'Semiconductor Device With Esd Protection Structure And Method Of Making Same', for Approval (USPTO 20240405015)
23. Researchers Submit Patent Application, 'Integrated Circuit With Supply Voltage Detector', for Approval (USPTO 20240405538)
24. Patent Application Titled 'Semiconductor Integrated Circuit, System On Chip And Electronic Device To Implement Them' Published Online (USPTO 20240405011)
25. Researchers Submit Patent Application, 'Structure To Reduce Chip Shift During Assembly', for Approval (USPTO 20240395758)
26. Patent Issued for Ohmic contacts for a high-electron-mobility transistor (USPTO 12154961)
27. Patent Issued for Methods for producing a 3D semiconductor memory device and structure (USPTO 12154817)
28. Patent Application Titled 'Stacked Hybrid Tfet And Mosfet' Published Online (USPTO 20240395814)
29. Patent Application Titled 'Semiconductor Chip And Semiconductor Package Including Same' Published Online (USPTO 20240395672)
30. Patent Application Titled 'Integrated Circuit' Published Online (USPTO 20240397709)
31. 'Semiconductor Chip' in Patent Application Approval Process (USPTO 20240395944)
32. Patent Issued for Semiconductor device (USPTO 12148716)
33. Patent Application Titled 'Bellows For Immersion Cooling' Published Online (USPTO 20240389268)
34. Patent Application Titled 'Integrated Circuit Device And Electronic System Including The Same' Published Online (USPTO 20240389325)
35. Researchers Submit Patent Application, 'Photonic Waveguide Power And Phase Monitor', for Approval (USPTO 20240385243)
36. Researchers Submit Patent Application, 'Light-Emitting Semiconductor Chip And Method For Producing A Light-Emitting Semiconductor Chip', for Approval (USPTO 20240387778)
37. Patent Application Titled 'Systems And Methods For Interconnecting Dies' Published Online (USPTO 20240387390)
38. 'Clustering Clock Chain Data For Test-Time Reduction' in Patent Application Approval Process (USPTO 20240385241)
39. 'Battery Modules With Integrated Module Converters And Methods Of Operating Thereof' in Patent Application Approval Process (USPTO 20240383375)
40. Researchers Submit Patent Application, 'Vertical Mosfet Using A Silicon Carbide Layer And A Silicon Layer For Improved Performance', for Approval (USPTO 20240379838)
41. Researchers Submit Patent Application, 'Semiconductor Device', for Approval (USPTO 20240381617)
42. Researchers Submit Patent Application, 'Four-Terminal Resistance Testing Structure', for Approval (USPTO 20240379472)
43. Patent Issued for Radiation-emitting semiconductor component and method for producing radiation-emitting semiconductor component (USPTO 12142712)
44. Patent Issued for Method of detecting a possible thinning of a substrate of an integrated circuit via the rear face thereof, and associated device (USPTO 12142536)
45. Patent Issued for 3D semiconductor device and structure with bonding and memory cells preliminary class (USPTO 12144190)
46. Patent Application Titled 'Wafer Chip Scale Package' Published Online (USPTO 20240379597)
47. Patent Application Titled 'Semiconductor Package' Published Online (USPTO 20240379575)
48. Patent Application Titled 'Semiconductor Device Including Buried Word Line' Published Online (USPTO 20240381614)
49. Patent Application Titled 'Integrated Circuit Metal Gate Structure' Published Online (USPTO 20240379811)
50. 'Semiconductor Packages And Substrates For Packages' in Patent Application Approval Process (USPTO 20240379524)
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