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A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

A novel data-sparsification method for multi-channel radiation detector readout ASICs is proposed. Based on the self-triggering approach, the scheme operates as follows: when one channel is being read out, the trigger signal from other channels is delayed one or more clock cycles and then processed. In this way, the dead time, during which the circuit fails to respond to the input, is reduced and so is the error rate. A 16-channel readout ASIC has been designed in a 0.5um DPTM CMOS technology. The feasibility of this novel sparse readout method is verified by simulation. Theory analysis and calculation show that the error rate is approximately 2.5%, and is reduced by about 37% compared with the conventional scanning scheme, assuming a 16-channel system with an event rate of 100 K/s per channel.

This paper presents a low jitter adaptive-bandwidth charge pump PLL with an improved passive filter. With an adaptive bandwidth, the proposed PLL maintains optimal performance over its whole operating range. In order to improve the jitter performance of the PLL, matching technique is employed in the charge pump, and a voltage-to-voltage converter is used to achieve a low gain VCO. The novel circuit has been implemented in 0.35 mum CMOS process. Post simulation results show that the PLL can scale its loop dynamics proportional to the operating frequency and has good jitter performance within its operating range from 100 MHz to 1.1 GHz.

This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.

A novel column readout architecture for infrared (IR) readout integrated circuit (ROIC) is proposed in this paper. When the readout rate is 5M Hz, by applying master-slave column amplifier and the technology of divided-output-bus, the power of the column readout stage has been reduced from more than 47mw to 6.74mw, which reduced more than 85%. In the master-slave readout structure, master amplifiers convert the charge to voltage, which have relaxed time limit. Slave amplifiers drive the output bus and ensure the readout rate, which adopts low power standby work mode. The technology of divided-output-bus is to divide the 320 pairs of switches to 20 groups and reduces the switches connected to the output bus, which does help to reduce power dissipation of slave amplifiers. A 320X288 IR ROIC with pixel size of 30X30μm2has been designed with this architecture which based on CSMC 0.5μm DPDM n-well CMOS process.

The paper presents a power analysis model for adiabatic SRAM. According to different performance frequency and different memory size, we simulate, analyze and compare adiabatic SRAM's power characteristics and propose the model. Based on the power analysis model, a scheme of array-division for adiabatic SRAM is presented. With array-division structure, the power dissipation is related to m, which is the array-division value. When the value increases, the main source of SRAM power is changed from word-line and cell-clock to decoder

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed

A novel method to adjust gain in CMOS infrared (IR) readout integrated circuit (ROIC) which is suitable for the application of small pixel size has been proposed in this paper. Current mirror is inserted in the pixel to adjust gain. Two comparators have been added outside of the pixel and provide the decision to select different gains. Adjustable gain makes the design of following signal process circuit easier and allows long integration time to increase SNR. With this method of automatic gain adjust, ROIC can deal with the current that varies from 40nA to 300nA, with the integration capacitor of 2pF and the integration time of 40/spl mu/s. An experimental 4/spl times/4-pixel ROIC has been designed and it will be fabricated with 0.5/spl mu/m DPDM n-well CMOS process.

A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor C/sub n/ and coupling resistor R/sub n/ can be calculated to improve the efficiency of GCNMOS ESD protection circuit.

SRCMOS (self-resetting CMOS) is one kind of popular technique which can be used for designing high-speed circuits. This paper presents a new kind of locally self-resetting SRCMOS technique. According to the operational principle that the reset signal is generated by a mechanism local to its stage, the technique can realize high-speed circuits and has low design complexity. Based on the locally SRCMOS technique, the paper presents the design of a 32 word/spl times/64 bits 2write/6read eight-port register file. Using 1.8 V 0.18 /spl mu/m CMOS technology, simulation results show that the write access delay of the register file is 700 ps, and read access delay is 910 ps.

A novel dual-window readout structure is presented in this paper. The ROIC with this structure can work in two modes: normal mode and windowing mode. The most special feature is that ROIC can readout two sub-arrays synchronously in windowing mode. Furthermore, the positions and sizes of these sub-arrays can be specified by users. This feature allows image system to trace two fast moving objects without using two ROICs. An experimental 64/spl times/64-pixel ROIC has been designed, and it will be fabricated with 0.5/spl mu/m DPTM n-well CMOS process.

Design of CMOS high-speed self-regulating voltage-controlled oscillator (HSSR VCO) using negative skewed delay scheme is presented in this paper. With a SMIC standard logic 0.18-/spl mu/ 1.8V CMOS process, the simulation results show that the HSSR VCO can work at 2.2 GHz with good linearity in frequency-voltage space as over an acceptable tuning range as well as a built-in compensation for the delay variation caused by supply fluctuation.

An improved CMOS snapshot readout structure called RRSCA (Reset Row-by-row Snapshot Charge Amplifier) for infrared focal plane array (IRFPA) is presented in this paper. The pixel circuits in RRSCA readout structure are reset row by row after each row's pixel signals were readout to the column stage in parallel and pixel circuit is very simple including only three MOSFETs. Thus, the RRSCA readout structure is very suitable for the readout circuit design with large-format and very small pixel size such as 30*30 or 25*25 mm2. An experimental 130 t 130 RRSCA chip has been fabricated with 1.2-mm Double-Poly Double-Metal (DPDM) n-well CMOS technology. Both simulation results and experimental results are presented.

This paper details a high performance CMOS linear readout integrated circuit (ROIC) and the measured result. This ROIC realizes time-delay integration (TDI) to enhance the signal to noise ratio (S/N), and defective element deselection (DED) to decrease the probability of bad columns. The Other features include adjustable integration time, multi gain, bi-direction of TDI scan. super-sample, and electrical test. It is fabricated using 1.2-mm double poly double metal (DPDM) CMOS technology. The total power consumption is about 24 mW at 5 V supply voltage.

A multi-layer modeling approach is proposed in this paper for creating behavioral models of charge-pump phase-locked loops, which offers great flexibility of trading off between the simulation speed and accuracy. Also the approach allows time domain noise simulation with a specific layer. A multi-layer Verilog-A charge-pump PLL model is created to illustrate the proposed approach. A simulation speed up factor of 12 to 99 is achieved with reasonable loss of accuracy.

The digital comparator is a widely used circuit block. The typical versions using static CMOS logic have been well known. In this paper we present a new efficient design-MCP, which employs Manchester chain to fulfil the compare operation. Compared with the static implementations, MCP's highest operating frequency (125 MHz) is much higher. At the same operating frequency, MCP's power dissipation is 15%-22% lower than static version's. The layout area of MCP is only 87.6% of the static's and it is very convenient for implementing parallel or pipeline structure that is important for high performance VLSI design. By a series of optimizations the MCP gained a good noise immunity, though it is sensitive to noise glitches for its dynamic structure. MCP is a high quality function block and suitable for high performance VLSI design.

An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.

Thispaperdescribesan8-bit125MHzlow-powerCMOSfully-foldinganalog-to-digitalconverter(ADC). A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5 m CMOS technology and occupies a die area of 2 × 1.5 mm 2 . The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. In this paper, a novel mixed-averaging distributed T/H circuit is proposed which improves the accuracy and provides a better tradeoff between accuracy, size and power dissipation. In addition, a novel bit synchronization architecture is pre- sented to reduce the number of comparators, and this architec- ture employs folding circuits to produce a bit synchronization signal. Therefore, folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchroniza- tion block. A special low-power CMOS ADC is designed and only 22 comparators are used in the whole ADC. The ADC is implemented in 0.5 m CMOS technology. Measured results show that the power dissipation of the ADC is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

With analyzing features of the accumulator in numerically controlled oscillator (NCO), it is pointed out that design based on pipeline for NCO is feasible. The schematic and results of logic simulation are given in this paper. The pipeline based NCO has evidently more advantages: higher speed (about twice) and fewer components (about 2/3) than usual. >