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We propose a new approach for the extraction of the equivalent parameters of quartz tuning forks used as sensors by means of noise measurements. Noise is used as the test signal for the determination, by means of spectral analysis, of the frequency response of a circuit including the quartz tuning fork whose parameters need to be determined. A new approach for the analysis of strongly peaked noise spectra was developed in order to allow the correct measurement of the strongly peaked noise spectrum at the output of the system, which is the result of the high-quality factor of any quartz tuning fork-based sensor. With the approach we propose, the best compromise in terms of accuracy and measurement time can be obtained in a single measurement run. The performances of the approach we propose are discussed in comparison with those that can be obtained from a swept spectrum approach in the same operating conditions.

The main requirement for using the Fluctuation Enhanced Sensing technique is the ability to perform low-frequency noise measurements. The portability of the measurement system is also a quite desirable feature not limited to this specific application. In this paper, an approach for the realization of a dual channel spectrum analyzer that is capable of exploring frequencies down to DC, although based on a USB sound card, is proposed. The lower frequency range of the input signals, which is outside the frequency range of the sound board, is upconverted to higher frequencies by means of a very simple modulation board. Then, the entire spectrum is reconstructed numerically by proper elaboration. With the exception of the modulation board, the approach we propose does not rely on any specific hardware. Thanks to the efficiency of the spectra estimation and reconstruction software, which is based on a public domain library, the system can be built on a low-cost computer single board computer, such as the Raspberry PI3. Moreover, when equipped with an optical TCP/IP link, it behaves as a compact spectrum analyzer that along with the device under test can be placed into a shielded environment, thus being isolated from external electromagnetic interferences.

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μFE> 1 cm2V−1s−1) and excellent stability under gate bias stress (bias stress Vds = 0V). However, after prolonged bias stress performed at high drain voltage, Vds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high Vds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed in detail the physics of operation and the performances of FB-DRAM cells based on JL transistors including the effect of Trap-Assisted-Tunneling (TAT), neglected in most of previous works. As expected, TAT severely limits the retention time due to the large doping, in particular during HOLD operation. The discussion is supported by 2D device simulation on a double gate junctionless transistor including the effect of statistical variability induced by random dopant fluctuations, and the technology (bandgap, lifetime) scaling. It is found that the cell, at least at the nanoscale, can work only by independent gate operation, having maximum performance when the bottom gate works at the limit of the BBT bias region during READ, and that at a gate length as large as 100 nm and fin width of 10 nm the cell can sustain the high doping induced variability to a retention time in the order of 1 ms, while the use of materials with higher bandgap (~1.3 eV) than Silicon can improve the retention time to the order of 10 ms. However several concerns remain on their actual use related to the necessary bias level and to the impact of the actual technologies on the lifetime, which strongly affects TAT degradation.

One-Transistor (1T) DRAMs are one of the potential replacements for conventional 1T-1C dynamic memory cells for future scaling of embedded and stand-alone memory architectures. In this work, a scaled (channel length 10nm) floating body 1T memory device architecture with ultra-thin body is studied, which uses a combined approach of a body raised storage region and separated source/drain regions having the role to reduce thermal and field enhanced band-to-band recombination. The physical mechanisms along the geometry and bias scaling are discussed in order to address the requirements of embedded or stand-alone applications. Two-dimensional device simulations show that, with proper optimization of the geometry and bias, the combined approach allows the increase of the retention time and of the programming window by more than one order of magnitude.

Knee injuries are among the most common health problems in the world. They not only affect people who practice sports, but also those who lead a rather sedentary life. Factors such as age, weight, working and leisure activities can affect the health of the knees, causing disorders such as inflammation, edema, deterioration of cartilage and osteoarthritis. Although for the diagnosis and treatment of the various pathologies it is always advisable to contact orthopedists and specialized structures, it would often be useful to monitor the state of health of the knees in order to evaluate the healing (or worsening) process and the effects of sport/motion activities or rehabilitation. In this perspective, a portable knee health monitoring system was developed to be used at home or in gyms and sports environments in general. Besides requiring a simple custom front end, the system relies on a PC audio board capable of a sampling rate of 192 kHz to perform bioimpedance measurements at frequencies in excess of 50 kHz. A simple numerical calibration procedure allows to obtain high accuracy while maintaining low hardware complexity. The software developed for the operation of the system is freely available to any researcher willing to experiment with the bioimpedance measurement approach we propose, ensuring the conditions of portability and low complexity. Primary (intracellular and extracellular resistances and cell membrane capacitance) and secondary (real and imaginary parts of the total impedance) bioimpedance parameters can be obtained and analyzed through direct measurements with reference to an equivalent circuit model. The functionality of the system has been tested on nine subjects with different well-known health conditions, providing encouraging results in terms of the ability to correlate bioimpedance measurements to the health status of the knees. If proper clinical trials were to confirm our preliminary results, a system such as the one we propose could be used for fast and frequent monitoring of knee joints, thus possibly reducing the frequency at which complex and expensive medical exams, sometimes involving long waiting lists, must be performed.

It is shown how some photovoltaic MOSFET drivers can be used for the realisation of a low noise, programmable voltage source, with a dynamic range that can easily exceed several tens of volts starting from standard ± 12 V power supplies. Such a source can be useful in the investigation of the electrical properties, and particularly noise properties, of organic thin film transistors on plastic substrates, since relatively large gate voltage sweeps are required in order to obtain a significant change in the conduction properties of the channel.

Focusing on the interplay between interface chemistry, electrochemistry, and integrated electronics, we show a novel low-cost and flexible biosensing platform for continuous glucose monitoring. The amperometric biosensing system features a planar three-electrode structure on a plastic substrate, and a wireless near-field communication-powered electronic system performing sensor analog front-end, A/D conversion, digital control, and display tasks. The working electrode is made of electropolymerized poly (3,4-ethylenedioxythiophene) film onto a polyethylene terephthalate/gold electrode followed by immobilization of cross-linked glucose oxidase by glutaraldehyde. The advantages offered by such a device, including low-cost materials and instrumentation as well as the good sensitivity of 9.24 $\mu \text{A}/({\mathrm {mM}} \cdot {\mathrm {cm}}^{2})$ are promising tools for point-of-care monitoring. It is demonstrated that the devices are good candidates for the development of advanced sensing approaches based on the investigation of the noise produced during operation (fluctuation-enhanced sensing).

We propose a simple topology for the realization of ultra low noise differential-input, differential-output preamplifiers. The input devices can be either low noise JFET pairs (for high impedance sources) or low noise BJT pairs (for minimum low frequency voltage noise). Besides the input devices, the circuit requires only two matched low noise BJT transistor pairs (either PNP or NPN, depending on the input device type) and a few excess noise free resistors for consistently obtaining differential gains of 100 (40 dB) with a bandwidth in excess of 100 kHz and an equivalent input noise floor comparable to (or better than) those reported in the literature for similar devices. The preamplifier is to be regarded as an off-the-shelf component that can be employed as a building block for a number of applications in the field of low frequency noise measurements.

When performing voltage noise measurements on a biased device, the DC component due to the bias must be rejected in order to avoid saturation of the high gain low noise input stage of the voltage amplifier employed to raise the level of the signal prior to sampling for spectral analysis. This is normally done by interposing an RC high pass filter between the device and the DC coupled amplifier input. The problem with this approach is that in order to reduce the noise contribution coming from the resistance R in the filter, its corner frequency must be chosen much smaller than the minimum frequency of interest, thus resulting in extremely long transients upon device connection or bias change. In order to address this problem we propose to employ a low noise, programmable floating voltage source that, together with a proper feedback loop, behaves as a noiseless AC coupling filter, thus allowing to considerably reduce the duration of the transients.

We report on experiments performed in order to verify the ability of low frequency noise measurements to serve as a sensitive tool for the characterization of the degradation of electron devices on flexible substrates as a consequence of mechanical stress. We designed and build a dedicated stress chamber for performing stress (repeated bending) in controlled environmental conditions. Test devices are copper resistance onto plastic substrates. We observe that, whenever the flicker noise produced by the resistances is clearly detectable, the level of flicker noise increases as the mechanical stress increases. In some cases noise increment of 100 % are observed when the change in the DC resistance of the sample is as low as 0.1%.

We present, for the first time, Low Frequency Noise measurements in Vertical Organic Transistors. Investigated devices are p-type Metal-Base Organic Transistors employing Pentacene and Copper Phthalocyanine as active layers for the Emitter and Collector regions, respectively. The power spectral densities measured at the Base and Collector terminals follow a 1/fγ law, with γ≈1, suggesting that noise is generated, in both cases, by a continuous distribution of traps. Cross-correlation measurements show that Base current noise and Collector current noise are uncorrelated meaning that the physical origin of the noise measured at the Base and Collector terminals is different.

Vertical organic transistors are a promising candidate to overcome the scaling limits of conventional horizontal organic field-effect devices. In this paper, based on the results of direct current (dc) and low-frequency noise (LFN) measurements, we propose a picture for the carrier transport in metal-base organic transistors in which transmission across the base is due to the combined action of both hot-carriers (HCs) and high-conduction paths (pores) in the metal base. Investigated devices employ pentacene and copper phthalocyanine as active layers for the emitter and collector regions, and a bilayer consisting of Au/MoO3 as injecting electrode. The dc analysis highlights that the charge transport in the investigated devices is due to drift diffusion of the emitter-injected carriers in the highest occupied molecular orbital (HOMO) band and is dominated by HC injection, although conduction via pores increases and becomes not negligible at high base–emitter fields. The LFN analysis highlights the presence of two dominant and uncorrelated 1/f current noise sources, one located between base and emitter, due to the fluctuations of the not-transmitted HC current, and a second source located between collector and emitter, due to the fluctuations of the transmitted HC current and/or to the fluctuations of the current through the pores in the metallic base.

SUMMARY Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low-noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt-shunt configuration, the equivalent input noise decreases as the feedback resistor (RF), which also sets the gain, increases. Unfortunately, as RF increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of RF and reduces as RF increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large-bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/, corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.

Floating Body one transistor Dynamic Random Access Memories (FBRAMs) have been widely studied and proposed in the literature as an alternative for conventional one transistor/one capacitor DRAMs. FBRAM performance depends on charge degradation during READ and HOLD operations and on the body effect during READ operation, the first setting the amount of the residual non-equilibrium charge during READ operation, and the second setting the effectiveness of this residual charge to modulate the source-body barrier during READ operation. In this work it is proposed a simple analytical charge-based compact model for the body-effect in FBRAMs which is able to reproduce device performance in terms of READ Sense Margin and current ratio. Physical insights of the body effect and charge degradation mechanisms, with particular emphasis to their bias dependence, are discussed in detail. Conclusions can be useful for the choice and the optimization of the bias in FBRAMs. All the discussion is supported by two-dimensional drift–diffusion device simulation on a template double-gate MOSFET.

In this paper, we discuss a few techniques that allow an effective reduction of the background noise and/or the reduction of the measurement time when performing voltage noise measurements by employing a number of nominally identical voltage amplifiers with negligible equivalent input current noise. It is demonstrated in particular that, if $N\ (N > 2)$ voltage amplifiers are connected to the device under test and if the properties of cross-correlation among all $N$ acquisition channels connected to the output of each amplifier are exploited, the time required for obtaining a given accuracy is reduced by a factor $N(N - 1)/2$ with respect to the conventional setup for cross-correlation that employs only two channels. From another point of view, the effective background noise is reduced for constant measurement time. Such a factor can be further increased if amplifier paralleling is also employed for reducing the equivalent input voltage noise for each channel. Measurements on two different setups employing up to four channels and up to eight channels are presented that confirm the expected reduction factors in measurement times.

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/ $f$ behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility ( $\mu _{{\mathrm{eff}}}\sim $ 2 cm2/V/s), the large scattering parameter ( $\alpha \sim 10 ^{7}$ Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product $\alpha \mu _{{\mathrm{eff}}} \approx 2\cdot 10^{7}$ cm2/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance–voltage, and noise measurements. Results suggest that transport in the CYTOP™ gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier $\phi _{B} \approx 1$ eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility $\mu \theta $ estimated in the order of $10^{-9}$ cm2/(Vs). Gate current noise follows a 1/ $f$ law and it is found to be proportional to $I_{G}^{2}$ , which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

Strontium titanate (STO) has been proposed as dielectric material in metal-insulator-metal (MIM) capacitors for future DRAM generations due to its higher dielectric constant and corresponding lower equivalent oxide thickness. In this letter, we show for the first time the impact of electrode composition and processing on the low-frequency noise (LFN), hence on the device material defectiveness, in large area (1000 μm × 1000 μm) MIM capacitors with STO dielectric (EOT is ~0.4nm, physical thickness is ~8.5nm) and Ru/TiN or TiN as metal electrodes. LFN measurements show that the power spectral density (S IG ) associated with gate current (I G ) fluctuations follows a 1/f shape and that SIG αI α G with α measured between 1.6 and 1.9. In particular, it is shown that PVD processing for top electrode Ru in place of chemical vapor deposition processing results in a significant (more than three decades) noise reduction (lower trap density) according to the observed lower gate leakage (

In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the total retention time is limited by the leakage associated with state “0” due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time.

In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.

Low-frequency (LF) analysis is applied to advanced memory devices in order to characterize, quantify and identify defects affecting their performance. In single-transistor (1T) Floating-Body Random Access Memory (FBRAM) on Ultra-thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI), it is shown that the retention time behavior can be explained by the traps giving rise to Generation-Recombination noise. In conventional DRAM technology, the capacitor leakage is one of the most serious showstoppers for scaling down. The analysis of the 1/ƒ noise in the gate leakage current of STO-based DRAM Metal-Insulator-Metal (MIM) capacitors shows a strong impact of the gate stack on the defect density.

A test and measurement system for the characterization of standard 32 kHz tuning fork crystal based sensors is proposed. A very simple circuit configuration provides for a white noise voltage test signal to be applied to the tuning fork device and to a variable capacitor that, in combination with a differential transimpedance amplifier, allows to detect and amplify the current through the device subtracting the effect of the intrinsic and external stray capacitance. The white noise signal and the output of the transimpedance amplifier are fed to the left and right channels of a PC sound board that provides for signal elaboration and direct extraction of the sensor admittance vs frequency.

In this work we propose a measurement setup topology suitable for the automatic DC and low frequency noise (LFN) characterization of field effect transistors at wafer level. The system is composed of source and measure units (SMUs), by a custom-built low noise amplifier (LNA), and by a PC based spectrum analyzer. No bias filters and switch matrices are used, allowing fast switching between DC and LFN measurements together with low leakage. The programmable LNA can reach background noise levels in the order of fA/Hz1/2, while DC performances are limited by the SMUs. The main feature of the proposed system is the high degree of operational flexibility due to the complete PC-based software control. LFN characterization, down to bias DC currents of 1pA, in organic thin film transistors is reported to demonstrate system operation and performances.

In this paper, the authors demonstrate that a proper connection of two or more low-cost low-accuracy digital-analog converters can be used for the realization of a high-accuracy static analog memory (SAM). High-accuracy SAM is a circuit behaving as a high-accuracy sample and hold block with indefinite hold capability. The proposed topology can be applied both at the board level and at the integrated-circuit level when designing compact and low-cost devices for automated test equipment. In fact, as it will be demonstrated in this paper, high accuracy can be guaranteed by design, without the need for any calibration procedure. The proposed approach can therefore be considered as a possible and advantageous alternative to the conventional methods employed for the realization of high-accuracy multiple-output programmable voltage or current sources. A prototype of the SAM, based on the proposed approach, has been assembled and tested. As it will be shown, the obtained experimental results fully confirm the validity of the approach

Ultralow noise measurements often require the application of signal processing and correction techniques to go beyond the noise performances of front-end amplifiers. In this paper, a new method for the voltage noise measurement is proposed, which allows, at least in principle, the complete elimination of the noise introduced by the amplifiers used for the measurements. This is obtained by resorting to the conventional cross-correlation technique for the elimination of the contribution of the equivalent input voltage noise of the amplifiers and by using a new three-step-measurement procedure that exploits different amplifier-configuration measurements in order to subtract the contribution of the equivalent input current noise of the amplifiers

In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO/sub 2/. Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content.

One-transistor dynamic random access memories (DRAMs) (1T-DRAMs) are considered a promising candidate to overcome the limits of scalability of conventional one-transistor/one-capacitor DRAMs. Robust and reproducible operation has been demonstrated by experiments in MOSFET devices with a gate length (L) down to ~50 nm, which prevents their use in future technological nodes. The main factors limiting the retention time of 1T-DRAMs are the Shockley-Read-Hall recombination in the channel and the band-to-band tunneling between channel and source/drain junctions, both enhanced by the relatively high field at both junctions. In this letter, we show through statistical device simulations on a template double-gate MOSFET that, by introducing an underlap of ~16 nm between the drain (source) junction and the gate, it is possible to reduce both the electric field at the junction and the impact of process variability, achieving 1T-DRAMs with L = 10 nm with a retention time in excess of 100 ms. We also show that field plates at the source and drain contacts do not provide additional advantages and that the junctionless transistor operation as 1T-DRAM is totally undermined by the impact of random dopants.

The low-frequency noise behavior of locally strained pMOSFETs with a 7HfO/sub 2//TiN gate stack is reported. Different ways of compressive-strain engineering have been compared: a Si/sub 3/N/sub 4/ cap layer, SiGe source/drain (S/D) regions, or the combination of both. It is shown that the use of a cap layer does not degrade the 1/f noise magnitude, while an increase of this parameter is found for SiGe S/D devices. This increase is ascribed to the creation of additional traps in the high-k oxide by the SiGe S/D processing. The effect appears to be independent of the germanium content in the range studied (15%-25%). Another conclusion is that no direct correlation has been observed here between the applied stress and the noise magnitude.

In this work we propose a channel backscattering model in which increased carrier temperature at the top of the potential energy barrier in the channel is taken into account. This model represents an extension of a previous model by the same authors which highlighted the importance of considering the partially ballistic transport between the source contact and the top of the potential energy barrier in the channel. The increase of carrier temperature is precisely due to energy dissipation between the source contact and the top of the barrier caused by the high saturation current. To support our discussion, accurate 2D full band Monte Carlo device simulations with quantum correction have been performed in double gate nMOSFETs for different geometries (gate length down to 10 nm), biases and lattice temperatures. Including the effective carrier temperature is especially important to properly treat the high inversion regime, where previous backscattering models usually fail.

In this paper we critically review and compare experimental methods, based on the Lundstrom model, to extract the channel backscattering ratio in nano MOSFETs. Basically two experimental methods are currently used, the most common of them is based on the measurement of the saturation drain current at different temperatures. We show that this method is affected by very poor assumptions and that the extracted backscattering ratio strongly underestimates its actual value posing particular attention to the backscattering actually extracted in nano devices. The second method is based on the direct measurement of the inversion charge by CV characteristics and gets closer to the physics of the backscattering model. We show, through measurements in high mobility p-germanium devices, how the temperature-based method gives the same result of the CV-based method once that its approximations are removed. Moreover we show that the CV-based method uses a number of approximations which are partially inconsistent with the model. In particular we show, with the aid of 2D quantum corrected device simulations, that the value of the barrier lowering obtained through the CV-based method is totally inconsistent with the barrier lowering used to correct the inversion charge and that the extracted saturation inversion charge is underestimated.

In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate length down to 70 nm. Moreover we propose an extension of the backscattering model to the case of 2D geometries (e.g. bulk MOSFETs). We found that, in this case, the backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1D approach can be significantly different from the real 2D value.

We propose a model for partially ballistic MOSFETs and for channel backscattering that is alternative to the well known Lundstrom model and is more accurate from the point of view of the actual energy distribution of carriers. The key point is that we do not use the concept of "virtual source". Our model differs from the Lundstrom model in two assumptions: i) the reflection coefficients from the top of the energy barrier to the drain and from top of the barrier to the source are approximately equal (whereas in the Lundstrom model the latter is zero), and ii) inelastic scattering is assumed through a ratio of the average velocity of forward-going carriers to that of backward-going carriers at the top of the barrier kv > 1 (=1 in the Lundstrom model). We support our assumptions with 2D full band Monte Carlo (MC) simulations including quantum corrections in nMOSFETs. We show that our model allows to extract from the electrical characteristics a backscattering coefficient very close to that obtained from the solution of the Boltzmann transport equation, whereas the Lundstrom model overestimates backscattering by up to 40%.

In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages: (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface: (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique. (C) 2009

In this paper, a comprehensive study of hot- carrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: (1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; (2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and (3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.

In this paper, we propose a method to fully characterize noise in operational amplifiers (op-amps). The method allows the extraction not only of the spectra of the equivalent input current noise (EICN) and equivalent input voltage noise generators but also of their cross-correlation coefficients, which are routinely discarded in noise analysis of op-amps. The method is applied to extract all noise parameters of the low-noise bipolar-input op-amp OP27 and is validated through noise measurements in a test circuit. A key finding is that neglecting the cross-correlation coefficient between the two EICN generators can lead to severe errors in noise analysis.

In this paper we investigate warm electron injection in a double gate SONOS memory by means of 2D full-band Monte Carlo simulations of the Boltzmann Transport Equation (BTE). Electrons are accelerated in the channel by a drain-to-source voltage VDS smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based post-processing method as a function of the particle distribution obtained from Monte Carlo. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias and warm electron injection can be an interesting option for programming when short channel effects prohibit the application of larger drain bias.

This letter studies the impact of defects close to the gate electrode side on low-frequency 1/f noise in the drain and gate current. Defects are selectively introduced by deposition of a submonolayer of HfO2 dielectric, which induce a large Fermi-level pinning on the gate. Contrary to the common belief that defects at the Si/SiO2 interface are the dominant effect on 1/f noise, defects at the interface and fluctuations in the poly-Si charge are also important.

Strain engineering based on either a global approach using high-mobility substrates or the implementa- tion of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated.

In this paper, we report a purposely designed instrumentation and a jump detection procedure for the measurement of single-electron phenomena in solid-state nonvolatile memories based on a silicon nanocrystal floating gate metal-oxide-semiconductor field-effect transistor. The stepwise evolution of the drain current of a memory cell after a ldquowriterdquo operation is monitored by means of a purposely designed low-noise acquisition system with a bandwidth of up to 10 kHz. The advantage of the measurement system background noise and bandwidth over a traditional semiconductor parameter analyzer performance is evident in the detection and classification of single-electron events.

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO2) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.

A complete comparison of performance and reliability between polysilicon gate/SiON oxide nMOSFETs with and without SiN cap layer is presented. The uniaxial tensile strain induced by the cap layer causes an improvement in the channel current drive capability without degrading the noise performance. The gain in the transconductance, for the strained devices, was found to decrease for increasing channel lengths and for higher channel fields. Similar robustness against hot carrier stress, bias-temperature instability, and time to breakdown were found between strained and unstrained-silicon devices, confirming the advantages of strain technology