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Thermal conductivity of copper and tungsten nanowires, copper damascene structures are modeled theoretically on the basis of Boltzmann transport equation. The size-dependent thermal conductivities of the nanowires are obtained by taking into account interface scattering, grain boundary scattering, and interface roughness effect. Expressions for the thermal conductivity of thin films including the above mechanisms are extended to the case of rectangular cross-sectional nanowires. The fractal model is also used to predict the contribution of interface roughness to the thermal conductivity of nanowires. It is shown that the interface roughness is important for the nanowires with lateral dimensions down to the sub-30 nm region. Calculated thermal conductivities are in good agreement with the experimental data for copper and tungsten nanowires. Furthermore, it is found that the titanium nitride barrier layer obviously leads to further thermal conductivity reduction in the copper damascene structures. [ABSTRACT FROM AUTHOR]

Electromigration lifetime was studied on 0.23 μm wide Cu dual-damascene lines connected to underlying W lines with a TaN/Ta liner and SiN[sub x]/SiO[sub 2] insulator. The failure criteria used to study electromigration lifetime were based on the increase in test line resistance. Over 900 samples were tested to observe early electromigration Cu lifetime. Experimental results show that the lifetime distribution of samples tested using a failure criterion of 1% (3 Ω) resistance increase at the test temperature is best described by a trimodal function. However, the lifetime distribution of samples tested using a failure criterion of 50% is best described by a bimodal function. This difference in lifetime distribution is due to three types of observed deviant line resistance behaviors (plateau, fluctuating, and uphill) of certain samples which are caused by different types of void growth and a variation in liner stability. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

An in situ electromigration apparatus was used to study the kinetics of void growth in unpassivated, electropolated copper damascene lines. Voids were observed to grow by consuming grains in a stepwise fashion, either by grain thinning or by an edge displacement mechanism. Surface diffusion was found to be the primary diffusion path for void growth. In addition, grain boundaries provided a secondary path for copper diffusion in polycrystalline structures and nucleation sites for void growth in bamboo structures. Void growth rate was measured as a function of sample temperature and linewidth using a scanning electron microscope. An electromigration activation energy of 0.9±0.1 eV was determined for the copper voiding process. The effect of linewidth on void growth rate was also investigated and found to be negligible, consistent with a surface-diffusion dominated model for void growth. The in situ apparatus also made it possible to directly correlate changes in electrical resistance with physical changes taking place in the test structures. [ABSTRACT FROM AUTHOR]

An overview of process and quality control issues faced in controlling copper damascene plating is provided. The challenges for effective management of a copper damascene plating process have evolved due to early limitations and problems which were discovered, and then as more demands resulted from Chemical Mechanical Planarization issues, yield and reliability concerns, reduction in critical feature size and the shift to 300 mm wafers as well as the adoption of dielectric films with low dielectric constants. The demands have been addressed by adherence to quality control methodology, improvements in plater design and operation, advancements in plating electrolytes, and by new metrology tools and methodology. The key measurement areas outlined here are bath concentrationmeasurement and control, film properties metrology, contamination issues, and defects. Particular attention is given to the use of electrochemical and optical methods with enhanced capabilities. This includes the use of chemometrics for electroanalytical bath concentration control and optical methods for film thickness, surface roughness, and film stress/wafer curvature measurements. [ABSTRACT FROM AUTHOR]

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10 µm used for 40 nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063 µm. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40 nm or below technology. [ABSTRACT FROM AUTHOR]

The role of electrolyte additive chemistry in the incorporation of non-metallic impurities (such as C, S, and Cl) in electrodeposited Cu and its subsequent recrystallization behavior was characterized for both blanket electrodeposited Cu films and Cu plated into Damascene features. Chemistries yielding both pure and "doped" Cu were considered. For wide features (~ >1 µm), impurity levels correspond well with blanket Cu film observations, while for narrow features (~50 nm), impurity levels were elevated within the features, regardless of chemistry type. Recrystallization within Damascene features was observed to be relatively insensitive to the electrodeposited Cu purity and instead more dependent on feature size and the post-plate anneal temperature employed. The correlation of the electrodeposited Cu purity to electromigration and stress migration behavior is discussed. [ABSTRACT FROM AUTHOR]

Abstract: Electromigration (EM) of a dual damascene, test vehicle was measured using direct current (DC), alternating current (AC) followed by DC, and three rectangular-wave DC stressing conditions at 598K. In some of the experiments samples were allowed to cool to room temperature between the 598K stress cycles. We find that that only net DC time at test has a significant effect on time to fail. AC stressing for one week at 2.5MA/cm2 prior to DC stressing to EM failure had no effect on the EM performance. A similar result is obtained with various DC and thermal cycling conditions. Thermal history of the EM test samples, and in particular cooling to room temperature, has no effect on EM lifetime. All tests, regardless of thermal history and current cycling conditions, resulted in statistically similar times to fail and distributions of those times. We conclude that the standard test methodologies, using accelerated DC stress conditions at elevated temperatures, are adequate. Since only the net DC stress time had any measurable effect on EM lifetime, the use of accelerated testing provides a good predictor for lifetime expectations under operating conditions. We also conclude that neither low current density AC stressing nor DC cycling, and associated changes to grain structure that may result, provide any measurable benefit to EM lifetime. [Copyright &y& Elsevier]

A direct-polishing process was applied to the ultralow-k dielectric without a dielectric protective layer to reduce the effective dielectric constant in damascene interconnects. The direct-polishing process on organic non-porous ultralow-k dielectric, fluorocarbon (k = 2.2), was demonstrated and an optimum direct-polishing process condition was investigated. Mechanically enhanced chemical reaction on the fluorocarbon degraded the electrical properties by changing the structure of the fluorocarbon. Higher down-pressure, one of the most important factors in mechanical effects, resulted in both higher leakage current and a variance of the structure of th fluorocarbon. A surface nitrogen plasma treatment of fluorocarbon before polishing to form an effective protective layer was applied to avoid the degradation of electrical characteristics during the direct-polish, and this result revealed that the surface nitrogen plasma treatment of fluorocarbon is a practical technique for a direct-polishing process in advanced Cu interconnects. [ABSTRACT FROM AUTHOR]

Extreme bottom-up copper superfihling of through-silicon-vias (TSV) is demonstrated using a CuSO4-H2SO4 electroplating bath containing chloride and a polyether suppressor. Via filling occurs almost exclusively by deposition on the bottom via surface. The differential between the incoming fluxes of hydrated metal cations and larger suppressor molecules is accentuated by the recessed via geometry and accounts for preferential metal deposition initiating and growing from the bottom surface. The bottom-up growth front eventually propagates beyond the via opening and a substantial overburden develops. Feature filling is enhanced in electrolytes with a high [Cu2+/[H3O+] ratio where global coupling by migration helps sustain the flux of Cu2+ to actively growing surface sections. Bottom-up superfilling relies on positive feedback whereby inhibition provided by adsorption of the polyether additive on the chloride saturated surface is disrupted by the metal deposition reaction. Release of the water of hydration that accompanies reduction of the Cu2+ aquo complex contributes to the sustained disruption of suppressor activity at the growth front. The correlation between TSV superfilhing and additive-generated voltammetric hysteresis on planar substrates, which also involves a negative- differential-resistance (S-NDR) coupled with the electrolyte resistance, provides a general framework for understanding and guiding optimization of the bottom-up growth mode in recessed surface features. [ABSTRACT FROM AUTHOR]

Abstract: The 300mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5–6. [Copyright &y& Elsevier]

Abstract: This study explored a simplified micro-scale Cu damascene process based on UV-assisted thermal imprinting of SU-8 to investigate its process merits and potential defects that may occur during and after processing. For comparative study, arbitrary electrical circuits composed of Cu wiring structures with widths ranging from 10μm to 1mm were developed in SU-8/Si patterned by UV-assisted thermal imprinting and in oxidized Si samples prepared by reactive ion etching (RIE) followed by thermal oxidation. The imprint-based approach could lower process cycles, equipment cost, and etching gas use, whereas it induced a higher residual stress and more delamination defects. The process studied here are expected to be applied to fabricate micro-scale Cu structures, such as coils, antennas, electrical circuits, and wiring and connecting lines if further enhancements of the adhesion ability between layers and the design of pattern fields in a mold are accomplished. [Copyright &y& Elsevier]

Temperature distributions and von Mises strains produced by cyclic Joule heating of damascene copper interconnect structures of varying geometries were calculated by finite element analysis. Constraining the top surface of the lines with rigid dielectric increased the temperature range required to produce a given strain range, relative to unconstrained lines. Much narrower lines required much higher temperatures to reach this same range of strain. Electrical tests to failure of actual structures were conducted. Scanning electron microscope images of unconstrained damascene copper lines after testing showed significant topographic features that have been associated in previous reports with mechanical fatigue. None of the constrained lines -- including those cycled at ranges of total strain similar to those of the unconstrained lines -- exhibited these features, but they did have large voids. Present and previously reported observations suggest that both cyclic plastic deformation and void formation can contribute to damage and failure of small-scale structures subjected to cyclic Joule heating, and that mechanical constraint has a strong effect on the operation of these mechanisms. [ABSTRACT FROM AUTHOR]

As device dimensions shrink to the sub-65 nm regime, a greater demand is placed upon the barrier polishing process. Therefore the ability to modulate the barrier chemical mechanical planarization performance window by process and formulation synergy can provide tunability at advanced technology nodes to meet stringent electrical, topography, and defect requirements. This study introduces one approach in achieving the synergy between barrier polishing slurry and the development of a robust process. The system investigated has demonstrated desirable Rs uniformity control and greater margin for polishing. Extensive Mx layer testing (more than 10 wafer lots) has consistently shown better within-wafer Rs (resistance) spread compared to process of record, with improvement above 30% for all layers. The slurry also shows a more gradual Rs fluctuation over a 20 s polish time range. A marathon run has also shown consistent polishing rate performance over the pad life with comparable defect density' and characteristics. [ABSTRACT FROM AUTHOR]

Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLK™) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Ω at 0.28 μm⊘ with keeping large tolerance of misalignment up to 0.1 μm. [ABSTRACT FROM AUTHOR]

There is considerable interest in the use of ruthenium as an ultrathin trench liner in damascene copper plating used to fabricate on-chip interconnects. The problem is that when freshly deposited ruthenium films are exposed to air, their surfaces tend to undergo spontaneous oxidation, and such deposits (as demonstrated here) are reluctant to undergo reduction. Copper deposition in an acid plating bath occurs readily on the oxidized ruthenium, but the presence of oxide is known to have a detrimental effect both on the copper superfilling process and copper adhesion at the Ru/Cu interface. [ABSTRACT FROM AUTHOR]

Abstract: The mechanism of copper (Cu) voids formation from electro-chemical plating (ECP) followed by Cu chemical mechanical polishing (CMP) are studied in Cu dual-damascene interconnection. The formation of Cu voids at metal lines is the main problem that causes not only the failure of via-induced metal-island corrosion but also yield loss. The galvanic theory and Cu lifting mechanism are proposed to explain the dependence of Cu-void performance on the Cu grain size and the benzotriazole (BTA, C6H5N3) flow rates. In the integration process of Cu interconnects, it is found that the smaller Cu grain size in ECP conditions and less BTA flow rate in CMP processes cannot only reduce the number of Cu voids but also improve the wafer yield. [Copyright &y& Elsevier]

Abstract: This paper discusses the first evidence about the low pattern density causing abnormally high VIA resistance, which is at least more than two times the normal level. The low pattern density also induces the exposure-like shape formed in VIA bottom, where high concentration of sulfur element is detected in the copper film after electric- and thermal-torture testing. These effects, due to the low pattern density, are significantly important for nano-scale feature filling and the quality of VIA superfilling. This paper also proposes a mechanism to explain the observed results by inferring from the local resistance and chemical polarity difference with different numbers of VIA serially connected. The experiment with high accelerator concentration also supports the proposed mechanism by locating abnormal voids in the region with low VIA pattern density. [Copyright &y& Elsevier]

A Cu electroplating solution applicable to porous silica ultralow-k films (k = 2.1) without pore sealing was investigated. A suppressor which causes permeation of Cu electroplating solution was replaced by polyethylene glycol (PEG) with specific molecular weight (Mw). Transmission electron microscopy observation revealed that permeation by the Cu solution into the porous silica layer can be suppressed by decreasing the molecular weight of the PEG suppressor in the electroplating solution. A Cu electroplating solution using PEG with Mw = 600 was examined for the low-k porous silica/Cu single-damascene integration process of 300 mm wafer. The filling characteristics in trenches and the uniformity of Cu film thickness were investigated. Interline leakage current on low-k/Cu damascene interconnects was successfully reduced by six orders of magnitude using this Cu plating solution compared with the conventional solution. [ABSTRACT FROM AUTHOR]

Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability. [ABSTRACT FROM AUTHOR]

Copper pits formed after copper chemical mechanical polishing (CMP) are the critical defects in the copper dual damascene process because the imperfect copper surface can cause the interconnection to be missed or broken. There are many parameters contributing a flat copper surface, such as the polishing down-force, slurry pH value, and galvanic effects between barrier and copper materials. One of the important factors influencing the pit formation is the friction force. The kinetics of the polishing friction can be studied to understand the mechanism of the pit-defect formation. A mechanism is proposed and can be explained by two characteristics of pit-defect formation during the polishing, i.e., the location of the edges between the metal line and wafer and the magnitude of the friction torque inducing the defect. Furthermore, three different polishing platforms are used to demon- strate this kinetic approach toward understanding the role of the threshold of the friction force in the pit-defect immunization. With this understanding, the pit formation can be reduced significantly. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, new porous spin-on dielectric (HL02™, trademark of the LG Ltd.) was studied. The characterizations, such as thermal stability, chemical structure, dielectric constant (k) and mechanical properties (hardness and modulus), of methylsilsesquioxane (MSQ)-based dielectrics were evaluated. An optimized material (k =2.25), characterized by a hardness and a modulus of 1.0 GPa and 6.5 GPa each in association with a porosity of 30% and a mean pore radius of 2.2 nm, was successfully integrated in damascene process with 10 levels of Cu/low-k film for 65 nm technology and beyond. Good electrical results were obtained in metal line resistance and leakage current. [Copyright &y& Elsevier]

Abstract: The copper damascene process is one of the most promising technologies for fabricating Cu wirings for electronic devices such as LSIs. In this research, the fabrication of damascene Cu wirings was conducted using solid acidic catalyst. When a Cu-plated wafer, whose oxide is a basic oxide is dipped into a mixture of oxidizing solution and acidic solution, surface atoms are ionized and etched off into the solution. However, because conventional nonelectrolytic etching does not have a reference surface, it is difficult to utilize for planarization. Therefore, a new nonelectrolytic machining method using a cation-exchange fabric instead of an acidic solution was developed. To be more precise, the planarization of a Cu-plated wafer was carried out by rubbing with the cation-exchange fabric in ozone water. Basically, this method exploits chemical reactions so that the physical properties of the workpiece surface are not deteriorated. Furthermore, this method uses no chemicals except for ozone water, which easily dissociates into water and oxygen molecules; thus, this method is a low-cost, environmentally friendly process. In this paper, as a preliminary experiment, the nonelectrolytic etching of a Cu sample using solutions of O3 and CO2 was carried out to inspect the dependence of the etching rate on [O3] and [H+]. The results indicate that the etching rate increased as [O3] and [H+] increased. When [H+] was high relative to [O3], a smooth etch-pit-free surface was achieved. Next, nonelectrolytic etching using a cation-exchange fabric was carried out, and properties similar to those in the case of etching using solutions were obtained. Finally, damascene Cu wirings were fabricated using ozone water and a cation-exchange catalyst. [Copyright &y& Elsevier]

Abstract: In this study the degradation phenomena in dual-damascene copper (DD-Cu) metallizations will be investigated due to high current densities and substrate temperatures by finite element modeling. The static and dynamic simulations and calculations will show the suitability of the method in comparison to experimental results from the literature. Different geometry variations, like overlap and via height as well as a variation of the stress free temperature of the metallization will be carried out. It will be found, that if the maximum temperature in the metallization is near the stress free temperature the electromigration is dominant. If the temperatures differ from the stress free level stress migration will be predominant. Out of this it will be found that the knowledge of the stress free temperature in the metallization is very important for a sufficient migration determination. [Copyright &y& Elsevier]

Abstract: Ta (N)/Ta bi-layer is a commonly used barrier in damascene copper interconnects for 90nm and 65nm technology nodes. A new barrier integration scheme so-called punch-through is currently used for 65nm node. The main feature of the new deposition scheme is to introduce an etch-back step between the Ta (N) layer deposition and the Ta layer deposition. This intermediate etch step cleans up the bottom of via and also partially etch the underlying copper line with a depth of few nanometers. This step changes dramatically the bottom of via shape leading to via anchoring into the underlying copper line. In this paper we compare punch-through versus no punch-through approach. We show that the punch-through leads to a lower via resistance and to a tighter via resistance distribution, while keeping line resistance similar. We show that via anchoring into the underlying copper line coupled with a better tantalum step coverage dramatically reduces stress migration effect and also improves electro-migration performances at 65nm technology node. [Copyright &y& Elsevier]

Abstract: New metal insulator metal (MIM) capacitors in parallel configuration have been implemented between upper copper interconnect levels using a damascene architecture. High frequency characterization has been performed on these devices in order to study their electrical performances. A new extraction method has been developed to obtain a lumped electrical equivalent model of MIM capacitors that is frequency dependant. Many designs have been used. Thanks to the high frequency characterization, a quality factor Q has been established. [Copyright &y& Elsevier]

In recent years, Cu/low-k damascene (buried interconnects) processing, which uses Cu interconnects with low-dielectric-constant (low-k) films, has emerged as a way to satisfy the requirements for making devices ultrasmall, high-speed, and usable in ultralarge-scale integration (ultra-LSI). However, the use of Cu in combination with new materials to make the low-k films has led to difficulties in developing a process for cleaning after post-chemical-mechanical planarization (CMP). One of these problems is the presence of hydrophobic residuals on the low-k films, for whose removal many slurries (polishing agents) and cleaning fluids have been developed. In our work, we have combined these slurries and cleaning fluids, and investigated the effectiveness of the combinations in cleaning low-k films, allowing us to develop an optimum process. We determined the defect counts for TEOS, Cu, and two kinds of low-k films, and measured the level of contamination of the low-k film contaminant by spots of Cu, from which we identified cleaning fluid that performed best. We also confirmed that the performance of the cleaning fluids was different depending on the choice of slurry. We then used our optimum process to formulate a fabrication scheme for devices with the Cu/low-k structure, fabricated a set of devices, and investigated their electrical characteristics. Because of the significant reduction we observed in leakage currents between circuit lines to below 10-9 to 10-10A/m, we argue that our process can be used to fabricate ultra-LSI device ensembles under real conditions. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(11): 19–30, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20187 [ABSTRACT FROM AUTHOR]

Abstract: The influence of M1 (lower level Cu) line width on stress-induced voiding (SIV) behavior of copper dual damascene interconnects was investigated by stress migration test at 200 °C and finite element analysis (FEA). M1 line width under study ranged from 200 nm to 1000 nm, whereas the M2 line width was fixed to be 3 μm. The normalized change in resistance indicated that the via-line structures with larger M1 line width were more susceptible to SIV. Failure analysis utilizing focus ion beam (FIB) showed that voids were formed in the via bottom region for samples with M1 line width less than 280 nm. However, voids were found at the Si3N4/M1 Cu interface near the via bottom if M1 line width is larger than 280 nm. To further understand the underlying physics of SIV, three dimensional finite element models were built to simulate the hydrostatic stress distribution in the via-line structures. It was found that the stress gradient in the length direction, gradσ l, was not sensitive to M1 line width, however, the stress gradient in the line width direction, gradσ w, was found to increase with M1 line widths. It is thus proposed that in addition to the active diffusion volume, it is the gradσ w that further favors the migration of voids (or vacancies) along the Si3N4/M1 Cu interface and subsequent accumulation of the voids near the via bottom leading to a much higher resistance change at larger M1 widths. [Copyright &y& Elsevier]

Copper chemical-mechanical polishing (CMP) dishing concerns semiconductor manufacturing yield in contemporary back-end-of-the-line process. In this work, we first propose and validate a dishing model through first-principle analysis and carefully designed experimentation. This model utilizes the novel concept of dishing radius, a metric that assumes cylindrically shaped post-CMP copper surface and directly captures the extent of metal dishing for a CMP process. Additionally, a dishing-model-based method for extracting the parameterized two-dimensional post-CMP metal profile is developed for damascene structures. The case study utilizing this method shows that the extracted parameters are in good agreement with those from cross-sectional scanning electron microscopy and surface profilers, which confirmed that dishing radius is linewidth-independent for typical metal lines. This method is particularly useful in determining dishing artifacts, which are modeled using the dishing radius concept. The approach is nondestructive, precise, and efficient. [ABSTRACT FROM AUTHOR]

Microstructure in the damascene interconnects evolves with the overburden layer, an excessive metal layer over trenches. We present the results of three-dimensional simulation, which show the effects of overburden thickness on microstructure evolution in a trench. When the thickness of the overburden is less than half of the trench depth, for a trench with the aspect ratio of unity, the microstructure in the trench tends to evolve into a bamboo structure. This effect is discussed in terms of grain sizes in the trench and those in the over-burden. The thinner overburden layer would have smaller grains, of which growth is limited by its thickness. Such small-sized grains in the overburden are not likely to grow into the trench, which hardly make grain boundaries in the trench. Meanwhile, the grains from the trench are able to continue growth inside the trench, resulting in a bamboo structure. Overburden thickness affects the reliability and the electrical performance of the damascene copper interconnects. Optimization of overburden thickness is required to minimize these effects. [ABSTRACT FROM AUTHOR]

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits. [ABSTRACT FROM AUTHOR]

The article focuses on superfilling and the curvature enhanced accelerator coverage mechanism. In the early years of copper Damascene technology an understanding of the superfilling process lagged behind its implementation due to a combination of factors. The first generation of electrolytes contained numerous components and general knowledge of both the chemistry and processing conditions was significantly constrained by proprietary concerns. Subsequently, a curvature enhanced accelerator coverage mechanism was developed to quantitatively describe superconformal film growth that is responsible for bottom-up superfilling of sub-micrometer features in Damascene processing.

130 nm technology uses Cu/low k materials integration for the back-end-of-line (BEOL) process. The motivation of this work is to improve the electrical performance of Cu/CVD low k Coral™ dual damascene metallization through optimization of the Cu cap etch wet clean. Two types of wet clean chemicals (amine- and fluoride-based mixtures) were selected for the study, using either a conventional batch spray process or single wafer cleaning system. The single wafer cleaning system provides an efficient means of removing polymeric residues (especially the via sidewall and bottom) with the application of mega-sonic acoustic agitation. On the whole, we achieved excellent physical, electrical and burn-in reliability results for the interconnects processed from single wafer cleaning system with ST250™ at post Cu cap etch. The fabricated wafers achieved electrical yields >95% for the dense via chains before and after 500 h burn-in reliability tests. [Copyright &y& Elsevier]

Design rules were developed for the layout of copper Damascene interconnect layers to minimize the within-die resistance variation. The impact of various layout configurations on the metal sheet resistance was characterized using two different test vehicles. An increase in resistance was observed on wide lines and high pattern densities due to dishing and dielectric erosion, respectively. In addition to the above, narrow lines were severely impacted by the presence of wide adjacent features in close proximity. The pattern interaction distance for copper chemical-mechanical planarization (CMP) was calculated by analyzing the resistance variation at the edge of a density or width transition. In this work, the interaction distance was found to be on the order of 25μm (as opposed to a few millimeters for oxide CMP). From these results, a window of about 50 to 60 μm was found to be necessary to obtain the effective pattern density for copper CMP. The resistance of the upper metal level was a strong function of the under lying layer density. Hence, multilevel pattern dependencies have to be considered when modeling and predicting the line resistance on a real design. However, unlike oxide polish, pattern density alone is insufficient to predict the final copper thickness. Width-dependent spacing rules are necessary to prevent clustering of features (narrow lines very close to wide buses) and avoid regions of very low density. [ABSTRACT FROM AUTHOR]

Presents a review of planarization methods and techniques that can reach topography levels in the semiconductor industry. Obstacles for the copper interconnect process; Contribution of improving the planarity at the copper deposition step and reducing the amount of dishing at the chemical mechanical planarization step in achieving topography reduction; Importance of planar copper films to overcome th obstacles facing integration of copper damascene technology.

Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16 µm. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-µm technology node. [ABSTRACT FROM AUTHOR]

Abstract: The work described in the present paper is about electromigration induced void formation mechanisms in Cu lines. An unusual behavior observed on the electrical resistance of some samples suggests the presence of more than one void in the stressed lines. The scope of this paper is about the origin of these voids; mainly how they appear in the lines and how they affect the Cu lines reliability. [Copyright &y& Elsevier]

The article reports on the challenges of 65nm and 45nm Cu/low-k interconnect integration. One of the main challenges of it is the development of processes to accommodate low-k dielectrics with k = 2.5-3.0. Key issues include dual-damascene patterning, line resistance, low-k integrity, chemical mechanical planarization compatibility, and copper defectivity. Selecting the right dual-damascene process scheme is critical because it needs to work over a range of technology nodes, and with a variety of low-k dielectric stacks.

Focuses on the convergence of chemical mechanical planarization and low-k dielectrics for copper dual-damascene. Cause of delamination; Examination of the removal of copper from the wafer through control of wafer rotation, recirculating electrolyte flow, and voltage and current; Accomplishment of the stress-free polishing process development work.

Electromigration of Cu and diffusion of Co in Cu damascene bamboo-like grain structure lines capped with CoWP have been studied for sample temperatures between 350 and 425 °C. Void growth from the Cu line/W via interface was observed. Bulk-like activation energy for electromigration of 2.4±0.2 eV was obtained for these samples suggesting that electromigration damage is greatly diminished for these on-chip Cu interconnections. The solubility and diffusivity of Co in Cu was determined from line resistance measurements of thermally annealed Cu lines which were affected by Co diffusion into the Cu line. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Microscopic observation and imaging of Cu damascene interconnect grains were carried out using the x-ray microbeam of the BL-16XU at SPring-8. The x-ray focusing system of the beamline consists of a bent-cylindrical prefocusing mirror and elliptical mirrors with a Kirkpatric–Baez configuration. Diffraction spots from the microscopic area irradiated by the intense x-ray microbeam (7×6 μm full width at half maximum) at the boundary between the metal line and the dielectric were observed. The diffraction spots observed show that Cu(111) grains grow normally on the sidewall and Cu(200) grain orientation distribution is quite broad, suggesting that crystallographic texture near the trench is quite disordered. Two-dimensional images of grains with a specific orientation angle were also obtained. Grains as large as about 10 μm caused by self-annealing were observed. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]