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Ionizing radiation effects spectroscopy (IRES) for the analysis of total-ionizing dose (TID) degradation in radio frequency (RF) circuits is presented. IRES is used to image the change in the operating parameters with respect to TID and for classification of the circuit’s state based on image features. Measured data from two voltage-controlled oscillators (VCOs) and two phase-locked loops (PLLs) exposed to TID are used to demonstrate the utility of IRES for radiation effects analysis. The VCO and PLL circuits were designed in a 130-nm bulk CMOS technology. The circuits were irradiated up to 300 krad(SiO2) using an Aracor X-ray source, and IRES images were developed at various TID levels based on the instantaneous frequency of the output waveforms. The IRES technique is based upon RF-distinct native attribute fingerprinting for specific emitter identification using RF waveforms in communication systems. The technique employs statistical time–frequency analyses of various signal features. The resulting statistical measures are utilized to identify the operational state of the circuit (i.e., the TID level and bias voltage) using machine learning (ML) classification. While minor increases in operating frequency were measured with dose, the technique resulted in up to 100% prediction accuracy in the identification of the operational state following an ML training set of at least 50 measured samples. Moreover, the IRES technique enhances standard measurements by capturing global parametric shifts as well as transient variation. The technique, which exploits the subtle characteristics inherent in the waveforms, shows promise in radiation dosimetry applications as well as in-situ monitoring of device and circuit operational health. [ABSTRACT FROM AUTHOR]

Novel design techniques for efficient testability are developed and have been implemented in a 14-/16-nm bulk FinFET node technology characterization vehicle. The result of this paper was the measurement of over 300 000 SETs across 12 combinational logic variants and 415 000 SEUs in three D-flip-flop designs over a large test matrix of heavy-ion linear energy transfer, angle of incidence, and supply voltage in only 319 test runs with a total test time of 108 h. A similar-sized data set with equivalent technology coverage, using the traditional serial testing approach as used in previous work, would typically require thousands of test runs and a significant number of additional hours of testing. The methodologies developed in this paper are technology agnostic and have provided the capability to efficiently characterize the radiation-induced response of the 14-/16-nm FinFET technology generation and yielded insights for assessing the feasibility for incorporation in systems requiring radiation resiliency. [ABSTRACT FROM PUBLISHER]

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region. [ABSTRACT FROM PUBLISHER]

Integrated circuits fabricated at advanced technology nodes are expected to operate in gigahertz range of frequencies. At these frequencies, single-event transient (SET)-induced errors result in significant increases in single-event (SE) cross section for flip-flop (FF) designs. For FinFET transistors, the physical structure has changed significantly from planar structure. These changes have resulted in significantly less collected charge than that for planar technologies for the same ion strike, leading to shorter SET pulse generation. These results have necessitated the evaluation of SE cross section for FF designs as a function of frequency for accurate SE predictive capability. Circuit-level simulations and heavy-ion experiments were carried out to investigate frequency dependence of SE cross section for a hardened dual-interlocked cell-based FF design with different spacing options in a 16-nm bulk FinFET technology. [ABSTRACT FROM PUBLISHER]

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification. [ABSTRACT FROM PUBLISHER]

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints. [ABSTRACT FROM PUBLISHER]

The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition. Single-event tolerant design guidelines for the digital loop filter are proposed and validated through FPGA-based fault injection experiments. [ABSTRACT FROM PUBLISHER]

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30\times on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage. [ABSTRACT FROM PUBLISHER]

For advanced technology nodes, the close proximity of semiconductor regions results in multiple regions collecting charge after an ion strike. This is especially true for static random access memory (SRAM) integrated circuits (ICs) where transistors are placed closer to each other compared to application-specific ICs (ASICs). As a result, SRAM ICs are highly vulnerable to multi-cell upsets (MCU). In this work, heavy-ion irradiations of bulk 28-nm planar and 16-nm FinFET SRAM ICs are investigated to show that small cell size for 16-nm node results in dominance of MCUs over single-cell upsets. Three-dimensional TCAD simulations showing the spread of well-potential perturbation as a function of particle LET support the experimental data. The size of the MCU cluster is also presented to determine the design parameters for error correcting codes (ECC) and interleaving for SRAM designs to meet performance requirements. [ABSTRACT FROM PUBLISHER]

With the emphasis on low-power design, achieving soft error reliability in combinational logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate combinational logic soft errors. This work shows that for certain circuits, reduction in both power and combinational logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits. [ABSTRACT FROM PUBLISHER]

Single-event transient (SET) induced harmonic errors have been observed in digitally controlled ring oscillators (DCRO). Accumulated phase error is used to characterize harmonic errors in ring oscillator circuits. An analytical model for determining minimum and maximum SET transient duration capable of generating a harmonic is described. Simulation and TPA laser experimental results on a 40-nm DCRO are shown to confirm the assertion of the harmonic vulnerability window with respect to SET pulsewidth. Further more, fault injection experimental results on three RO designs built with discrete commercial off-the-shelf components are included to demonstrate the relationship between harmonic response and SET pulsewidth. [ABSTRACT FROM PUBLISHER]

The impacts of total ionizing dose (TID), temperature and RF stress on the DC and RF performance of a commercial 32 nm RF silicon-on-insulator CMOS technology are presented. Temperature dependence is the overwhelmingly dominant single factor affecting the DC and RF performance, with the combined effects of elevated temperature and TID showing the most pronounced degradation. The most significant effect due to TID is an increase in off-state leakage current. Key DC and RF parameters of this 32 nm RF process degrade less than those of an otherwise similar 45 nm RF SOI CMOS process. The implications of the combined TID and temperature response are discussed for low-power RF design. [ABSTRACT FROM PUBLISHER]

Accurate estimation of single event upset rates for complex combinational logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS combinational logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30–60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify logic error rate calculations. [ABSTRACT FROM AUTHOR]

In this paper, the alpha-particle induced soft error rate of two flip-flops are investigated as a function of operating frequency between 80 MHz and 1.2 GHz. The two flip-flops—an unhardened D flip-flop and a hardened pseudo-DICE flip-flop were designed in a TSMC 40 nm bulk CMOS technology. The error rates of both flip-flops increase with frequency. Analyses show that an internal single-event transient based upset mechanism is responsible for the frequency dependence of the error rates. [ABSTRACT FROM AUTHOR]

A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally. Differential charge cancellation (DCC) layout leverages the inherent common-mode rejection of differential circuits to mitigate voltage transients induced by ion strikes. A simple layout variation transforms normally single-ended error signals into common-mode signals that are mitigated by the differential signal path. This layout change maintains the matching achieved via a standard common-centroid layout but incurs negligible area penalty. [ABSTRACT FROM AUTHOR]

High-speed communication systems typically employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Current-mode logic is the industry standard for high-speed CMOS circuit design due to the inherent speed of current steering. However, current-mode output voltages are not rail-to-rail and therefore require a conversion to a full-swing signal for downstream CMOS logic. This interface between current-mode and CMOS logic is found to be vulnerable to single-event effects. A radiation-hardened-by-design solution is proposed for such interfaces. [ABSTRACT FROM AUTHOR]

Heavy-ion broadbeam results from a 90 nm process are presented for five inverter chains with varying n-well contact schemes. Results show that inverters with the smallest percentage of n-well contact area within an n-well produced the longest and most frequent single-event transients (SETs). As the percentage of n-well area contacted increases above 2%, the pulse width and number of SETs levels-off. A result indicating an optimized percentage of n-well area contacted can be calculated that minimizes the pulse width and number of SETs in a digital circuit. [ABSTRACT FROM PUBLISHER]

Process variations and charge sharing impact the single-event circuit response. This paper correlates parameter shift impact on the single-event upset (SEU) probability of flip-flop designs in advanced CMOS processes under the influence of charge sharing. [ABSTRACT FROM PUBLISHER]

In this paper, the radiation response of a single-event tolerant flip-flop design named the Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the critical charge of the sensitive nodes to be greater than that of DICE flip-flop, 2) the number of sensitive nodes and the sensitive area to be fewer than that of DICE flip-flop. A test-chip designed and fabricated at the 40-nm bulk CMOS technology node consisting of Quatro, DICE, and standard D- flip-flops was used for heavy-ions, neutrons, and alpha particles exposures. The experimental results demonstrate superior performance of the Quatro flip-flop design over conventional DICE and D-flip-flop designs. [ABSTRACT FROM PUBLISHER]

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm^2/mg. [ABSTRACT FROM PUBLISHER]

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits. [ABSTRACT FROM PUBLISHER]

Layout techniques that exploit charge-sharing phenomena for analog single-event transient (ASET) mitigation in fully-differential analog/mixed-signal (A/MS) designs are experimentally explored in a 65 nm CMOS process. Benefits of the proposed RHBD layout techniques are illustrated through circuit simulations. Preliminary RHBD layout guidelines are discussed. [ABSTRACT FROM AUTHOR]

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty. [ABSTRACT FROM AUTHOR]

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design. [ABSTRACT FROM AUTHOR]

The analysis and measurement of a radiation hardened by design 3.125 Gbps SerDes transmitter driver fabricated in commercial 90 nm CMOS is presented. The transmit driver is implemented in thick oxide 2.5 V devices. Testing and simulation of laser-induced single-event transients of a fabricated driver section are discussed. A highly-flexible data collection technique that allows post-processing of data for different error types and thresholds within a single data set is presented. This effort represents the first single-event effects measurement and analysis on a highly-scaled analoglRF CMOS circuit element operating at GHz frequencies. Sensitive nodes are identified through experiment and simulation. [ABSTRACT FROM AUTHOR]

Charge-collection circuits were designed and fabricated in a 90 nm bulk CMOS process to examine the effects of charge sharing in sub-100 nm bulk CMOS processes. Laser interrogation of the charge-collection circuits provide the first direct verification of sub-100 am charge sharing effects and show the nodal spacing dependence of charge sharing. 3-D TCAD simulations corroborate the laser data and also show the use of guarddiodes as an effective charge sharing mitigation technique. [ABSTRACT FROM AUTHOR]

Single event latchup (SEL) in a 65 nm CMOS SRAM technology due to heavy ions is observed and device sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. Experimental results show the importance of testing at multiple lateral beam orientations to properly characterize device sensitivity. [ABSTRACT FROM AUTHOR]

Scaling of complementary metal oxide semiconductor (CMOS) technologies to the sub-100 nm dimension regime increase the sensitivity to pervasive terrestrial radiation. Diminishing levels of charge associated with information in electronic circuits, interactions of multiple transistors due to tight packing densities, and high circuit clock speeds make single event effects (SEE) a reliability consideration for advanced electronics. The trend to adapt and apply commercial IC processes for space and defense applications has provided a catalyst to the development of infrastructure for analysis and mitigation that can be leveraged for advanced commercial electronic devices. In particular, modeling and simulation, leveraging the dramatic reduction in computing cost and increase in computing power, can be used to analyze the response of electronics to radiation, to develop and evaluate mitigation approaches, and to calculate the frequency of problematic events for target applications and environments. [ABSTRACT FROM AUTHOR]

Single event charge collection mechanisms in 90 nm triple-well NMOS devices are explained and compared with those of dual-well devices. The primary factors affecting the single event pulse width in triple-well NMOSFETs are the separation of deposited charge due to the n-well, potential rise in the p-well followed by the injection of electrons into the p-well by the source, and removal of holes by the p-well contact. Design parameters of p-wells, such as contact area, doping depth and placement, are varied to reduce single event pulse widths. Pulse width decreases as the area of the p-well contacts increases, the p-well contacts become deeper, and the p-well contacts are placed more frequently. Increasing the p-well-n-well junction depth also causes the full width half rail (FWHR) pulse width to decrease. [ABSTRACT FROM PUBLISHER]

The minimum laser energy required to cause sustained harmonic oscillations in a 201-stage ring oscillator varies little with increasing power supply voltage when operating in the subthreshold region. These small changes in threshold laser energy in the subthreshold region suggest that the cross-section curves as a function of power supply voltage remain relatively constant. Simulations show that the minimum pulsewidth required to generate higher-order oscillations decreases as operating voltage increases. Single-event transients are wider when circuits are operating in the subthreshold region than when operating at the nominal power supply voltages. Narrower single-event transients result for strikes on PMOS transistors as compared to those for strikes on NMOS devices in the subthreshold region; the opposite is observed when circuits are operating at the nominal power supply voltages. [ABSTRACT FROM PUBLISHER]

SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty. [ABSTRACT FROM PUBLISHER]

Most pulse width characterization circuits measure single-event transients (SETs) using a target circuit consisting of long inverter chains or temporal latches exposed to heavy-ions over extended periods of time. For these approaches, circuit-level effects eliminate shorter pulses due to prolonged heavy-ion exposure providing the worst case estimate of measurable transients. Simulation results in the IBM 180 nm and 90 nm technologies corroborate this effect and discuss the resulting factors affecting single event (SE) error cross-sections. Experimental evaluation of such a SET pulse width characterization circuit under heavy-ion exposure showed reduced number of events measured due to total dose effects as expected. Additional experimental and simulation results show that the length of the propagation chains in the target circuit (for capturing SETs), the exposed flux and time (total dose) affect the resulting number of SEs measured. [ABSTRACT FROM PUBLISHER]

A radiation-hardened-by-design phase-locked loop (PLL)—designed and fabricated in 130 nm CMOS—is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs by more than two orders of magnitude as measured by the number of erroneous PLL clock pulses following a single-event. Additionally, SEU mapping indicates a 99% reduction in the vulnerable area of the radiation-hardened-by-design (RHBD) charge pump over a conventional design. Furthermore, the TPA experiments highlight the importance of the voltage-controlled oscillator in the overall SET response of the PLL implementing the RHBD charge pump. [ABSTRACT FROM AUTHOR]

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping. [ABSTRACT FROM AUTHOR]

Random Dopant Fluctuation (RDF) induced threshold voltage (Vt) variations affect two critical parameters used as a measure of Single Event (SE) Hardness (i) Single Event Transient (SET) pulse widths and (ii) Critical Charge (Qcrit). This causes an increase in the spread of SET pulse widths in sequential logic circuits and in the Qcrit required for Single Event Upsets (SEUs) in Static Random Access Memory Cells (SRAMs). Monte Carlo simulations show this can affect the hardness characterization in a commercial 90 nm process and a generic 65 nm technology. This necessitates statistical design approaches for validating conventional hardening schemes, to assure a required level of radiation tolerance in these deep submicron technologies. [ABSTRACT FROM AUTHOR]

In deep sub-micron technologies, scaling and closely packed interconnects magnify crosstalk effects causing a Single Event Transient (SET) pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This paper analyses factors affecting the crosstalk pulse due to an Single Event Upset (SEU) in digital logic circuits for advanced technologies. Simulation results obtained substantiate that the effects of Single Event (SE) crosstalk increase as devices scale down, as the amount of Charge deposited to cause an upset increases, and as the interconnect length increases. [ABSTRACT FROM AUTHOR]

We analyze single-event transient (SET) effects in a high-speed voltage-controlled oscillator (VCO) design that is applicable to mixed-signal RF operations. Our study shows that the sensitivity of this type of circuit topologies exhibits a strong correlation to: the minimum feature size of the technology in use, the range of oscillating frequencies that the circuit is designed to achieve and the frequency at which the VCO is operating. We also determine that current-starved VCOs have an optimal functional range for improved radiation tolerance, located at the upper segment of their voltage-to-frequency transfer characteristic, where exposition to low LET ions become of no consequence on the operation of the circuit. More importantly, we show that derating the frequency of such VCO designed in a state-of-the-art technology does not compensate for the increased radiation vulnerability at that node. If not properly accounted for, the performance overhead that the newer technology provides is shown to severely penalize the radiation hardness of the circuit. [ABSTRACT FROM AUTHOR]