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3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system. [ABSTRACT FROM AUTHOR]

We propose and demonstrate an efficient grating coupler for integrated SiGe photonic devices. A bottom metal layer is adopted to enhance the coupling efficiency on the wafer backside. A low coupling loss of −1.34 dB and −0.79 dB can be theoretically obtained with optimal parameters for uniform and apodized grating couplers, respectively. The fabrication process is CMOS compatible without need of wafer bonding. The influence of fabrication errors on the coupling efficiency is analyzed in terms of substrate thickness, grating dimension and material refractive index. The results indicate a large tolerance for the deviations in practical fabrication. The measured coupling loss of the uniform grating is −2.7 dB at approximately 1465 nm with a 3 dB bandwidth of more than 40 nm. The proposed grating coupler provides a promising approach to realize efficient chip-fiber coupling for the SiGe photonic integration. [ABSTRACT FROM AUTHOR]

A compatible fabrication technology for integrating InGaAs nMOSFETs and Ge pMOSFETs is developed based on the development of the two-step gate oxide fabrication strategy. The direct wafer bonding method was utilized to obtain the InGaAs-Insulator-Ge structure, providing the heterogeneous channels for CMOS integration. Superior transistor characteristics were achieved by optimizing the InGaAs gate oxide with a self-cleaning process in atomic layer deposition, and modifying the Ge gate oxide by the ozone post oxidation (OPO) technique, in the sequential two-step gate oxide fabrication process. With the combination of the gate-first fabrication process, superior on- and off-state characteristics, i.e., on current up to 8.3 µA/μm and leakage as low as 10−6 µA/μm, have been demonstrated in the integrated MOSFETs, together with the preferable symmetric output characteristics that promises excellent CMOS performances. [ABSTRACT FROM AUTHOR]

Heterogeneous integration of micro-electro mechanical systems (MEMS) and complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) by 3D stacking or wafer bonding is an emerging approach to advance the functionality of microdevices. Aluminum (Al) has been of interest as one of the wafer bonding materials due to its low cost and compatibility with CMOS processes. However, Al wafer bonding typically requires a high temperature of 450 ° C or more due to the stable native oxide which presents on the Al surface. In this study, a wafer bonding technique for heterogeneous integration using electroplated Al bonding frame is demonstrated. The bonding mechanism relies on the mechanical deformation of the electroplated Al bonding frame through a localized bonding pressure by the groove structures on the counter wafer, i.e., press marking. The native oxide on the surface was removed and a fresh Al surface at the bonding interface was released through such a large mechanical deformation. The wafer bonding was demonstrated at the bonding temperatures of 250–450 ° C. The influence of the bonding temperature to the quality of the bonded substrates was investigated. The bonding shear strength of 8–100 MPa was obtained, which is comparable with the other Al bonding techniques requiring high bonding temperature. [ABSTRACT FROM AUTHOR]

A thin Si layer transfer process for monolithic 3D (M3D) integration is proposed using hydrogen ion (H+) implantation. The upper Si layer was transferred to CMOS circuits fabricated on the lower substrate by H+ implantation, oxide-to-oxide bonding, and a cleavage process at low temperature (< 500 °C). The M3D system comprising the photosensor connected to the CMOS device was demonstrated, where the thickness and roughness of the transferred Si layer were determined by H+ implantation and subsequent processes. The hetero-junctional photosensor was fabricated on the transferred Si layer, which generated the photocurrent ($\text{I}_{\text {ph}}$) by light exposure. The photosensor and ring oscillator circuits of the vertical structure implemented by the M3D process generated the $\text{I}_{\text {ph}}$ according to the light exposure intensity and showed different frequency behaviors accordingly. Compared with the continuous device scaling approach, M3D may be an alternative scheme for low-power, high-performance, and multi-functional devices. [ABSTRACT FROM AUTHOR]

Capacitive micromachined ultrasonic transducer (CMUT) was introduced as an alternative to the piezoelectric thick-film-based transducers in medical imaging applications. Gradually, CMUTs have been investigated in almost all the applications in acoustics due to their superior transduction properties. CMOS compatible process flow and limitless possibilities of miniaturization made CMUT a preferred choice for the ultrasound industry. This article comprehensively reviews all the applications in which CMUT was used until now. Such a complete review of the practical applications of CMUT has not been reported elsewhere. A topicwise presentation approach is adopted, and wherever possible, the necessary details of the device properties and experimental niceties were briefly covered. [ABSTRACT FROM AUTHOR]

Featured Application: Compact lasers integrated onto SOI for optical communications. The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity and scalability. However, Si itself cannot provide an efficient emitting light source due to its indirect bandgap. Therefore, the integration of III-V semiconductors on Si wafers allows us to benefit from the III-V emitting properties combined with benefits offered by the Si photonics platform. Direct epitaxy of InP-based materials on 300 mm Si wafers is the most promising approach to reduce the costs. However, the differences between InP and Si in terms of lattice mismatch, thermal coefficients and polarity inducing defects are challenging issues to overcome. III-V/Si hetero-integration platform by wafer-bonding is the most mature integration scheme. However, no additional epitaxial regrowth steps are implemented after the bonding step. Considering the much larger epitaxial toolkit available in the conventional monolithic InP platform, where several epitaxial steps are often implemented, this represents a significant limitation. In this paper, we review an advanced integration scheme of AlGaInAs-based laser sources on Si wafers by bonding a thin InP seed on which further regrowth steps are implemented. A 3 µm-thick AlGaInAs-based MutiQuantum Wells (MQW) laser structure was grown onto on InP-SiO2/Si (InPoSi) wafer and compared to the same structure grown on InP wafer as a reference. The 400 ppm thermal strain on the structure grown on InPoSi, induced by the difference of coefficient of thermal expansion between InP and Si, was assessed at growth temperature. We also showed that this structure demonstrates laser performance similar to the ones obtained for the same structure grown on InP. Therefore, no material degradation was observed in spite of the thermal strain. Then, we developed the Selective Area Growth (SAG) technique to grow multi-wavelength laser sources from a single growth step on InPoSi. A 155 nm-wide spectral range from 1515 nm to 1670 nm was achieved. Furthermore, an AlGaInAs MQW-based laser source was successfully grown on InP-SOI wafers and efficiently coupled to Si-photonic DBR cavities. Altogether, the regrowth on InP-SOI wafers holds great promises to combine the best from the III-V monolithic platform combined with the possibilities offered by the Si photonics circuitry via efficient light-coupling. [ABSTRACT FROM AUTHOR]

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal–silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion. [ABSTRACT FROM AUTHOR]

Highlights • We optimized the adhesive wafer bonding process for the fabrication of CMUTs. • A void-free and deformation-free adhesive wafer bonding process was demonstrated. • CMUTs with in-air resonance frequency of 6.44 MHz was fabricated and characterized. • An inverse CMUT structure is demonstrated enabling arbitrary cavity height control. Abstract It has been demonstrated that the adhesive wafer bonding technique benefits the fabrication of capacitive micromachined ultrasonic transducers (CMUTs) in the aspects of structural flexibility, CMOS process compatibility, and fabrication yield. Recently, the feasibility of fabricating CMUTs using benzocyclobutene (BCB) based polymer as both the adhesive and structural material was reported. However, the issues of voids at the wafer bonding interface, material deformation and electrode distance control need to be addressed. In this paper, we present an improved fabrication process that allows a void-free device with reduced polymer deformation. The chemical reactions during the BCB curing process were revealed using Fourier transform infrared spectroscopy. Microscopy and cross-sectional SEM images were employed to illustrate the structure improvement in terms of voids and polymer deformation. In addition, an inverse structure that allows an accurate control of the effective electrode distance was presented. The cross-sectional SEM images and the impedance measurement showing the dynamic response of the CMUT demonstrated the feasibility of this inverse structure. The differences between the inverse structure and the conventional structure were also discussed and compared. [ABSTRACT FROM AUTHOR]

Aluminum-aluminum wafer bonding is becoming increasingly important in the production of CMOS microelectromechanical systems. So far, successful bonding has required extreme processing temperatures of 450 °C or more, because the chemically highly stable oxide layer acts as a diffusion barrier between the two aluminum metallization layers. By using the ComBond system, in which a surface treatment and subsequent wafer bonding are both performed in a high vacuum cluster, for the first time successful Al-Al wafer bonding was possible at a temperature of 150 °C. The bonded interfaces were characterized using C-mode scanning acoustic microscopy and transmission electron microscopy, and featured areas of oxide-free, atomic contact. [ABSTRACT FROM AUTHOR]

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO. [ABSTRACT FROM PUBLISHER]

On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters. [ABSTRACT FROM AUTHOR]

We propose the Ge CMOS photonics platform with Ge-on-Insulator (GOI) substrate on which Ge mid-infrared photonic devices and Ge CMOS transistors can be monolithically integrated. The GOI wafer for the Ge CMOS photonics was fabricated by combining wafer bonding and H ion cut technologies. We studied the effect of thermal annealing on the GOI substrate in terms of crystal quality, surface morphology and electrical property. From Raman spectrum, it was found that the crystal quality of the Ge layer was significantly recovered after a 550 °C annealing in N 2 (or O 2 ) ambient for 1 h. Meanwhile, the surface roughness of the GOI substrate remained very low even after the annealing process. As a result, the significant improvements on electrical properties of the GOI substrate were confirmed by Hall measurement results. The carrier density of a GOI Hall device decreases from 2.9×10 16 to 8.9×10 15 cm −3 and hole mobility increases from 925 to 2295 cm 2 /V s. These results strongly suggest the necessity of a proper thermal annealing on improving the GOI qualities. [ABSTRACT FROM AUTHOR]

This paper reviews CMOS (complementary metal-oxide-semiconductor) MEMS (micro-electro-mechanical systems) fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator) CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered. [ABSTRACT FROM AUTHOR]

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 \mu \textm top entrant critical dimension and 50 \mu \textm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 \mu \textm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating. [ABSTRACT FROM AUTHOR]

The article offers information on the wafer bonding use for microelectromechanical systems (MEMS) devices and technology. Topics discussed include the importance of sodium (Na) in anodic bonding use to combine complementary metal-oxide semiconductor (CMOS) and MEMS devices, the advantage of aluminium (Al)- aluminium (Al) thermo-compression wafer bonding process, and the significant effects of process temperature on the bonding process.

This paper investigates silicon oxide bevel deposition to manage contamination in 3D integration with intermediate Back-End Of Lines (iBEOL) levels. Bevel etching and cleaning techniques are now sufficiently mature to remove efficiently contamination on wafer bevel area. However, 3D integration with iBEOL could require encapsulating metal lines, which emerge on the bevel area. This paper explores the efficiency of bevel deposition to answer contamination issues in 3D integration. Films are deposited on the bevel area of 300 mm wafers thanks to a torus shaped Plasma Enhanced Chemical Vapor Deposition (PECVD) configuration allowing encapsulation of the last few mm of the wafer frontside, backside and the apex in a single processing step. Deposition is carried out at 350 °C from mixture of SiH 4 and N 2 O at 2 Torr. When the gap between wafer and top insulator increases from 0.4 to 0.7 mm, the frontside deposition profile is shifted by 0.5 mm inward. In accordance with refractive index of 1.55 measured by ellipsometry, surface analysis by X-ray Photoelectrons Spectroscopy (XPS) show a film composition of SiO 1.8 N 0.3 with a quasi-constant composition from 147 to 149 mm wafer radius. The film resistance, evaluated by wet etch in 2% HF, leads to Wet Etch Rate (WER) ratio to thermal oxide of 4–5. We demonstrate that such films are compatible with oxide bonding. Thanks to a proper integration scheme, minimal impact on the bonding edge quality with bonding limit of 147.7 mm on real product Complementary Metal Oxide Semiconductor with 4 Metal levels (CMOS+M4) is reported. Finally, the effectiveness of the strategy to keep the metallic contamination at 1 × 1010 at.cm-2 or below is verified by either specific Liquid Phase Decomposition bevel Inductively Coupled Plasma Mass Spectrometry (LPD bevel-ICPMS) on BEOL wafers or by Vapor Phase Decomposition (VPD)-ICPMS standard process control on Front-End Of Line (FEOL) wet tool just after having cleaned BEOL wafers. [Display omitted] • 3D integration requires innovative strategies to process stacked wafers. • Wafer bevel deposition offers a solution to keep metal contamination compatible with front end of line tools. • The bevel management is compatible with wafer bonding and thinning. [ABSTRACT FROM AUTHOR]

This paper presents an ultrasonic fingerprint sensor based on a 24×8 array of 22MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 lm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ~14 kPa with a 28V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20×8 sub-array, resulting in 300mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10mm × 8mm) at a 1.2mm distance from the array. [ABSTRACT FROM AUTHOR]

A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 \Omega between two nearby interconnections. [ABSTRACT FROM PUBLISHER]

This paper describes a three-dimensional DRAM in which the floating body capacitance (FBC) of a fully depleted SO1 (FD-SOI) device is used as a storage node. This 1T DRAM lends itself particularly well to a 3D wafer-to-wafer bonding process because of the absence of deep etched and filled trench capacitor structure, and the improved thickness control tolerance in wafer thinning. A novel three-tier, 3D, IT embedded DRAM is presented that can be vertically integrated with a microprocessor, achieving low cost, high-density on-chip main memory. A 394 Kbits test chip has been designed and fabricated using the Lincoln Labs 3-Tier 3D 0.18 um fully depleted SO1 CMOS process where an earlier (and previously reported) successful 3D SRAM was obtained. The measured retention time under holding conditions in this 180 nm process is greater than 10 ms. The test chip measures an access time of 50 ns and operates at 10 MHz. [ABSTRACT FROM AUTHOR]

A high-aspect-ratio three-dimensionally (3D) stacked comb structure for micromirror application is demonstrated by wafer bonding technology in CMOS-compatible processes in this work. A vertically stacked comb structure is designed to circumvent any misalignment issues that could arise from multiple wafer bonding. These out-of-plane comb drives are used for the bias actuation to achieve a larger tilt angle for micromirrors. The high-aspect-ratio mechanical structure is realized by the deep reactive ion etching of silicon, and the notching effect in silicon-on-insulator (SOI) wafers is minimized. The low-temperature bonding of two patterned wafers is achieved with fusion bonding, and a high bond strength up to 2.5 J/m2 is obtained, which sustains subsequent processing steps. Furthermore, the dependency of resonant frequency on device dimensions is studied systematically, which provides useful guidelines for future design and application. A finalized device fabricated here was also tested to have a resonant frequency of 17.57 kHz and a tilt angle of 70° under an AC bias voltage of 2 V. [ABSTRACT FROM AUTHOR]

• Integration of III-V materials on SI substrates key to enable commercial viability. • Direct wafer bonding is a promising III-V integration technique for high-performance electronics. • Tunneling field effect transistors based on III-V materials are demonstrated. • Cryogenic applications are promising for III-V electronics enabling ultra-low power devices. In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for low-power electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal–oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits. [ABSTRACT FROM AUTHOR]