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The study deals with the handling of thin wafers in 3D integration. It concerns the fabrication of 300 mm wafers in industrial tools. Usually, the manufacturing is based on a temporary bonding process performed at 200 °C using a thermoplastic adhesive. In that condition bonding, thinning and dismounting are satisfactory. Moreover, the adhesive flattening during bonding results in an excellent thickness uniformity of the bonded pairs, with a small total thickness variation (TTV) value suitable for 3D integration. If the temperature is 150 °C or lower, the adhesive thickness uniformity is not acceptable anymore. An innovative temporary bonding process at low temperature has thus been developed. It consists in a carrier fabrication with highly uniform adhesive thickness. The standard coated adhesive is flattened with a first reversible temporary bonding at 210 °C. After a first dismounting, this carrier is then bonded to the target device wafer with a low bonding temperature, from 110 °C to 150 °C. Due to the pre-flattening, 80 μm thick silicon films with an excellent TTV value can thus be obtained even with a low bonding temperature required by the device wafer. Moreover, after the device wafer thinning, the final dismounting can be performed without any antisticking layer.

International audience; This study reports the manufacturing of Silicon On Polymer (SOP). It describes the transfer of a 200 mm diameter silicon thin film from a silicon on insulator (SOI) substrate to a flexible polymer. The thickness of the single-crystal silicon film was less than 200 nm and the transfer was achieved by bonding the SOI wafer to a temporary silicon carrier with an adhesive polymer. Various parameters of the transfer were investigated: adherence of the stack, temperature of bonding, temporary carrier and Si film thickness. The substrate and the SOI buried oxide were removed by mechanical grinding and chemical etching. The Si thin film was held on a flexible tape and the temporary carrier was dismounted. SOPs consisting of 20 to 205 nm thin Si films on a flexible polymer (230 μm) were successfully obtained. 200 mm diameter full wafers or patterned wafers could be transferred.

Vertical p-i-n lasers integrated by wafer-bonding and regrowth on a heterogeneous InP-on-SOI wafer are presented. We demonstrate for the first time lasers based on regrown III-V active regions efficiently coupled to Si-photonic DBR cavities.

Vertical p-i-n AlGaInAs lasers obtained from a single Selective Area Growth (SAG) step on a thin InP layer bonded to silicon wafers are presented. A PL extension from 1490 nm to 1645 nm was demonstrated on InP-SOI wafer. Based on this result, a record of 155 nm wide spectral range was obtained for FP lasers on InP-SiO 2 /Si wafer.

Monolayers (MLs) of transition metal dichalcogenides (TMDs) such as WSe2 and MoSe2 can be placed by dry stamping directly on broadband dielectric resonators, which have the ability to enhance the spontaneous emission rate and brightness of solid-state emitters at room temperature. We show strongly enhanced emission and directivity modifications in room temperature photoluminescence mapping experiments. By varying TMD material (WSe2 versus MoSe2) transferred on silicon nanoresonators with various designs (planarized versus non-planarized), we experimentally separate the different physical mechanisms that govern the global light emission enhancement. For WSe2 and MoSe2 we address the effects of Mie Resonances and strain in the monolayer. For WSe2 an important additional contribution comes from out-of-plane exciton dipoles. This paves the way for more targeted designs of TMD-Si nanoresonator structures for room temperature applications., Comment: 10 pages, 5 figures

Hybrid integration of III-V materials onto silicon by direct bonding technique is a mature and promising approaches to develop advanced photonic integrated devices into the silicon photonics platform. In this approach, the III-V material stack is grown on an InP wafer in a unique epitaxial step prior to the direct bonding process onto the silicon-on-insulator wafer. Currently, no additional epitaxial regrowth steps are implemented after bonding. This can be seen as a huge limitation as compared to the III-V on III-V wafer mature technology where multi-regrowth steps are most often implemented. In this work, we have studied the material behavior of an InP membrane on silicon (InPoSi) under epitaxial regrowth conditions by metal-organic vapor phase epitaxy (MOVPE). MOVPE requires high-temperature elevation, typically above 600 °C. We show for the first time the appearance of voids at 400 °C in an InP seed (100 nm) directly-bonded onto a thermally oxidized Si substrate despite the use of a thick SiO2 oxide (200 nm) at the bonding interface. This phenomenon is explained by a weakening of the bonding interface while high-pressurized hydrogen is present. A kinetic study of the hydrogen lateral diffusion is carried out, enabling the assessment of its lateral diffusion length. To overcome the void formation, highly efficient outgassing trenches after bonding are demonstrated. Finally, high-quality AlGaInAs-based multi-quantum well (MQW) heterostructure surrounded by two InP layers was grown by MOVPE on InPoSi template patterned with outgassing trenches. This process is not only compatible with MOVPE regrowth conditions (650 °C under PH3) but also with conventional fabrication processes used for photonic devices.

Integrated transmitters incorporating lasers and modulators on silicon are of primary importance for all communication applications, and at the same time are the most challenging to manufacture due to the need of hybrid III-V integration. In order to introduce III-V materials in low cost silicon platform manufacturing, direct bonding approach could present a great interest due to the growth limitation of III-V hetero-epitaxial layers directly onto silicon. Furthermore, by using a 100 nm silicon dioxide layer between the silicon wave guide and the III-V active stack, direct bonding allows the optical coupling necessary to build active optical device. Nevertheless, the potential low cost model of silicon photonic is based only on the hypothesis that we are able to work on the full surface of the 200/300 mm SOI photonic wafer. III-V wafer direct bonding is not suitable to fulfill this requirement for two main reasons. First, the maximum diameter available for III-V wafers is limited to 150 mm up to now. Secondly, the III-V material is necessary only on the emitter and receiver areas which represent only a very little part of the device area. Therefore, the most part of the reported full III-V wafer is lost by the layer patterning on required areas. To overcome this limitation in term of wafer diameter and to limit the loss of a very expensive starting material we have developed at LETI a collective die direct bonding process. The idea is to bond collectively III-V chips only where there are necessary and on the full photonic SOI surface. The die size is selected to be slightly higher than the targeted area in order to be compatible with a wafer notch alignment and avoid any accurate alignment with alignment marks. The requirements for direct bonding are exactly the same than for wafer bonding, but die direct bonding is obviously more difficult due to the dicing step which generates a high level particle contamination. All the process steps have to be adapted to be compatible with die handling and the die cleaning before bonding have to be strongly optimized to remove this high particle contamination. We have then developed specific silicon die holder in order to clean the die surfaces collectively in classical microelectronics high performance cleaning tools. A test vehicle containing few hundred 3*3 mm² dice will be used to evaluate the collective die direct bonding process. Because III-V materials are not as mature as silicon, the bonding process will be firstly evaluated with silicon dies. After optimization, Indium phosphide dice will be used to validate the global process. Bonding interfaces of dice are finely characterized by Scanning Acoustic Microscopy and SAM images will be processed in order to quantify the bonding yield and the die positioning accuracy. Figure 1

International audience; The development of a silicon temporary carrier for thin wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4 J/m(2) and lower than the adherence of a stack without any antiadhesive layer (above 4 J/m(2)). The carrier was nevertheless suitable for different back side processes in 300 mm grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon device wafer of 80 pm. The carrier recycling was possible without any new preparation.

300 mm diameter thinned-down wafers are manufactured using temporary adhesive bonding. A thermoplastic adhesive and a silicon carrier are used to fabricate 100 μm thick silicon wafers. The impact of temperature on the thickness homogeneity of temporary bonded stacks is studied. From 150 °C up to 300 °C, the total thickness of the structure increases with the temperature. Moreover, its amplitude strongly increases with the thinned wafer stress and the adhesive thickness. On the contrary, it does not depend on the different interface adherence. The thinned wafer stress results in a significant peeling force which drives the deformation of the structure. This deformation is possible because of the high elasticity of the polymer at high temperature. To reduce this deformation, an alternative carrier is proposed yielding reduction of the adhesive thickness at the bonded edge only.

Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some additional challenges compared to Wafer-To-Wafer processing. This paper presents a 300mm wafer complete solution developed at LETI to improve bonding yield of D2W hybrid bonding using copper interconnections until the assessment of the electrical performances thanks to a dedicated 300mm electrical test vehicle and robust stacking system. Stackings with +/-1.5μm accuracy and excellent bonding interface have been obtained (80% bonding yield). After stacking and annealing, the die can be thinned down to 10μm without damage. Electrical yield measured on daisy-chains with more than 20.000 connections present more than 75% yield and shown very limited drift after preliminary environmental reliability tests. All these results confirmed the high industrial potential of D2W hybrid bonding technology.

Direct wafer bonding of wafers is now well establish. However in many interesting applications, direct bonding of die to wafer can lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications.

International audience; The presented work concerns the manufacturing of very thin silicon wafers for a 3D Integrated Circuit industrial purpose. One of the key parameters of the 3D integration is the adherence of the bonded structure which involves silicon wafers and a polymer adhesive as an intermediate layer. The scope of the paper is to determine the suitable adherence of the stack for a successful manufacturing onto industrial tools. For this purpose the dismounting capacity of the fully automated equipment EVG (R) 850DB depending on the adherence energy is studied. Direct and polymer bonded silicon pairs are prepared. Their energies of adherence cover a large range of energy from 0.3 to 14 J/m(2). The automatic mechanical dismounting process is successful when the stack adherence is 1.2 J/m(2) or lower. This value does not depend on the bonded structure type direct bonded pairs or thinned polymer bonded pairs exhibit the same behavior regarding the dismounting capacity. And we demonstrate that the industrial manufacturing of 70 pm thin silicon wafers is possible if the adherence is 0.4 J/m(2) to 1.2 J/m(2).

In this paper we study the formation and behaviour of liquid Al-Ge alloy, its solidification, the resulting microstructures and the appearance of voids in bonded structure for MEMS packaging. The underneath layer influences the wettability of liquid Al-Ge as well as its solidification which can lead to undesirable Al dendrites. Each underneath layer imposes a critical value for the cooling rate above which dendrites are likely to appear. Blanket and patterned Al/Ge deposited wafers are bonded together with process parameters optimized thanks to previous results. The interfaces present a dendritic-free eutectic structure. Micro-voids are observed at the interfaces between Al and Ge phases. The Kirkendall effect and thermal stresses are two possible reasons for voiding phenomenon.

Nowadays silicon (Si) based die-to-wafer (D2W) direct bonding technique is of great interest for enabling advanced 3D-integrated device applications. The small size of bonded dies makes an important difference from standard wafer-to-wafer direct bonding in terms of bonding mechanism or bonding strength evolution, because it allows rapid lateral diffusion of the chemical species related to direct bonding at the interface. In the case of hydrophilic SiO2-SiO2 direct bonding, water plays an essential role for bonding area evolution. Control of sample storage condition is therefore quite important because the humidity of storage environment may affect water diffusion at the bonding interface. However, there is a lack of in-depth study about the reliability of the SiO2-SiO2 D2W direct bonding due to the difficulty of evaluating the strength of the bonding interface. In this paper, using a previously developed modified four-point flexion test, we have systematically investigated the effect of sample storage before or after post-bonding annealing on SiO2-SiO2 D2W direct bonding energies. Weakening of the SiO2-SiO2 D2W direct bonding interfaces was observed during sample storage in humid ambiences after post-bonding annealing. This unexpected weakening effect could be explained by the water stress corrosion which occurs around asperity contacts of the bonded SiO2 surfaces due to water molecule diffusion at the bonding interface after post-bonding annealing.

Nowadays Silicon direct wafer bonding is a mass production technology in many different applications. Starting around the sixties for industrial optical system elaboration, its major development is now in the microelectronic, microtechnology and optoelectronic fields. Obviously to reach such a mature level, the direct bonding mechanisms have to be established. The silicon or silicon dioxide direct bonding is now well established and direct bonding using metallic surfaces starts also to be investigated. For instance, copper or titanium direct bonding mechanism are established. The behavior of hybrid direct bonding using surfaces composed of both materials can then be understood. This hybrid bonding paves the way to high-density interconnection bonding for 3D applications.

International audience; This paper deals with the effect of the silicon bonding temperature with thermoplastic adhesive. The bonding temperature exhibits a significant effect on the morphology and on the adherence energy of the bonded stack. A suitable temperature control leads to an excellent homogeneity of the bonded structure and an optimal total thickness variation (TTV) value. Using Brewer Bsi5150 adhesive material, 275 A degrees C appears as the optimal bonding temperature in order to optimize the TTV from 55 A mu m down to 5 A mu m. The adherence of the structure is also increased with high bonding temperatures. Indeed, the adherence energy is above 10 J/m(2) when the temperature is above 250 A degrees C. On the contrary, when the temperature is less than 150 A degrees C, the adherence is only around 1 J/m(2). Noteworthy, this value is suitable for back side processing and a mechanical debonding of the structure without any need of other specific layer which could lead to a very simple temporary bonding process.

International audience; Direct bonding of PECVD SiOx films is of great interest in the field of microtechnologies for applications such as stacked structures, thin film transfers, whose fabrication processes still deserve to be investigated. This work deals with the influence of water diffusion in the SiOx films deposited onto 200mm Si wafers and its impact on adherence of hydrophilic surfaces. The as-deposited film nature induces various stresses. Stresses evolutions and water penetration are characterized and a correlation is made between the kinetics of both stress variations and water diffusion through the oxide thin films. Impacts of room temperature (RT) storage prior to bonding and thermal treatments applied for strengthening the bonding is shown. As direct bonding operates through surface asperities deformation, specific mechanical properties of such contact asperities can lead to a stronger bonding by increasing bonding area (Fournel 2015, Rieutord 2006; Ventosa 2008; Ventosa 2009). As the mechanical properties of silicon oxide material are greatly influenced by internal water concentration, aging and water diffusion on asperity have a real impact in term of direct bonding energy. Moreover at bonding interfaces, it is observed by X-ray reflectivity (XRR) that aging of deposited SiOx prior to bonding enables shallower bonding gaps, indicating better bonding interface closure which is coherent with the bonding energy enhancement. All these results confirm the link between water diffusion and hydrophilic surface adherence of deposited SiOx films.

International audience; Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.

In this study, fabrication of monolithic triple junction (3J) GaInP/AlGaAs/Si solar cells is reported by different wafer bonding approaches: (i) the most straightforward, direct GaAs/Si wafer bonding; (ii) an innovative 2-step approach combining epitaxy of GaAs bonding layer on Si cell followed by GaAs/GaAs direct wafer bonding; and (iii) Surface-Activated GaAs/Si wafer Bonding (SAB). Bonding interfaces properties are comparatively studied, and the performance of resulting III-V on Si triple junction devices is examined. Open-circuit voltages close to 2.9V are obtained in all cases, but large differences in fill factors between the bonding methods are observed, probably due to the presence of an oxide layer.

Low temperature direct bonding technologies are now widely used for many applications. Mechanisms of some of these technics will be presented. The different way to obtain low temperature direct bonding will then be compared with their respective advantages and drawbacks.

The Solar cell front side is a key design point for improved cell efficiency as a trade is made between optical losses (shadowing effect) and electrical losses (resistance). One solution consists in frontside contacts report to the cell’s backside using through device conductive vias. By this way metal shadowing could be drastically reduced without increasing resistive losses. Such architecture is called Metal Wrap Through (MWT) and has been developed on silicon solar cells. Its application to III-V Multi-Junctions Solar Cells (MJSC) could be of great interest and has been simulated and studied for several years. We present here first functional MWT III-V dual-junction solar cells. Prototype developments have been based on inverted tandem solar cell (GaInP/GaAs) epitaxial structures grown on GaAs substrates. Front side contacts have been reported on the device’s backside using specifically adapted Trough Semiconductor Via (TSV) technologies. Finally, the III-V active film was transferred on a conductive r...

International audience; The kinetics of water diffusion through the gap formed by the direct bonding of two silicon wafers is studied using two different techniques. X-ray reflectivity is able to monitor the interface density changes associated with the water front progression. The water intake is also revealed through the defect creation upon annealing, creating a rim-like pattern whose extent also gives the water diffusion law. At room temperature, the kinetics observed by either technique are consistent with the Lucas-Washburn law for diffusion through a gap width smaller than 1 nm, excluding any significant no-slip layer thickness. Published by AIP Publishing.

Tandem GaInP/GaAs//Si(inactive) solar cells were manufactured by direct wafer bonding under vacuum. At this early stage, an inactive silicon substrate was used (i.e. n+ Si substrate instead of an active n-p Si junction). Bonded devices presented an S-shaped J-V curve with a kink close to Voc caused by a built-in potential barrier at the III-V//Si interface that reduces the fill factor and therefore the efficiency of the device by 7% compared to the stand-alone GaInP/GaAs tandem cells. Nevertheless, losses in Jsc and Voc caused by the bonding process, account for less than 10%. AlGaAs single junction cells, designed to be bonded on a silicon cell for low concentrator photovoltaics (LCPV), were also manufactured reaching an efficiency of 15.9% under one sun AM1.5G spectrum for a 2cm2 cell.

Direct silicon or silicon dioxide wafer bonding appears as a more and more attractive way to build up stacking structures in micro-technologies. For this, high bond strengths and void-free bonding interfaces are required. Although Si-Si hydrophilic bonding provides suitable bonding energies after low temperature annealing (T

CEA-INAC, 17, rue des Martyrs 38054 GRENOBLE - France Low temperature wafer bonding is requested in many applications. Most of them involve silicon or silicon dioxide bonding interfaces. Studying bonding process / mechanism in the low temperature range (

Promoted by the component miniaturization trend, three-dimensional integration appears as a promising option for implementation of the next generation of integrated circuits. In this context, copper is still an interesting material to be integrated to vertical interconnexion through direct metal-metal bonding processes. However, it was already reported that voiding phenomena occur in bonded copper layers for temperature beyond 300°C leading to serious reliability problems. This paper aims at explaining voiding mechanisms in the specific metal bonding configuration. Voiding characteristics are compared in different structures allows highlighting several thermal effects. It appears that the mechanical stress sustained by copper layers during post-bonding thermal processes is the main contribution in the voiding phenomenon. Creep mechanisms occurring in polycrystalline copper structure could be considered as the origin of this phenomenon. This study offers better understanding of reliability problems in structures involving encapsulated copper layers and can be used as guideline for metal bonding integration.

An innovative method to fabricate large area (up to several squared millimeters) ultrathin (100 nm) monocrystalline silicon (Si) membranes is described. This process is based on the direct bonding of a silicon-on-insulator wafer with a preperforated silicon wafer. The stress generated by the thermal difference applied during the bonding process is exploited to produce buckling free silicon nanomembranes of large areas. The thermal differences required to achieve these membranes (≥1 mm(2)) are estimated by analytical calculations. An experimental study of the stress achievable by direct bonding through two specific surface preparations (hydrophobic or hydrophilic) is reported. Buckling free silicon nanomembranes secured on a 2 × 2 cm(2) frame with lateral dimensions up to 5 × 5 mm(2) are successfully fabricated using the optimized direct bonding process. The stress estimated by theoretical analysis is confirmed by Raman measurements, while the flatness of the nanomembranes is demonstrated by optical interferometry. The successful fabrications of high resolution (50 nm half pitch) tungsten gratings on the silicon nanomembranes and of focused ion beam milling nanostructures show the promising potential of the Si membranes for X-ray optics and for the emerging nanosensor market.

Direct bonding is now a well-known technique to join two flat surfaces without any additional material. This technique is used in many applications and especially in SOI (Silicon-On-Insulator) elaboration or in some backside imager manufacturing processes which are now almost in mass production. Direct bonding mechanism study is then very important in order to clearly understand this bonding behavior. Especially in the case of silicon or silicon dioxide hydrophilic surface, the role of water is essential. Water could lead to lots of different reactions at the bonding interface and especially the water stress corrosion could play an important role in the direct bonding mechanism. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0031505jss] All rights reserved.

International audience; The use of reconstructed silicon wafers obtained after high temperature annealing under H-2 atmosphere was demonstrated as an efficient way for increasing the bonding energy of silicon hydrophobic bonding (Rauer et al. 2013). Mechanisms occurring in these bondings are the focus of this paper. Si bonding interface closure was analyzed at the nanometer scale using X-Ray Reflectivity and Fourier Transform InfraRed spectroscopy in multiple internal reflexion mode. These two characterization techniques enable one to follow the interface closure taking under consideration mechanical and chemical aspects. We have shown that the terrace morphology and the monohydride surface termination specific to reconstructed Si surfaces both play a role in obtaining an efficient bonding gap closure after annealing at low temperature.

The electrical, mechanical, and hermeticity properties of low-temperature, plasma activated direct silicon bonds were investigated. On individual dies with a bonding area ranging from 1–4 mm 2 , the bonded interface was found to have a capacitance ranging from 2.62 pF/mm 2 –2.89 pF/mm 2 at 1 kHz. Linear I-V curves showed ohmic behavior without hysteresis. A resistance around 2.2 � and a current density of 1.1 × 10 4 A/m 2 was measured at DC. We speculate that the capacitive and resistive responses are related to traps that are formed during the plasma activation process. The applied bonding process resulted in hermetic sealing with 100% yield on 2 × 481 dies. The maximum leak rate of the seals was 2.4 × 10 −11 mbar·l·s −1 , but could be significantly lower. No gross leaks were observed following a steady-state life test, a thermal shock test, and a moisture resistance test applied on 100 dies.

International audience; SOI circuit exhibits excellent performance and rehabilitee but with the component miniaturization trend and the clock frequency increase, the self-heating phenomena that arise from the SOI structure itself must not be underestimated. In order to minimize this problem, several candidates have been identified to replace the buried silicon oxide (SiO2) by high thermal conductive dielectric layers such as HfO2, Si3N4, diamond or Al2O3. In order to elaborate a SOI structure using this kind of innovative buried dielectric, first of all, their direct bonding with silicon has to be studied. In this work, we investigate the bonding thermal behaviour of Si/Al2O3 and Al2O3/Al2O3 direct bonded structures: bondings are submitted to room temperature up to 900 A degrees C annealing. Amorphous or crystallized Al2O3 thin films were used in this study. Bonding energies are measured in an anhydrous atmosphere and bonding defectivity is analysed using scanning acoustic microscope (SAM). With amorphous a-Al2O3 layer, for T > 200 A degrees C, high bonding energy are obtained even if high defect density appeared when annealing temperature exceeded 400-500 A degrees C. Spontaneous debonding phenomena even occurred for a-Al2O3/a-Al2O3 direct bonding. This defectivity, unobservable using infrared camera, may be explained by chemical or structural Al2O3 modification such as gases desorption, internal stress or crystallisation state. Bonding with crystallized Al2O3 film has been also characterized by infrared spectroscopy and complementary analysis. No high defect density is observed with crystallized Al2O3 layer. Based on these results, an Al2O3 bonding mechanism is proposed.

For both hydrophilic and hydrophobic surface preparation, using the combination of advanced surface treatment and tuned annealing process, void free Si/Si direct bonding have been successfully obtained. The pre-bonding procedure involves only low temperature (

In order to control simultaneously the nanostructures size, density and positioning, nanopatterned substrates are elaborated using an original process based on the revelation by preferential chemical etching up to the surface of a buried square dislocation network obtained by direct twist wafer bonding. By including the dislocation network into a SOI substrate thin film the surface patterning evolution during the selective chemical etching for 20 and 50 nm periodicity samples is controlled and checked by Scanning Electron Microscopy (SEM). A dislocation network periodicity dependent surface grating is showed. Si mesas with efficient aspect ratios are obtained after a second selective chemical etching allowing the further Ge islands self-assembled growth. Germanium growth equivalent to 10 Aå layer is performed at 600{degree sign} C on 50 nm periodicity nanopatterned surfaces. For different cooling rate from deposition temperature to room temperature the dots size, shape and density are characterized by Scanning Tunneling Microscopy and SEM.

Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.

A direct wafer bonding process has been developed to accurately control both the bonding interface twist and tilt angles between a monocrystalline layer and a bare monocrystalline wafer. This process is based on the bonding of twin surfaces produced by splitting a single wafer, using for instance the Smart Cut® process. A targeted control of ±0.005° is obtained for the twist angle without any crystallographic measurement. Moreover, pure twist-bonded interfaces have been artificially made between two (001) bonded silicon surfaces.

Ultrathin (001) Si films bonded onto (001) Si wafers, inducing grain boundaries with twist angles varying from 0.5° to 12°, were studied by transmission electron microscopy. A great structural difference between low (ψ 6°) twist angles was observed. In low twist angle grain boundaries, “twist interfacial dislocations” are dissociated and produce rough interfaces with no oxide precipitates. It is the opposite in high-angle grain boundaries: there is no dissociation, the interfaces are smoother but contain oxide precipitates. These differences are not attributed to the thin thickness of one grain, but to the large atomic differences between high- and low-angle twist grain boundaries, which is not the case for tilt grain boundaries.

Investigation of a surface patterned by buried dislocation networks is performed with grazing incidence x-ray scattering (GIXS). It is shown that surface long-range undulations lead to a azimuth-dependent diffusion spot, the scattering vector of which is mainly parallel to the x-ray propagation direction. This unusual scattering direction with GIXS is explained by the scales of the scattering objects. A geometrical model is proposed to extract the periodicity of the surface from GIXS.

Single Si/SiO 2 quantum wells were fabricated using silicon on insulator (SOI) substrates, the upper barrier being a thin thermally oxidized Si layer. Samples were Er and O implanted at low energy in order to center their concentration profile in the well, and then annealed. A bulk Si sample implanted under the identical conditions was used as a reference. We present low temperature photoluminescence results using UV excitation in order to create photogenerated carriers mainly in the Si well. We show that the 1.54-μm photoluminescence is much more intense for Er in a well than for Er in implanted bulk silicon. We show that infrared emission occurs through an energy transfer mechanism from Si to Er centers. Confinement prevents the escape of photogenerated carriers towards the substrate and promotes energy transfer towards optical active erbium center.

International audience; Ultrathin films of silicon bonded on 4-inch (001) silicon wafers have been obtained by combining a direct hydrophobic silicon bonding technique with a layer transfer. The strain field produced by the dislocation network localized at the bonded interface is a good candidate to induce a long-range order growth of nanostructure. To be able to make this new kind of substrate, knowledge of the dislocation strain field extension is essential. Grazing incidence X-ray diffraction allows us to measure its spatial extension through the diffraction peak satellites due to different dislocation networks. The exponential decay of these peaks were measured and compared. We found that the decrease of the strain field extension is almost two times lower for the screw dislocation network than for the ‘mixed’ dislocations one. The film thickness control is then two times more critical for the screw dislocations.

International audience; Twist-bonded Si/Si (0 0 1) and Si/SiO2 interfaces have been investigated by grazing incidence X-ray scattering methods. For Si/Si (0 0 1) bonding, conventional X-ray reflectivity reveals the good quality of the interfaces in terms of flatness and roughness. In-plane grazing incidence diffraction measurements around the (2 2 0) reflection show satellite peaks close to the substrate and the layer diffraction peaks. These sharp satellites are produced by a periodic displacement resulting from a very regular buried dislocation network. The Si/SiO2 bonding has been studied with X-ray reflectivity within a transmission geometry. The analysis of the data shows the high quality of both bonded Si/SiO2 and thermal oxide SiO2/Si interfaces.

International audience; Ultra thin film of silicon bonded on 4 in. (001) silicon wafers have been obtained by combining a direct hydrophobic silicon bonded technique with a layer transfer. The twist angle between the ultra thin Si film and the Si substrate was varied from 0 to 15°. X-ray reflectivity measured the thickness and the roughness of the ultra thin films. Complementary results concerning the interface structure were obtained with high resolution transmission electronic microscopy. It is shown that an ultra thin film (a few nm) can be reproductively prepared upon the full 4 in. wafers. Moreover, this process gives very small thickness fluctuations and a small surface roughness. The bonding interface has a low concentration of oxide precipitates and presents two arrays dislocations respectively, due to the twist (screw dislocations) and a residual tilt angle (mixed dislocations) of the crystals. Dissociation of the screw dislocations is also observed on the lowest twist angle sample.

We performed a low temperature photoluminescence study of ultra thin single Si/SiO/sub 2/ quantum wells. We observe a strong quantum confinement effect and a high increase in the internal quantum efficiency in the thinnest wells.