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A 1.2-Mpixel indirect time-of-flight (ToF) CMOS image sensor is presented to lower peak current and to cancel out multi-user interference. The proposed 4-tap 3.5- $\mu \text{m}$ demodulation pixel is optimally designed to improve quantum efficiency (QE) and demodulation contrast (DC). A new “multiple-interleaving” scheme is proposed to reduce the peak current and self-compensate fixed-pattern phase noise (FPPN) with the minimal side effect of DC imbalance. To cancel out interference from the other ToF sensors, a multi-user interference cancellation (MUIC) scheme based on pseudorandom modulation is adopted. From the measurement results, we achieve a high QE of 38% at 940 nm and a high DC of 96% and 80% at 100- and 200-MHz modulation frequencies, respectively. With the superior pixel performance, the depth noise of $\times $ 2 binning modes, respectively. The multiple-interleaving scheme suppresses the peak current to less than 0.9 A and removes the column FPPN with constant DC for the whole pixel array. The proposed MUIC proves that at least two interferers can be successfully rejected. The sensor chip is fabricated in a two-stack process with 65 nm for the top die and 65 nm for the bottom die.

This letter presents a low-power continuous-time delta–sigma modulator (CTDSM) that operates at a 0.6-V supply. The loop filter of the CTDSM is realized with inverter-based integrators and negative-R compensation on each integrator’s virtual ground. A body-biasing technique is used for inverters as well as for negative-Rs to ensure robustness against process, voltage, and temperature (PVT) variations. A prototype CTDSM is fabricated in a 28-nm CMOS process and achieves 83-dB SNDR, 84-dB SNR, and 86.5-dB DR in a 40-kHz bandwidth while consuming only 33.6 $\mu \text{W}$ from a 0.6-V supply. This corresponds to the state-of-the-art Schreier FoM of 177.3 dB.

For years, there has been a strong drive for sub-micron pixel development, in spite of reaching the visible light diffraction limit, because a smaller pixel pitch of CMOS image sensors (CISs) is inevitably required for ever-miniaturizing camera modules as mobile devices incorporate more cameras, few of which are dedicated to ultra-high-resolution zoomed images [1]. To that end, image sensor vendors have tried to find new ways to avoid reduction in sensitivity and more crosstalk in the sensor through pixel architecture change and/or fabrication process refinement [2] –[4]. For example, a $0.7 \mu m$ pixel sensor was demonstrated with acceptable photodiode (PD) full-well capacity (FWC) of $\gt 6$,000e- as well as signal-to-noise ratio (SNR) of $\sim32$ dB without optical/electrical crosstalk by employing state-of-the-art full-depth deep-trench isolations (FDTIs). [4] However, further scaling requires elaborate fabrication innovation and layout ideas. At the same time, meeting every aspect of pixel performance compared to the previous generation becomes even more difficult, e.g., with respect to dark or illuminated characteristics, fixed-pattern or temporal noises, etc. The latter, in particular, is associated with in-pixel source-follower (SF) amplifiers. Therefore, electrical performance of scaled in-pixel transistors cannot be overlooked. In this paper, a 32-megpixel (MP) CIS with $0.64 \mu m$ unit pixels is demonstrated with FDTI design. Innovations in terms of fabrication and design to achieve this performance with scaling are discussed.

A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- of high full-well capacity (FWC) per a tap is obtained by employing a supplementary MOS capacitor. 36% of high quantum efficiency (QE) has been achieved by backside scattering technology (BST) and thick silicon process. In addition, demodulation contrast (DC) is improved to 86 % by additional deep photodiode doping process for static potential gradient in a photodiode.

A 0.8μm-pitch 108 megapixels (Mp) ultrahigh-resolution CMOS image sensor has been demonstrated for mobile applications. The Nonacell was developed through a 3x3 color filter and 1x3 shared pixel structures which can be operated the 3 binning mode to achieve 12Mp resolution and improve low-illuminance signal-to-noise ratio (SNR) characteristic. The full-well capacity (FWC) of Nonacell was achieved up to 18,000e- using FD-shared dual conversion gain (CG) technology, and excellent high-illuminance SNR was demonstrated.

As the smart mobile device market continues to grow and the number of cameras per device rapidly increases, demand for CMOS image sensors (CIS) also increases. Two major trends in mobile device cameras are: (1) adopting smaller pixels that enable greater pixel count at similar optical format, and (2) bigger pixels for higher image quality. To be more specific, front-facing cameras have a trend towards smaller pixels, while rear main cameras have a trend towards both smaller and bigger pixels. The optical format of front-facing cameras is especially limited due to existing bezel-less or border-less display designs, yet higher resolution still-shot and video (such as 4K UHD) recording is desired. To implement greater pixel count in a limited camera module size, scaling of pixel size is required. The main challenges are to maintain acceptable photodiode full-well capacity (FWC) and sensitivity, while suppressing optical crosstalk [1]. To completely eliminate both electrical and optical crosstalk, deep-trench isolation (DTI) has evolved from early BDTI (Back-side DTI) to current FDTI (Front-side DTI) technology, which is also called full-depth DTI. In this paper, a 44Mpixel CIS with 0.7µm pixels using full-depth DTI is demonstrated.

A 0.8 μm-pitch 64 megapixels ultrahighresolution CMOS image sensor has been demonstrated for mobile applications for the first time. Full-well capacity (FWC) of 6k e- was achieved in 0.8 μm pixels as the best in the world, and the advanced color filter (CF) isolation technology was introduced to overcome sensitivity degradation. Dual conversion gain (CG) technology was also first applied to mobile applications to improve the FWC performance of Tetracell up to 12k e-. In addition, highly refined deep trench isolation (DTI) and photodiode design significantly improved dark noise characteristics.

CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.

Process design of multi-stage forging for a bolt with nonaxisymmetric washer cam has been studied by using finite element method. For shape complexity of the bolt, it is impossible to manufacture in a single stage forging. To design multi-stage forging for the bolt the forging load and fiber flow of each step have been analyzed by using commercial finite element code DEFORM-3D. Simulated results have been compared with experimental ones. Multi-stage forging process has been designed with four stages. The workpiece should be eccentric shape until third forging stage. And then bolt head and washer of eccentrical shape is created in last stage. As a results, It was predicted that shape of product would be good and effective strain would be uniformly distributed in the product. Also, it was predicted whether defects would exist or not by reviewing the fiber flow.

Recently the environment of Korean business cultures has rapidly changed. Companies have their own images. They are Perceived among companies, so they are awarded as the important factors of the making relation. Especially the importance of corporate image was brought to the fore and it has been dealing with continuously and variously since 1990s. Previous empirical research has focused on the orientation of consumer in perceived company image. But the goal of this study is focused on the effects of the perceived image between corporations in trust and commitment of relationship. The results of this study perceived image were indicated to have an effect on trust. In addition, trust were also indicated to have an effect on commitment. C.E.O, Growth, Innovation image were indicated to have an effect on trust as the important factors.

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.

Microstructural reactions of Pd/Ge/Ti/Au contact to AlGaAs/InGaAs pseudomorphic high electron mobility transistor with an undoped GaAs/AlGaAs cap layer have been investigated using cross-sectional transmission electron microscopy, and the results are used to interpret the electrical properties of the ohmic contact. In the as-deposited state, a quaternary phase of PdxAlGaAs containing excess Ge atoms is formed at the interface of Pd/AlGaAs and some microvoids exist at the Pd layer in the vicinity of the interface. When the ohmic metals deposited on the undoped cap layer were annealed, the lowest contact resistivity of 9.1×10−5 Ω cm2 is obtained at 380 °C. AuGa compound is formed at the PdGe/undoped-AlGaAs interface as a result of the reaction between the ohmic metal and the undoped GaAs cap. This is due to the fast in-diffusion of Au toward the undoped AlGaAs through grain boundaries of the PdGe compound. The layer structure is changed to TiO/AuGa/PdGe/AuGa(TiAs+epi-Ge)/undoped-AlGaAs. The AuGa compound en...

New isolation scheme for CMOS image sensor pixel is proposed and its improved dark current performance is reported. It is well known that shallow trench isolation (STI) is one of major sources of dark current in imager pixel due to the existence of interfacial defects at STI/Si interface. On the account STI-free structure over the whole pixel area was previously reported for reducing dark current. As the size of pixel pitch is shrunk, however, it becomes increasingly difficult to isolate in-pixel transistors electrically without STI. In this work, we implemented hybrid type isolation scheme of removing STI around photodiode to suppress the dark current and remaining STI near transistors to guarantee the electrical isolation of transistors in pixel. It was successfully achieved that the dark current was significantly reduced by removing the STI around the photodiode together with normal operation of in-pixel transistors.

As pixel sizes continue to scale down, backside-illuminated (BSI) technology has been recently adopted as a solution to improve pixel SNR performance [1,2]. In addition, as the application of image sensors widens from digital still cameras to digital camcorders, high-resolution and high-speed operation are required. This paper presents 1/2.33-inch 14.6Mpixel CMOS image sensor employing a 1.4μm BSI pixel architecture with a floating-diffusion (FD) boosting scheme that enables high SNR and high speed read-out.

Microstructural evidence on the formation of a heavily Ge-doped layer below Pd/Ge-based ohmic contact to AlGaAs/InGaAs pseudomorphic high electron mobility transistor was obtained. The contact resistivity is decreased by two orders of magnitude as InGaAs channel is intermixed. This originates from the formation of Au2Al and Au7Ga2 compounds below the contacts during annealing, via production of group III vacancies. The vacancies play a role in producing free electrons by the incorporation of Ge atoms, resulting in intermixing of InGaAs as well as reduction of contact resistivity.

Microstructural evidence on direct contact of Au/Ge/Ni/Au ohmic metals to a InGaAs channel in AlGaAs/InGaAs pseudomorphic high electron mobility transistor with an undoped GaAs/AlGaAs cap layer was found using transmission electron microscopy, and the results were used to interpret the electrical properties of the contact. The lowest contact resistivity of 3.8×10−6 Ω cm2, obtained at 420 °C annealing, is due to the penetration of the interfacial compounds, Au2Ga and Au2Al, into the buried InGaAs channel. The direct contact of the compounds to the channel causes the reduction of series resistances between the ohmic compounds and the channel, resulting in the low contact resistivity.

A 1/2-inch 7.2Mpixel CMOS image sensor with 2.25mum pixels employs a 4-shared pixel structure with pixel-level charge summation. It achieves a 57% fill factor, full well capacity of 14ke- with 41dB maximum SNR at full resolution, 8e-random noise, 15ke-/lux-s sensitivity, and a 3dB increment in SNR for pixel-level charge summation and sub-sampling operation. A 0.13mum Cu process is used

The Pd/Ge/Ti/Au ohmic contact to AlGaAs/InGaAs pseudomorphic high electron mobility transistor was investigated with the etch depth of an undoped GaAs/AlGaAs cap layer. The contact resistivity decreases from 9.5×10−5 to 2.3×10−6 Ω cm2 when the contacts were formed on a n-Al0.23Ga0.77As layer by removing the undoped cap layer. X-ray diffraction results show that the good ohmic contact is due to the formation of Au2Al as well as β-AuGa. Both compounds play a role to create group-III vacancies, followed by the incorporation of Ge into group-III vacancies, namely, creation of free electron below the contact. This results in the considerable elimination of contact resistivity by lowering the effective tunneling barrier.

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

Microstructural reactions of a Pd/Ge contact to a AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT) have been investigated, and the results have been used to interpret the changes of electrical properties of the PHEMT. In the as-deposited state, a ternary phase of Pd x GaAs containing excess Ge atoms is formed at the interface of Pd/GaAs. When the ohmic metals deposited were annealed at 300°C, a PdGe compound was formed and its contact resistivity was decreased to 1.2×10-7 Ω·cm2. This is due to the preferential outdiffusion of Ga atoms to the PdGe during annealing, leaving Ga vacancies behind. Simultaneously, Ge atoms are indiffused to the GaAs and occupy the Ga vacancies, converting the interfacial GaAs layer into n+-GaAs. The low-temperature PdGe ohmic contact allows changing the sequence in the formation of source/drain and gate electrodes in the PHEMT process. The device performance was remarkably improved as the annealing temperature was increased or the contact resistivity was reduced. The PHEMTs with a gate length of 1.1 µm, annealed at 300°C, exhibit maximum transconductance of 381 mS/mm.

The effect of existence of undoped GaAs/AlGaAs cap layers on Ohmic contact resistivity in an AlGaAs/InGaAs pseudomorphic high electron mobility transistor was investigated. The Au/Ge/Ni/Au Ohmic contact formed on the undoped GaAs cap layer yields the lowest contact resistivity of 3.8×10−6 Ω cm2. Meanwhile, the contact resistivity increases a little to 5.0×10−6 Ω cm2 for the contacts formed on an n-Al0.23Ga0.77As layer exposed by removing the undoped cap layer. Both contact resistivities are comparable to those obtained using the n+-GaAs cap layer. The good Ohmic contacts obtained independent of removal of the undoped cap layer are due to the formation of the interfacial compounds, Au2Al and Au2Ga, during annealing. The interfacial compounds penetrate deep into the buried InGaAs channel, resulting in direct contacts to the channel.

The contact resistance degradation mechanism of the Pd/Ge ohmic contact on a pseudomorphic high electron mobility transistor was interpreted. The contact resistance continuously degrades at temperatures higher than 300 °C although no microstructural changes were observed. Meanwhile, elemental Ga atoms were preferentially outdiffused to the PdGe layer and Ge atoms were indiffused to the GaAs during annealing. The indiffused Ge converts the interfacial GaAs layer into n-GaAs, in which Ga vacancies are produced to maintain the charge neutrality condition. The Ga vacancy concentration further increases with annealing temperature, which plays a role in degrading the contact resistance as a result of the recombination of electrons with the Ga vacancies.