1. Demonstration of narrow switching distributions in STTMRAM arrays for LLC applications at 1x nm node
- Author
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C. P. D'Emic, S. L. Brown, E. R. J. Edwards, Gen P. Lauer, Janusz J. Nowak, Jung-hyeon Kim, Hyung-Suk Jung, Thitima Suwannasiri, Guohan Hu, Daniel C. Worledge, Matthias Georg Gottwald, Seonghoon Woo, Pouya Hashemi, Jonathan Z. Sun, and Philip L. Trouilloud
- Subjects
Physics ,Magnetoresistive random-access memory ,Tunnel magnetoresistance ,Magnetoresistance ,business.industry ,Optoelectronics ,Word error rate ,Torque ,Node (circuits) ,Cache ,business ,Voltage - Abstract
We demonstrate spin-transfer torque magnetoresistive random access memory (STT-MRAM) arrays achieving 2.8e-10 write error rate (WER) performance at 3 ns write duration at a magnetic tunnel junction (MTJ) diameter of 40 nm. The bit-to-bit distribution of the write voltage at a WER of 1e-6 is characterized by a relative standard deviation of 3.7% for W0 and 4.5% for W1, sufficient to meet the write voltage distribution requirement for last-level cache (LLC) applications at 1x nm nodes.
- Published
- 2020
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