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The “Quantum Dot Cellular Automata” or QCA is mainly used to design and simulate ‘3D’ structures for area-occupation, latency and total power reduction of any electronic circuit. At present, this “Nano-technology world” requires less-complex, small-size, high-frequency, fault-tolerant, low-power devices to increase the component-density in a single die. QCA designs are the well-known and optimum alternative of CMOS designs due to its above mentioned advantages. Further, reversible gates can also be formed based on QCA design. Reversible logic not only reduce the complexity of the design but also it can increase the information storage possibility by saving the power and energy. It is capable of reducing the leakage power (‘KTln2’ amount of dissipated energy for every bit can be ignored due to this logic). Cost of any device depends on the delay, power and occupied-area of the device which can be decreased by reversible multilayer (‘3D’) QCA structures. So, this proposed technique has an ability to provide the design for a cost-effective electronic device with good scalability and fault-tolerance. In the present work, we have simulated of an “Arithmetic and Logic Unit” in “QCA Designer” and “Xilinx” software. The first software is used due to the above advantages and here we apply reversible logic (reversible TSG gate with reversible AND-OR gate). This ALU is capable of performing one arithmetic (addition of two inputs) and three logical operations (AND, OR and XOR operations of two inputs) at a time. The TSG gate is used here as a full-adder with two input XOR operation and The reversible AND-OR gate is utilized for getting the AND result and OR result of two inputs. This design is also required a “4:1 MUX” which helps to select the operations properly. Schematic designs of proposed design with calculated values of delay and total power (for different room-temperature) are achieved in our work by using ‘Xilinx’ simulator. The used Verilog coding of our formed-design is also implemented in a “FPGA Board” (“Spartan 3E”) for hardware verification. Our presented circuitry can also continue its functionalities at high-temperature.

Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This paper address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks. Through the design of D-MUX, we uncover a major fallacy in existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented. To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning., Comment: Accepted at IEEE TCAD 2021

Silicon-based optical media present several desirable properties for a wide range of applications. Herein, we propose a novel hybrid integration scheme that combines a silicon photonics platform and a 5.5%--silica planar-lightwave circuit (PLC) platform. By exploiting the performance advantages of each platform, we fabricated a polarization-insensitive low-crosstalk 8 8 silicon photonics switch butt-jointed with a compact 5.5%--silica PLC-based 100-GHz 8-channel arrayed waveguide grating (AWG). The device was driven by a smartphone-sized (9 cm 13.5 cm) control board. The fabricated device exhibits a fiber-to-fiber insertion loss of 12.6 dB, an average polarization-dependent loss of less than 0.57 dB, and less than -40 dB leakage to non-target output ports. We also demonstrate two uses of the proposed device. The first is the DEMUX and Switch operation, in which the spectrally divided light by the AWG is routed to an arbitrary output port by a subsequent switch. The second is the Switch and MUX operation, in which arbitrary wavelengths from arbitrary input ports are merged by the AWG. No spectral degradation was observed in either operation. These results demonstrate the potential of the 5.5%--PLC/silicon photonics hybrid platform for compact, low-power, and fast-switching applications.

This paper presents a selective laser melting (SLM) 3-D printed Ku-band diplexer using dual-mode resonators with high thermal stability. The diplexer is designed using dual-mode dimpled ellipsoid resonators which enables the diplexer mechanically self-supported in fabrication. Hence, the design has higher compatibility with the SLM printing process and the design can be extended to multiplexers with more channels. The excellent thermal stability is benefited from both the 4J36 invar alloy material with a lower coefficient of thermal expansion (C.T.E) as well as the tailored SLM printing process. Electrical and thermal performances of the diplexer are measured, showing that the fabricated diplexer is with average insertion losses of 0.69dB/0.42dB, return losses of >14dB, and centre frequency shifts of 5.62MHz/3.75MHz (

New transmission techniques for short-reach optical transmission applications especially datacenter interconnections are highly expected to break current bandwidth bottleneck, among which mode division multiplexing (MDM) based on few-mode fiber (FMF) is promising by exploring different linearly-polarized (LP) modes or mode groups as spatial transmission channels. However, it has been a great challenge to deal with degenerate modes in FMFs. In this paper, a FMF design utilizing multiple ring perturbations in fiber core to suppress modal crosstalk during fiber transmission is firstly proposed and a 6-LP-mode double-ring-core (DRC) FMF is fabricated with a high minimum refractive index difference (min|neff|) of 1.4910-3 among all the modes. Secondly, a novel degenerate-mode-selective coupler (DMSC) converting each degenerate LPmn mode into the LP11 mode in a two-mode fiber is proposed. Then intensity-modulation/direct-detection (IM/DD) MDM transmission scheme without any digital signal processing (DSP) can be realized utilizing mode multiplexer/demultiplexer (MUX/DEMUX) consisting of cascaded mode-selective couplers (MSC) and DMSCs, in which each degenerate or non-degenerate LP mode is considered as an independent transmission channel. Then based on the proposed DRC-FMF and mode MUX/DEMUX, we demonstrate a 4-LP-mode prototype system using commercial single-mode 10 Gbps SFP + modules and 4K video transceivers without any hardware or software modifications. Finally, the intra-LP-mode dispersion (ILMD) effect in a weakly-coupled FMF is analyzed and a modified fixed-analyzer method is proposed for its measurement. Experimental results show that it may be one of the major impairments for IM/DD MDM transmission.

Mode-locked lasers with low noise performance, such as low timing jitter and relative intensity noise are essential for high-precision applications. In this letter, we demonstrated a 122-MHz all-polarization-maintaining mode-locked Er-doped fiber laser based on a nonlinear amplifying loop mirror. A hybrid component integrating a wavelength division multiplexer and a phase shifter is applied to increase the repetition rate. The relative intensity noise is 0.004% and 0.76% rms (integrated from 1 MHz to 100 Hz) from two output ports. The timing jitter characteristic is measured by the delayed optical heterodyne method. The timing jitter is ~1.9 fs rms (integrated from 1 MHz to 10 Hz) of both two output ports. The origin of the timing jitter of this laser is analyzed numerically based on the well-established theoretical model using the laser’s repetition rate, cavity dispersion, etc.

In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.

We design and experimentally demonstrate an ultra-compact dual-mode mode-division multiplexing (MDM) photonic integrated circuit (PIC), which supports on-chip optical signal mode-order-based routing and mode-independent broadcasting. The MDM circuit is composed of inverse-designed three multiplexers, one 3-dB power splitter, three bends and one crossing based on photonic-crystal-like subwavelength structure. The measured excess loss and crosstalk of the fabricated MDM circuit are lower than 5.9 dB and −13 dB over a 60 nm observable wavelength span, respectively. The experiment results of single-channel 25 Gbit/s optical signal transmission show that only 1.2-dB power penalty is introduced through the MDM circuit at a bit-error-rate of 10−9.

Mode division multiplexing (MDM) has attracted great attention in recent years to increase the network capacity. To apply MDM in data center applications, a low-cost and low power consumption system is desired. In this letter, we utilize 850-nm single-mode VCSEL as the laser source and report mode division multiplexed transmission over a standard single-mode fiber, which is two-mode at 850 nm. Due to the small spot size and low numerical aperture, single-mode VCSEL can be coupled into single-mode fibers with low loss. The mode multiplexer and de-multiplexer devices are designed and fabricated based on fiber mode selective couplers using Hi780 fiber as the 850-nm single-mode launch and receiving fiber and standard single-mode fiber as the few-mode transmission fiber. The MDM system supports two channels, corresponding to the LP01 and LP11 mode in the few-mode transmission fiber. Detailed characterizations of the multiplexer and de-multiplexer are conducted including the insertion loss and crosstalk measurements. System transmission at 25 Gb/s shows error free performance over 1-km standard single- mode fiber for both channels. The utilization of VCSEL and standard single-mode fiber can potentially provide a low-cost solution for MDM systems in data center applications.

The development of devices for communication networks to transmit information has become an active and growing field of research. Multiplexer/demultiplexer (M/D) is one of the basic devices in this field. In this paper, an M/D design is introduced based on the surface plasmon resonance in optical ring resonators. The number of inputs and outputs of M/D is 3 × 1 and 1 × 3, respectively. All parameters of the structure, including radius and width of ring resonators and waveguides, have been evaluated to obtain the optimal response. Also, we used the nonlinear gold property to expand the range of M/D performance and simulated the results for intensities less than 100 MW/cm2. Selectivity in the number of inputs and outputs, controllability using several parameters, all optically, selectivity in operation frequency, nanoscale size, reconfigurability, and integrated capability are the features of this design. In our simulation, we consider transmission and reflection of light in each port based on the finite difference time domain for evaluation of results.

A 3D architecture made up of a CMOS layer combined with a 3D stack of bipolar memristor crossbar arrays provides an innovative approach to hardware support for utilizing the strength of CMOS combined with the strength of memristors. Memristors have been evaluated for implementing a broad spectrum of applications such as memory, computations, hardware-based security primitives, cryptography, etc., and numerous studies have shown that memristors are desirable candidates for such applications. This paper proposes a novel 3D memristive crossbar architecture (i.e., a stack of memristive crossbar arrays built on top of CMOS substrate) with a specific focus on the way of connecting the crossbar arrays to the CMOS layer. The proposed architecture is configurable and allows restructuring crossbar arrays and creating 1D arrays with adjustable sizes. The proposed architecture enables parallel and pipeline computations where data can move or be processed in planes perpendicular to the stacked crossbar arrays. In addition, the proposed architecture is scalable meaning that stacks of crossbar arrays can be connected without additional overhead. This paper shows examples of implementing a full adder, a 4-bit look-ahead carry generator, and an 8-bit multiplexer. Simulations and area, delay, and power analysis demonstrate the behavior of the proposed 3D circuit.

This article presents a hardware- and power-efficient RRAM-based neural network capable of online learning. The network is modularized in consideration of scalability and consists of 11 modules. Each module comprises two 25 × 25 RRAM crossbar arrays, four analog multiplexers, and one neuron chip. A stochastic neuron that performs both quantization and activation of the column current flowing through the RRAM array is used to perform online learning without using the high-resolution analog-to-digital converters and digital-to-analog converters. The impact of the initialization of the RRAM device on the network performance is analyzed and a fast yet effective method of initialization is also presented. The network consists of three fully connected layers with 100 input and 10 output neurons. The two hidden layers are made up of 50 and 25 neurons, respectively, and a total of 13 × 103 synapses are implemented by combining 21 RRAM arrays. The neuron chip, which includes 32 neurons, is fabricated through a 0.18-μm standard CMOS process. The network achieves a classification accuracy of 93.4% for the reduced Modified National Institute of Standards and Technology database (MNIST) dataset and the energy efficiency of 38.1 teraoperations per second per Watt (TOPS/W), the highest efficiency among recently reported state-of-the-art RRAM-based neural networks.

Here a 1×5 microfluidic optical switch using double drives is proposed. It has a simple structure and ignorable polarization dependent loss. First, the switch with the straight waveguide structure ...

A multiplexed electrochemical platform has been designed for electrochemical screening applications, such as bacteria detection. It includes 16x16 electrochemical cell array in a two-electrode mode fabricated by a combination of screen printing, inkjet printing, and flash-light sintering techniques wherein each cell is addressed sequentially by a portable multiplexer potentiostat. This multiplexer unit is capable of making a total of 256 independent voltametric measurements that were validated by performing cyclic voltammetry in two-electrode mode using four different redox mediators: [Fe(CN)(6)](3-)/(4-), FcMeOH, Ru[(NH3)(6)]Cl-3 and K-2[IrCl6]. The smart design and the use of mass production techniques makes the multiplexer device applicable for numerous electrochemical applications including health, food, and environmental monitoring.

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and 22Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

This paper discusses modeling and optimizing the performance of hybrid plasmonic bidirectional coupler which is used as a basic building block in modeling high transmission efficiency of opto-electronic devices such as filter, wavelength division multiplexer, logic gates, and switching matrix with the help of an active material (indium tin oxide) that has an electrically adjustable permittivity. All the proposed devices satisfied high transmission efficiencies at the desired output ports over a suitable wavelength range. The realized structures are characterized and simulated by 3D finite-difference time-domain (FDTD). The components would be useful in the optical interconnection networks, photonic integrated circuits, and signal processing system.

The 4-moduli set residue number system (RNS),{2n+1, 2n−1, 2n+3, 2n−3}, with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.

In this paper, to achieve high-quality filters, nanostructured plasmon resonators are proposed. The structure of proposed resonator is based on metal-dielectric-metal configuration and is designed in the range of 1550-nm telecommunication wavelength. To evaluate the proposed structure, finite-difference time-domain method and analytical method of coupled mode theory have been used. To obtain optimal results, the effects of the number of waveguides as well as the radius of circular and ring waveguides were investigated. The appropriate results will be obtained by considering a strong coupling between the incoming light and the surface plasmon. In addition, two transient and static wave structures have been used to evaluate the structure. The simulation results show that besides filtering behavior of the structure, it is possible to control the surface plasmon propagation speed in the proposed structure. Therefore, it is expected that the proposed structure will be used in many parts of a telecommunication link such as multiplexers.

Polarization and mode division multiplexing are powerful tools for large-capacity parallel optical communications. Dual-polarization and mode-division multiplexed silicon photonic integrated circuit with ultra-small footprint is proposed and experimentally demonstrated. The circuits consist of a mode multiplexer, 3-dB power splitter and two demultiplexers which can simultaneously handle TE0, TE1, TM0 and TM1 mode. Compared with conventional device structure, the device footprint is scaled down via pixelated waveguide meta-structure. The mode multiplexer and the splitter have a footprint of only 6.8 μm × 6 μm and 6 μm × 5.25 μm, respectively. The fabrication tolerance on the nanohole size variations are studied, and the fabricated devices are systematically characterized. The measured insertion losses of the multiplexer and 3-dB power splitter are below 1.4 dB and 4.5 dB for all four modes within the wavelength range from 1530 nm-1570 nm. In the meantime, the measured maximum inter-mode cross talk is below -15 dB over a 30 nm bandwidth. The experimental results also indicate the power imbalance of the splitter is within 0.4 dB from 1530 nm-1570 nm. Since the demonstrated polarization and mode handling devices via pixelated meta-structures occupy significantly smaller chip area than conventional wisdoms, this work shows the potential for large scale and dense integration of polarization and mode division multiplexing system on photonic chip.

As part of the ATLAS experiment’s Phase-II Upgrade, improved trigger hardware and algorithms will be implemented onto a single-level architecture. The global trigger (GT) subsystem is a new firmware (FW)-focused project designed to meet stringent requirements from the high-luminosity runs of the large hadron collider (LHC). The global multiplexer (MUX) is the input aggregating stage of the GT; it performs three main tasks: 1) aggregating data from several sources, connected with more than 2300 input fibers, under different protocols; 2) time-multiplexing the incoming data, to sort the packets per bunch-crossing (BC) events, by compensating the relative skews across the various serial input channels; and 3) transmitting, in a round-robin fashion, the sorted BC data to the global event processor (GEP) array, which is the following stage of the GT subsystem and is composed of 48 nodes, each one processing a single BC event. Two MUX FW prototypes for the Global Feature EXtractor (gFEX, part of the liquid argon calorimeter trigger) inputs have been designed, implemented, and validated on a gFEX production board, for up to 72 input and output channels. A four-channel version has been completed with I/O interfaces and validated in a full-chain design, accepting 8b/10b encoded inputs at 11.2 Gb/s and transmitting at 25.78125 Gb/s under Xilinx Aurora 64b/66b protocol. The total latency has been benchmarked in all of its contributing subcomponents and proven to meet the requirements from the Technical Design Report for the Phase-II Upgrade of the trigger and data acquisition system.

Modern integrated photonic platforms should combine low-loss guiding, spectral flexibility, high light confinement, and close packing of optical components. One of the prominent platforms represents a one-dimensional photonic crystal combined with dielectric nanostructures that manipulate low-loss Bloch surface waves (BSWs). Proper design of nanostructures gives rise to a variety of optical resonances suitable for efficient capturing and controlling light. In this work, we achieve color-selective directional excitation of BSWs mediated by Mie resonances in a semiconductor nanoparticle. We show that a single silicon nanoparticle can be used as a subwavelength multiplexer switching the BSW excitation direction from forward to backward within the 30 nm spectral range with its central wavelength governed by the nanoparticle size. Our work opens a route for the on-demand fabrication of photonic nanocouplers with tailored optical properties and submicron footprint.

A broadband silicon four-mode (de)multiplexer [(De)MUX] is proposed and experimentally demonstrated based on subwavelength gratings (SWGs)-assisted triple-waveguide couplers (TWCs), which can (de)multiplex TE0, TE1, TE2, and TE3 modes. The mode interaction is enhanced, benefitting from both the triple-waveguide coupling and subwavelength structures. The proposed four-mode (De)MUX is composed of three SWG-assisted TWCs connected by three linear tapers. The experimental results show that the 3-dB bandwidths are 100 nm, 76 nm, 90 nm, and 95 nm for the TE0, TE1, TE2, and TE3 modes, respectively. The corresponding insertion losses are 0.2, 1.8, 1.3, and 1.7 dB, and the mode crosstalks are -23.3, -17.7, -15.5, and -17.0 dB at the 1550 nm wavelength. The proposed device can work as a mode-(De)MUX compatible with wavelength division multiplexing (WDM) to increase the transmission capacity of on-chip optical interconnects.

We demonstrate a compact ($367 \times 67 \, \mu {\text{m}}^2$) four-channel wavelength division multiplexer using an arrayed waveguide grating based on multimode interference couplers, and built on a monolithic silicon photonics platform. The design is particularly attractive due to the thin device layer. A semi-numerical approach was used for device design and simulation. Optical measurements were found to be consistent with simulation results. The device channel spacing, 3-dB bandwidth and crosstalk were measured to be 97 GHz, 87 GHz and 9.6 dB, respectively, for the designed wavelength of operation near 1310 nm.

We proposed a new kind of add-drop multiplexer based on $\pi $ phase-shifted antisymmetric Bragg grating ( $\pi $ -ASBG). Light resonance is formed in the $\pi $ -ASBG with mode conversion between backward fundamental transverse electric (TE0) mode and the forward first order transverse electric (T1) mode. With the aid of the TE1 mode generated in the $\pi $ -ASBG, add-drop multiplexer can be designed. As examples, two multiplexer structures based on single- and dual-bus resonator, on silicon-on-insulator (SOI) platform have been studied in detail. Besides, no light is reflected to the input port, if the structure is carefully designed with critical coupling condition satisfied. For the fabricated add-drop multiplexer based on single-bus resonator, the extinction ratio is 23.90 dB and full width at half maximum (FWHM) is 0.33 nm at the through port. For the fabricated add-drop multiplexer based on dual-bus resonator, the extinction ratio is 17.22 dB and FWHM is 0.29 nm at through port. The results show that proposed structures provide a new method to realize add-drop multiplexer and other integrated optical filters for optical communications and sensors.

This article presents a novel quad-ridge cavity resonator to realize a trimode response based on the TE101, TE011, and TE111 modes. The basic structure of the quad-ridge resonator (QRR) contains four ridges located at the center around the cavities. With an appropriate combination of the main parameters (length and width of the resonator and heights of the ridges), the first three TE resonant modes can be flexibly controlled, and each mode can carry the signal of a channel. Compared with a traditional rectangular cavity, the QRR provides more design freedoms for controlling the first three TE resonant modes and features a wider spurious-free window. The electric field distributions of the QRR are thoroughly analyzed to guide the realization of a filtering response. Intracavity coupling is achieved by an all-iris structure, including horizontal and vertical coupling slots with offsets to the cavity center, capable of easy fabrication and assembly. A nine-pole triple-band filter and a 12-pole triplexer are designed and manufactured to validate the concept. A comparison with other reported multiplexers indicates that the proposed triplexer exhibits the advantages of size reduction and high isolation.

Purpose The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power. Design/methodology/approach In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size. Findings This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area. Research limitations/implications To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler. Practical implications The simulation of the planned circuit with notional information established the practical identity of the scheme. Social implications The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. Originality/value The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

As molecular computing materials, information-encoded deoxyribonucleic acid (DNA) strands provide a logical computing process by cascaded and parallel chain reactions. However, the reactions in DNA-based combinational logic computing are mostly achieved through a manual process by adding desired DNA molecules in a single microtube or a substrate. For DNA-based Boolean logic, using microfluidic chips can afford automated operation, programmable control, and seamless combinational logic operation, similar to electronic microprocessors. In this paper, we present a programmable DNA-based microfluidic processing unit (MPU) chip that can be controlled via a personal computer for performing DNA calculations. To fabricate this DNA-based MPU, polydimethylsiloxane was cast using double-sided molding techniques for alignment between the microfluidics and valve switch. For a uniform surface, molds fabricated using a three-dimensional printer were spin-coated by a polymer. For programming control, the valve switch arms were operated by servo motors. In the MPU controlled via a personal computer or smartphone application, the molecules with two input DNAs and a logic template DNA were reacted for the basic AND and OR operations. Furthermore, the DNA molecules reacted in a cascading manner for combinational AND and OR operations. Finally, we demonstrated a 2-to-1 multiplexer and the XOR operation with a three-step cascade reaction using the simple DNA-based MPU, which can perform Boolean logic operations (AND, OR, and NOT). Through logic combination, this DNA-based Boolean logic MPU, which can be operated using programming language, is expected to facilitate the development of complex functional circuits such as arithmetic logical units and neuromorphic circuits.

Reconfigurable and scalable plasmonics demultiplexers have attracted increasing attention due to its potential applications in the nanophotonics. Therefore, here, a novel method to design compact plasmonic wavelength demultiplexers (DEMUXes) is proposed. The designed structures (two, four, and six-channel DEMUXes) consist of symmetrical rectangular resonators (RRs) incorporating metal nano-rod defects (NRDs). In the designed structures, the RRs are laterally coupled to metal–insulator-metal (MIM) waveguides. The wavelengths of the output channels depend on the numbers and radii of the metal NRDs in the RRs. The results obtained from various device geometries, with either a single or multiple output ports, are performed utilizing a single structure, showing real reconfigurability. The finite-difference time-domain (FDTD) method is used for the numerical investigation of the proposed structures. The metal and insulator used for the realization of the proposed DEMUXes are silver and air, respectively. The silver’s permittivity is characterized by the well-known Drude model. The basic plasmonic filter which is used to design plasmonic DEMUXes is a single-mode filter. A single-mode filter is easier to cope with in circuits with higher complexity such as DEMUXes. Also, different structural parameters of the basic filter are swept and their effects on the filter’s frequency response are presented, to provide a better physical insight. Taking into account the compact sizes of the proposed DEMUXes (considering the six-channel DEMUX), they can be used in integrated optical circuits for optical communication purposes.

In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA) architectures including a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. IRredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of a multiplexer-based logic to reduce the number of gates and to achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures. Experimental results show that the hybrid CSLAs lead to lowest area-delay product and energy-delay product among all the proposed and previous designs in a wide range of 8-bit to 128-bit adder size. In fact, 10–48% reduction in area-delay product and 8–65% reduction in energy-delay product are achieved compared to previous designs. Moreover, the hybrid CSLAs outperform the best existing design with respect to all three parameters of area, delay and energy.

Silicon photonics can be used to increase the versatility of wavelength division multiplexing (WDM). Ultra-dense wavelength division multiplexing (uDWDM) shrinks channel spacing between WDM channels to decrease guard bands and increase spectral efficiency. Microring modulators (MRMs) provide a simple solution for uDWDM transmitters - they require no multiplexer/demultiplexer. When used with comb lasers, MRMs provide extremely compact and low power solutions. The spectral efficiency is limited by interchannel interference (ICI) from incomplete isolation of channels. We report an MRM-uDWDM transmitter achieving channel spacing comparable to the symbol rate in each WDM channel, reaching a spectrum occupation of 80%. By choosing the correct operating point, we demonstrate experimentally our fabricated MRM chip design causes no discernable ICI power penalty. To the best of our knowledge, this is the first demonstration of MRM-uDWDM to support such dense channel spacing.

In this modern era, optical technology is used for high-speed processing because photon carries information instead of an electron. In signal processing, multiplexing and demultiplexing are the most valuable component. In this communication, designs of frequency encoded 2:1 multiplexer and 1:2 demultiplexer with the use of Reflective Semiconductor Optical Amplifier and add/drop multiplexer are devised. These proposed designs work at high-speed due to the high speed switching property of reflective semiconductor optical amplifier. In the multiplexing and demultiplexing system, coded data signals and coded control signals are the most important issues. Here, frequency encoding is opted because frequency is unaltered after reflection, refraction, absorption, etc., and it gives a very good response for long-distance transmission of processed data. The operation of devised designs has also been verified through MATLAB Simulink (R2018a) software.

This paper demonstrates a hardware encryption algorithm that can be integrated directly with sensors on the same chip. In contrast to using power-hungry microprocessors and software implementations, the encryption algorithm was based on a Lorenz chaotic system and was implemented as time scaling chaotic shift keying (TS-CSK). The coupled differential equations of TS-CSK were implemented using low power integrators, multiplexers, switches, and passive components. Both a single-ended and differential system was developed. The single-ended based system showed no oscillation, while the differential based system demonstrated oscillation. Experimental measurements of the differential system with an integrated temperature sensor demonstrated the ability to encrypt and decrypt the transmitted signal. The differential encryption/decryption system was implemented in 180 nm technology and operated with a 1.8 V power supply and 1.5 mW of power.

This paper presents an improved 8 × 8-bit Booth multiplier with reduced power, delay and area. The major operations that consume power and are responsible for larger critical path delays in Booth multiplication are partial product array generation (PPAG), partial product array compression (PPAC) and partial product array addition (PPAA), for the generation of the final product. So, in our proposed multiplication framework, the design improvements are focused on B-to-C, PPAG, PPAC and PPAA. For speed-power improvement in PPAG operations, an improved circuit for binary-to-two’s complement converter has been proposed to provide a lower critical path delay. Secondly, for power-area improvement, we have proposed a new scheme to generate the first term for all PPAs, the encoder for the generation of the first partial product array (PPA) and modified encoders for third PPA. This results in reduced multiplexer sizes, leading to lower power consumption and lower delays during PPAG. For speed-power improvement in the partial product array addition (PPAA), the carry save addition scheme without carry propagation has been proposed for the reduction of partial product arrays that speeds up the PPAC operation. For the final addition of the last two operands, i.e. PPAA, an n-bit adder segment is designed for our proposed 13-bit modified carry select adder (MCSA) that provides a major contribution in the speed-power and area efficiency of the proposed Booth multiplier architecture. The proposed architecture along with some recently reported state-of-the-art architectures is implemented in 1P-9 M Low K 90-nm CMOS technology, and simulations are carried out using Cadence Virtuoso using 500 MHz clock pulse frequency at a temperature of 27 °C using supply voltage of 1.25 V, for comparison purposes. The proposed multiplier provides an improvement of 26.12% in delay, 32.9% improvement in power-delay product and 32.36% improvement in area-delay product, as compared to the recent designs.

We demonstrate a dual-band two-mode (de)-multiplexer based on tapered asymmetric directional coupler (ADC). The working principle of the device relies on the conversion of the fundamental transverse electric (TE0) mode to the first order (TE1) mode. A phase-matching condition is applied across the O- and C-bands to broaden the operation wavelength of the device. Measurement performed on a mode division multiplexing (MDM) link formed by a back-to-back connected multiplexer and demultiplexer exhibited an insertion loss of less than 1.2 dB with cross talk better than 16 dB. The response is recorded over dual-bands, each with 100-nm bandwidth covering 1260-1360 nm and 1500–1600 nm (extends to the near L-band). The device is compact with an overall length of 75 μm.

Polymer waveguides are considered to be good candidates for optical interconnects application due to their advantages such as flexibility, good compatibility, and versatility for realizing 3D and micro structures. However, constrained by the limited degrees of freedom provided by template-based design approaches, there lacks a satisfying solution which achieves small footprint and low loss simultaneously. Inverse design has been proposed to improve the performance. However, most inverse design methods target at silicon-based optical devices optimization which has a relatively high refractive index difference. In this paper, we demonstrate an ultra-compact low loss polymer wavelength (de)multiplexer with spot-size conversion structure to interposing Si and optical fiber using gradient-based topology optimization and downhill simplex method. The 2-channel wavelength (de)multiplexer displays an excess propagation loss of 0.84 dB and 1.06 dB at 1310 nm and 1550 nm, respectively, with a total footprint of 245 × 35 $\mu$m$^2$. The 4-channel wavelength (de)multiplexer for coarse wavelength division multiplexing applications with 20 nm spacing (1270, 1290, 1310, and 1330 nm) with an excess waveguide propagation loss of 1.72 dB within 271 × 50 $\mu$m$^2$ has also been demonstrated and all the output ports of the polymer wavelength demultiplexing structure achieved a conversion efficiency over 90%.

The optical components based on photonic crystal had a wide range of applications fields these last years. In this work, we propose a configuration of photonic crystal structure of Channel Drop Filter (CDF). The proposed filter study by finite difference numerical method in the time domain FDTD makes it possible to ensure an average detected modal transmission rate of 95.30%, an average quality factor of order 3149.12 and a compact size of 144.65 μm2 with high sensitivity to small variation of refractive index, period and radius of rods. Thus, we designed demultiplexer with four channels, which has a low average crosstalk of −30.73 dB. The transmission and the quality factor are 90.94% and 2221.13 respectively, with channel spacing 4.2 nm and a size of 405.6 μm2. These properties make our model of the proposed filter and demultiplexer well adapted for the realization of optical integrated circuit.

A broadband mode (de)multiplexer [(De)MUX] is proposed and experimentally demonstrated based on a triple-waveguide coupler (TWC) with the phase-matching of a multimode access-waveguide. The tolerance to the operating wavelength and fabrication error of the proposed mode (De)MUX can be relaxed with the aid of the wider access-waveguide and the middle waveguide. The optimized mode (De)MUX is with a coupling length of $48~\mu $ m and a broad bandwidth of >122 nm with the mode crosstalk of

The design of a novel 1 × M fold-back type wavelength selective switch (WSS), which has fewer waveguide crossings than a conventional integrated WSS, is reported. The WSS is composed of interleavers, 1 × M optical switches, and arrayed waveguide gratings (AWGs). Switches are combined with AWGs by fold-back waveguides, and each AWG works as both a demultiplexer and multiplexer thus avoiding center wavelength mismatch caused by fabrication errors. Waveguide crossings cause excess crosstalk and loss in lightwave circuits. By using a fold-back architecture the number of crossings can be reduced to less than half that of a conventional design. We discuss the operating principle, the design method, and the scalability of the fold-back type WSS. Furthermore, the switching operation of a 200-GHz spacing, 20-channel, 1 × 2 silicon WSS in a fold-back configuration on a 5 mm × 10 mm SOI chip is demonstrated. This has 15 waveguide crossings in a path, of which six are additional crossings with monitor waveguides. The average insertion loss and average extinction ratio are 29.6 dB and 10.9 dB, respectively.

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m.

Logic locking is a new technique to prevent an integrated circuit from hardware Trojan, piracy, overbuilding, etc. Most of the well-known logic locking techniques are vulnerable to sensitization and cone based attacks. Though the existing techniques try to thwart these attacks, they are highly circuit topology dependent and require significant overhead. Therefore, this paper presents a new lightweight logic locking technique that effectively neutralizes the sensitization and cone based attacks. We further propose new multi key-input gates and a new replacement-based logic locking algorithm. The replacement of design gates with our multi key-input gates not only effectively prevents the key-sensitization and signal probability skew based removal attacks but also removes rare nets from design. On the other hand, our logic locking algorithm significantly increases the brute-force attempts against cone-based attack with minimum replacements by replacing the nodes which have the maximum number of fan-outs and paths to output nodes. We evaluate our technique using ISCAS benchmarks, and the results demonstrate that the proposed key-gates on average reduce 32 percent area-overhead over the XOR/MUX key-gates, whereas our algorithm on average doubles the effective key size while reducing 50 percent area overhead over the best-known technique.

A microwave resonator array is integrated with liquid metal to select an individual resonator response within a resonator array, enabling simple and accurate analysis for dielectric sensing. Galinstan, a liquid metal, acts as a multiplexer by inducing a capacitive load to the nearby resonator, lowering its resonant frequency, and thereby isolating its resonant response from other resonators in the array. The liquid metal could be positioned within a fluidic channel to be above any of the resonators, which tuned the resonant frequency from 3.9 to 3.3 GHz where it can be analyzed individually. The resonators showed a consistent response to liquid metal tuning, with tuning error measured below 30 MHz (5%). The sensor also exhibited stable sensitivity to test materials placed on the selected resonator, with a maximum resonant frequency shift of 300 MHz for a dielectric test material (ε = 10.2) and almost no variation in resonant amplitude. The selected resonant response was only sensitive to materials on the selected resonator, and was unaffected by test materials, even when placed on other resonators. The presented design enabled robust and accurate detection of materials using planar microwave resonators that can be controlled at a user’s convenience, specifically for use in systems where multiple parameters or system settings may need to be individually determined.

The aim of this research paper is to provide a general overview of Mux and Demux. This research paper starts with a brief description of these electronic devices. A multiplexer, also known as a data selector, is a system that can merge two or more data lines into a single data line for transmission to another venue. A demultiplexer, also known as a data distributor, is a device that divides a single, multiplexed data transmission line into individual data signals. This article addresses the 1 to 4 multiplexer and demultiplexer. Various applications of mux and demux in the fields of telephone and satellite communication, as well as uses of computer science, are discussed.

This article presents a methodological technology for studying digital logic devices. Recommendations on the technology of teaching digital logic devices using rational, best methodological methods and teaching techniques are given. The proposed topic is "Multiplexer and demultiplexer". Studying methods used: modular studying, developmental studying, demonstration (frontal), step-by-step studying, problem-based studying. The process of implementing learning technology explained by the plan prepared for the lesson (mostly the basics of electronics in Kazakhstan are not included into the educational basis of the school and are only taught in higher educational institutions, therefore, the basic learning range, conventionally referred to in the lesson plan, seminars or lectures.

A novel plasmonic unidirectional coupler and its extension to a multiplexer/demultiplexer are proposed and simulated. The proposed structure can be etched adjacent to metal-insulator-metal (MIM) waveguides which can result in considerable reduction in footprint of optical signal processing systems. Simulated results show very good agreement with design. Extinction ratio (ER) of more than 11 dB was achieved for both the coupler as well as the multiplexer/demultiplexer. Crosstalk as well as full width at half maximum (FWHM) was also highly acceptable for the multiplexer/demultiplexer. The proposed structures have an additional attractive feature of being amenable to integration with other relevant functionalities as demonstrated in the results.

Tremendous and inescapable application of full adder adds impetus to its optimization till high-end performance. Use of full adder propels the design engineer to unearth various digital circuits, whose implementation otherwise would not be a cakewalk. This paper exhumes finest 3-bit parity checker in terms of power dissipation (PWR) and energy-delay product (EDP) variability. MCML (MOS Current Mode Logic) based implementation is practiced to improvise the circuit. Further, in this treatise, above mentioned 'CNFET-based 3-bit MCML parity checker' (used as full adder) and Transmission Gate based multiplexer is used to implement a novel design of '4-Bit 4-Tube CNFET based ALU' at 16-nm Technology Node. This CNFET-based ALU thus implemented is further compared with its CMOS counterpart. Simulation results establish the superior performance of proposed '4-Bit 4-Tube CNFET-based ALU' in terms of propagation delay (tp) (9.04×), PWR (1.68×), PDP (15.09×) and EDP (136.42×). The exposition establishes that the idea of using a 'CNFET-based 3-bit MCML parity checker' to design a new ALU circuit, i.e., '4-Bit 4-Tube CNFET-based ALU' would provide a gigantic horizon for a design engineer.

The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and selects the lower metric value as a survivor path. SMU stores the data bits which utilizes the trace back method to fetch the likelihood path from the current state to a previous state. An ACS unit is an essential block for VD. The basic recursive ACSU design consists of Ripple Carry Adder (RCA), Comparator and a Selector block, which consume more area, power and operates with high junction temperature. To overcome these drawbacks, a modified ACSU design is implemented with recursive cancellation technique. ACS unit is modified by including a trace back mechanism to obtain a low latency and high speed in VD. It is designed with low complexity multiplexers, adders, logical AND gate and comparator block. This breaking recursive ACSU design utilizes less power, high throughput, low latency and also operates at low temperature. This analysis and simulation process are accomplished using Vivado Design Suite.